diff --git a/fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci b/fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci
index 7940858f3..a9afd1f74 100644
--- a/fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci
+++ b/fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci
@@ -88,7 +88,7 @@
0
1
8
- 16
+ 4
1
0
1
@@ -100,17 +100,17 @@
1
1
0
- 1
+ 0
0
0
0
0
kintex7
- 16
+ 256
axi_quad_spi_inst
1
8
- 16
+ 4
1
0
0
@@ -122,8 +122,8 @@
0x00000000
0
1
- 1
- 1
+ 0
+ 0
0
axi_quad_spi_0
1
@@ -156,6 +156,7 @@
+
diff --git a/fpga/constraints/genesys-2.xdc b/fpga/constraints/genesys-2.xdc
index 261588cf9..d90fbb25b 100644
--- a/fpga/constraints/genesys-2.xdc
+++ b/fpga/constraints/genesys-2.xdc
@@ -44,3 +44,8 @@ set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
+
+set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports spi_clk_o_2]
+set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports spi_ss_2]
+set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports spi_miso_2]
+set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports spi_mosi_2]
diff --git a/fpga/src/ariane_peripherals.sv b/fpga/src/ariane_peripherals.sv
index 6423b30e7..5bf40867f 100644
--- a/fpga/src/ariane_peripherals.sv
+++ b/fpga/src/ariane_peripherals.sv
@@ -13,21 +13,20 @@ module ariane_peripherals #(
parameter AxiAddrWidth = -1,
parameter AxiDataWidth = -1
) (
- input logic clk_i , // Clock
- input logic rst_ni , // Asynchronous reset active low
- AXI_BUS.in plic ,
- AXI_BUS.in uart ,
- AXI_BUS.in spi ,
- output logic [1:0] irq_o ,
+ input logic clk_i , // Clock
+ input logic rst_ni , // Asynchronous reset active low
+ AXI_BUS.in plic ,
+ AXI_BUS.in uart ,
+ AXI_BUS.in spi ,
+ output logic [1:0] irq_o ,
// UART
- input logic rx_i ,
- output logic tx_o ,
+ input logic rx_i ,
+ output logic tx_o ,
// SPI
- output logic spi_clk_o ,
- output logic spi_mosi ,
- input logic spi_miso ,
- output logic spi_ss ,
- output logic spi_ip2intc_irtp
+ output logic spi_clk_o,
+ output logic spi_mosi ,
+ input logic spi_miso ,
+ output logic spi_ss
);
// ---------------
@@ -469,12 +468,10 @@ module ariane_peripherals #(
.ss_i ('0 ),
.ss_o (spi_ss ),
.ss_t ('0 ),
- .ip2intc_irpt (spi_ip2intc_irtp ),
-
- .cfgclk (spi_clk_o ), // output wire cfgclk
- .cfgmclk ( ), // output wire cfgmclk
- .eos ( ), // output wire eos
- .preq ( ) // output wire preq
+ .ip2intc_irpt (irq_sources[1] ),
+ .sck_i ('0 ),
+ .sck_o (spi_clk_o ),
+ .sck_t ('0 )
);
diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv
index 4641b3f6e..da6073187 100644
--- a/fpga/src/ariane_xilinx.sv
+++ b/fpga/src/ariane_xilinx.sv
@@ -10,44 +10,44 @@
// Top-level for Genesys 2
module ariane_xilinx (
- input logic cpu_resetn,
- input logic sys_clk_p,
- input logic sys_clk_n,
- inout logic [31:0] ddr3_dq,
- inout logic [3:0] ddr3_dqs_n,
- inout logic [3:0] ddr3_dqs_p,
- output logic [14:0] ddr3_addr,
- output logic [2:0] ddr3_ba,
- output logic ddr3_ras_n,
- output logic ddr3_cas_n,
- output logic ddr3_we_n,
- output logic ddr3_reset_n,
- output logic [0:0] ddr3_ck_p,
- output logic [0:0] ddr3_ck_n,
- output logic [0:0] ddr3_cke,
- output logic [0:0] ddr3_cs_n,
- output logic [3:0] ddr3_dm,
- output logic [0:0] ddr3_odt,
-
- input logic tck,
- input logic tms,
- input logic trst_n,
- input logic tdi,
- output logic tdo,
-
- input logic rx,
- output logic tx,
-
- output logic [7:0] led,
- input logic [7:0] sw,
- output logic fan_pwm,
-
- // SPI
- output logic spi_mosi,
- input logic spi_miso,
- output logic spi_ss,
- output logic spi_clk_o
- //output logic spi_ip2intc_irtp
+ input logic cpu_resetn ,
+ input logic sys_clk_p ,
+ input logic sys_clk_n ,
+ inout logic [31:0] ddr3_dq ,
+ inout logic [ 3:0] ddr3_dqs_n ,
+ inout logic [ 3:0] ddr3_dqs_p ,
+ output logic [14:0] ddr3_addr ,
+ output logic [ 2:0] ddr3_ba ,
+ output logic ddr3_ras_n ,
+ output logic ddr3_cas_n ,
+ output logic ddr3_we_n ,
+ output logic ddr3_reset_n,
+ output logic [ 0:0] ddr3_ck_p ,
+ output logic [ 0:0] ddr3_ck_n ,
+ output logic [ 0:0] ddr3_cke ,
+ output logic [ 0:0] ddr3_cs_n ,
+ output logic [ 3:0] ddr3_dm ,
+ output logic [ 0:0] ddr3_odt ,
+ input logic tck ,
+ input logic tms ,
+ input logic trst_n ,
+ input logic tdi ,
+ output logic tdo ,
+ input logic rx ,
+ output logic tx ,
+ output logic [ 7:0] led ,
+ input logic [ 7:0] sw ,
+ output logic fan_pwm ,
+ // SPI
+ output logic spi_mosi ,
+ input logic spi_miso ,
+ output logic spi_ss ,
+ output logic spi_clk_o ,
+ output logic spi_mosi_2 ,
+ output logic spi_miso_2 ,
+ output logic spi_ss_2 ,
+ output logic spi_clk_o_2
+ //output logic spi_ip2intc_irtp
);
localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data
@@ -79,6 +79,12 @@ AXI_BUS #(
.AXI_USER_WIDTH ( AxiUserWidth )
) master[ariane_soc::NB_PERIPHERALS-1:0]();
+// spi hack
+assign spi_mosi_2 = spi_mosi;
+assign spi_miso_2 = spi_miso;
+assign spi_clk_o_2 = spi_clk_o;
+assign spi_ss_2 = spi_ss;
+
// disable test-enable
logic test_en;
logic ndmreset;
@@ -88,6 +94,7 @@ logic time_irq;
logic ipi;
logic clk;
+logic spi_clk_i;
logic ddr_sync_reset;
logic ddr_clock_out;
@@ -413,22 +420,21 @@ bootrom i_bootrom (
// Peripherals
// ---------------
ariane_peripherals #(
- .AxiAddrWidth(AxiAddrWidth),
- .AxiDataWidth(AxiDataWidth)
+ .AxiAddrWidth(AxiAddrWidth),
+ .AxiDataWidth(AxiDataWidth)
) i_ariane_peripherals (
- .clk_i (clk ),
- .rst_ni (ndmreset_n ),
- .plic (master[ariane_soc::PLIC]),
- .uart (master[ariane_soc::UART]),
- .spi (master[ariane_soc::SPI] ),
- .irq_o (irq ),
- .rx_i (rx ),
- .tx_o (tx ),
- .spi_clk_o (spi_clk_o ),
- .spi_mosi (spi_mosi ),
- .spi_miso (spi_miso ),
- .spi_ss (spi_ss ),
- .spi_ip2intc_irtp( )
+ .clk_i (clk ),
+ .rst_ni (ndmreset_n ),
+ .plic (master[ariane_soc::PLIC]),
+ .uart (master[ariane_soc::UART]),
+ .spi (master[ariane_soc::SPI] ),
+ .irq_o (irq ),
+ .rx_i (rx ),
+ .tx_o (tx ),
+ .spi_clk_o(spi_clk_o ),
+ .spi_mosi (spi_mosi ),
+ .spi_miso (spi_miso ),
+ .spi_ss (spi_ss )
);
// ---------------------
diff --git a/tb/ariane_soc_pkg.sv b/tb/ariane_soc_pkg.sv
index 7f0277006..1f040656a 100644
--- a/tb/ariane_soc_pkg.sv
+++ b/tb/ariane_soc_pkg.sv
@@ -14,7 +14,7 @@ package ariane_soc;
localparam NB_PERIPHERALS = 7;
localparam NumTargets = 2;
- localparam NumSources = 1;
+ localparam NumSources = 2;
typedef enum int unsigned {
DRAM = 0,