diff --git a/corev_apu/tb/common/tb_amoport.sv b/corev_apu/tb/common/tb_amoport.sv index 7d53b4450..18a59636f 100644 --- a/corev_apu/tb/common/tb_amoport.sv +++ b/corev_apu/tb/common/tb_amoport.sv @@ -17,10 +17,11 @@ `include "tb.svh" program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter string PortName = "atomics port 0", parameter MemWords = 1024*1024,// in 64bit words - parameter logic [63:0] CachedAddrBeg = 0, - parameter logic [63:0] CachedAddrEnd = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrBeg = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrEnd = 0, parameter RndSeed = 1110, parameter Verbose = 0 ) ( @@ -35,9 +36,9 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( output logic seq_done_o, // expresp interface - input logic [63:0] act_mem_i, - input logic [63:0] exp_mem_i, - input logic [63:0] exp_result_i, + input logic [CVA6Cfg.XLEN-1:0] act_mem_i, + input logic [CVA6Cfg.XLEN-1:0] exp_mem_i, + input logic [CVA6Cfg.XLEN-1:0] exp_result_i, // interface to DUT output amo_req_t dut_amo_req_port_o, @@ -55,8 +56,8 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( /////////////////////////////////////////////////////////////////////////////// task automatic applyAtomics(); - automatic logic [63:0] paddr; - automatic logic [63:0] data; + automatic logic [CVA6Cfg.XLEN-1:0] paddr; + automatic logic [CVA6Cfg.XLEN-1:0] data; automatic logic [1:0] size; automatic amo_t amo_op; automatic logic [63:0] delay; @@ -83,7 +84,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( void'(randomize(amo_op) with {!(amo_op inside {AMO_NONE, AMO_CAS1, AMO_CAS2});}); void'(randomize(data)); if (riscv::XLEN == 64) - void'(randomize(size) with {size >= 2; size <= 3;}); + void'(randomize(size) with {size >= 2; size <= $clog2(CVA6Cfg.XLEN/8);}); else size = 'h2; @@ -94,7 +95,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( if (amo_op inside {AMO_LR, AMO_SC}) void'(randomize(paddr) with {paddr >= 8; paddr < 12;}); else - void'(randomize(paddr) with {paddr >= 8; paddr < (MemWords<<3);}); + void'(randomize(paddr) with {paddr >= 8; paddr < (MemWords<<$clog2(CVA6Cfg.XLEN/8));}); // Align adress if (size == 2) @@ -163,7 +164,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( progress status; string failingTests, tmpstr0, tmpstr1, tmpstr2; int n; - logic [63:0] exp_res; + logic [CVA6Cfg.XLEN-1:0] exp_res; status = new(PortName); failingTests = ""; @@ -189,7 +190,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( // Assert expected data is not 'x, protects against ineffective ==? comparisons assert(exp_result_i !== 'x) else $error("Expected result is unknown"); // note: wildcard as defined in right operand! - ok=(dut_amo_resp_port_i.result ==? exp_result_i) && (act_mem_i == exp_mem_i); + ok=(dut_amo_resp_port_i.result[CVA6Cfg.XLEN-1:0] ==? exp_result_i) && (act_mem_i == exp_mem_i); if(Verbose | !ok) begin tmpstr0 = $psprintf("vector: %02d - %06d -- paddr: %16X -- AMO: 0x%2X -- size: %X -- op_a: %16X -- op_b: %16X", diff --git a/corev_apu/tb/common/tb_readport.sv b/corev_apu/tb/common/tb_readport.sv index 35b993061..486cfb48b 100644 --- a/corev_apu/tb/common/tb_readport.sv +++ b/corev_apu/tb/common/tb_readport.sv @@ -20,15 +20,18 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter string PortName = "read port 0", parameter FlushRate = 1, parameter KillRate = 5, parameter TlbHitRate = 95, parameter MemWords = 1024*1024,// in 64bit words - parameter logic [63:0] CachedAddrBeg = 0, - parameter logic [63:0] CachedAddrEnd = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrBeg = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrEnd = 0, parameter RndSeed = 1110, - parameter Verbose = 0 + parameter Verbose = 0, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -45,11 +48,11 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( output logic seq_done_o, // expresp interface - output logic [63:0] exp_paddr_o, - input logic [1:0] exp_size_i, - input logic [riscv::XLEN-1:0] exp_rdata_i, - input logic [63:0] exp_paddr_i, - input logic [63:0] act_paddr_i, + output logic [CVA6Cfg.PLEN-1:0] exp_paddr_o, + input logic [1:0] exp_size_i, + input logic [CVA6Cfg.XLEN-1:0] exp_rdata_i, + input logic [CVA6Cfg.PLEN-1:0] exp_paddr_i, + input logic [CVA6Cfg.PLEN-1:0] act_paddr_i, // interface to DUT output logic flush_o, @@ -62,7 +65,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( timeunit 1ps; timeprecision 1ps; - logic [63:0] paddr; + logic [CVA6Cfg.PLEN-1:0] paddr; logic seq_end_req, seq_end_ack, prog_end; logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_q; logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_vld_q; @@ -74,7 +77,8 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( // // TODO: add randomization initial begin : p_tag_delay - logic [63:0] tmp_paddr, val; + logic [CVA6Cfg.PLEN-1:0] tmp_paddr; + logic [CVA6Cfg.XLEN-1:0] val; int unsigned cnt; logic tmp_vld; @@ -142,7 +146,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( task automatic genRandReq(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; automatic logic [1:0] size; void'($urandom(RndSeed)); @@ -170,8 +174,8 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( if(val < req_rate_i) begin dut_req_port_o.data_req = 1'b1; // generate random address - void'(randomize(val) with {val >= 0; val < (MemWords<<3);}); - void'(randomize(size)); + void'(randomize(val) with {val >= 0; val < (MemWords<<$clog2(CVA6Cfg.XLEN/8));}); + void'(randomize(size) with {size <= $clog2(CVA6Cfg.XLEN/8);}); dut_req_port_o.data_size = size; paddr = val; @@ -198,7 +202,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( endtask : genRandReq task automatic genSeqRead(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; @@ -206,10 +210,10 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( val = '0; while(~seq_end_req) begin dut_req_port_o.data_req = 1'b1; - dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_size = $clog2(CVA6Cfg.XLEN/8); paddr = val; // generate linear read - val = (val + 8) % (MemWords<<3); + val = (val + CVA6Cfg.XLEN/8) % (MemWords<<$clog2(CVA6Cfg.XLEN/8)); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end @@ -220,7 +224,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( // Generate a sequence of reads to the same set (constant index) task automatic genSetSeqRead(); - automatic logic [63:0] val, rnd; + automatic logic [CVA6Cfg.XLEN-1:0] val, rnd; paddr = CachedAddrBeg + 2 ** CVA6Cfg.DCACHE_INDEX_WIDTH; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; @@ -230,12 +234,12 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( void'(randomize(rnd) with {rnd > 0; rnd <= 100;}); if(rnd < req_rate_i) begin dut_req_port_o.data_req = 1'b1; - dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_size = $clog2(CVA6Cfg.XLEN/8); paddr = val; // generate linear read `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) // increment by set size - val = (val + 2 ** CVA6Cfg.DCACHE_INDEX_WIDTH) % (MemWords<<3); + val = (val + 2 ** CVA6Cfg.DCACHE_INDEX_WIDTH) % (MemWords<<$clog2(CVA6Cfg.XLEN/8)); end `APPL_WAIT_CYC(clk_i,1) dut_req_port_o.data_req = '0; @@ -246,7 +250,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( endtask : genSetSeqRead task automatic genWrapSeq(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; paddr = CachedAddrBeg; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; @@ -254,11 +258,11 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( val = '0; while(~seq_end_req) begin dut_req_port_o.data_req = 1'b1; - dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_size = $clog2(CVA6Cfg.XLEN/8); paddr = val; // generate wrapping read of 1 cachelines paddr = CachedAddrBeg + val; - val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); + val = (val + CVA6Cfg.XLEN/8) % (1*(CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.XLEN)*(CVA6Cfg.XLEN/8)); // <=> /8 `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end @@ -341,7 +345,8 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( progress status; string failingTests, tmpstr1, tmpstr2; int n; - logic [63:0] exp_rdata, exp_paddr; + logic [CVA6Cfg.XLEN-1:0] exp_rdata; + logic [CVA6Cfg.PLEN-1:0] exp_paddr; logic [1:0] exp_size; status = new(PortName); @@ -378,7 +383,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #( if(Verbose | !ok) begin tmpstr1 = $psprintf("vector: %02d - %06d -- exp_paddr: %16X -- exp_data: %16X -- access size: %01d Byte", - n, k, exp_paddr_i, exp_rdata, 2**exp_size_i); + n, k, exp_paddr_i, exp_rdata_i, 2**exp_size_i); tmpstr2 = $psprintf("vector: %02d - %06d -- act_paddr: %16X -- act_data: %16X -- access size: %01d Byte", n, k, act_paddr_i, dut_req_port_i.data_rdata, 2**exp_size_i); $display("%s> %s", PortName, tmpstr1); diff --git a/corev_apu/tb/common/tb_writeport.sv b/corev_apu/tb/common/tb_writeport.sv index beae49ed0..46cb36287 100644 --- a/corev_apu/tb/common/tb_writeport.sv +++ b/corev_apu/tb/common/tb_writeport.sv @@ -19,12 +19,15 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter string PortName = "write port 0", parameter MemWords = 1024*1024,// in 64bit words - parameter logic [63:0] CachedAddrBeg = 0, - parameter logic [63:0] CachedAddrEnd = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrBeg = 0, + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrEnd = 0, parameter RndSeed = 1110, - parameter Verbose = 0 + parameter Verbose = 0, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -47,7 +50,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( timeunit 1ps; timeprecision 1ps; - logic [63:0] paddr; + logic [CVA6Cfg.PLEN-1:0] paddr; assign dut_req_port_o.address_tag = paddr[CVA6Cfg.DCACHE_TAG_WIDTH+CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_INDEX_WIDTH]; assign dut_req_port_o.address_index = paddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; @@ -59,11 +62,11 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( task automatic applyRandData(); - automatic logic [63:0] val; - automatic logic [7:0] be; + automatic logic [CVA6Cfg.XLEN-1:0] val; + automatic logic [CVA6Cfg.XLEN/8-1:0] be; automatic logic [1:0] size; - void'(randomize(size)); + void'(randomize(size) with {size <= $clog2(CVA6Cfg.XLEN/8);}); // align to size, set correct byte enables be = '0; unique case(size) @@ -77,7 +80,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( void'(randomize(val)); - for(int k=0; k<8; k++) begin + for(int k=0; k= 0; paddr < (MemWords<<3);}); + void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<$clog2(CVA6Cfg.XLEN/8));}); applyRandData(); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) end @@ -124,7 +127,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( endtask : genRandReq task automatic genSeqWrite(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; @@ -133,12 +136,12 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( val = '0; repeat(seq_num_vect_i) begin dut_req_port_o.data_req = 1'b1; - dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_size = $clog2(CVA6Cfg.XLEN/8); dut_req_port_o.data_be = '1; dut_req_port_o.data_wdata = val; paddr = val; // generate linear read - val = (val + 8) % (MemWords<<3); + val = (val + CVA6Cfg.XLEN/8) % (MemWords<<$clog2(CVA6Cfg.XLEN/8)); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end @@ -151,7 +154,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( // Repeadedly write to the same address task automatic genConstWrite(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; paddr = CachedAddrBeg; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; @@ -160,7 +163,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( repeat(seq_num_vect_i) begin void'(randomize(val)); dut_req_port_o.data_req = 1'b1; - dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_size = $clog2(CVA6Cfg.XLEN/8); dut_req_port_o.data_be = '1; dut_req_port_o.data_wdata = val; `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) @@ -174,7 +177,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( endtask : genConstWrite task automatic genWrapSeq(); - automatic logic [63:0] val; + automatic logic [CVA6Cfg.XLEN-1:0] val; void'($urandom(RndSeed)); paddr = CachedAddrBeg; @@ -188,7 +191,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( applyRandData(); // generate wrapping read of 1 cacheline paddr = CachedAddrBeg + val; - val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); + val = (val + CVA6Cfg.XLEN/8) % (1*(CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.XLEN)*(CVA6Cfg.XLEN/8)); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end @@ -201,8 +204,8 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( endtask : genWrapSeq task automatic genSeqBurst(); - automatic logic [63:0] val; - automatic logic [7:0] be; + automatic logic [CVA6Cfg.XLEN-1:0] val; + automatic logic [CVA6Cfg.XLEN/8-1:0] be; automatic logic [1:0] size; automatic int cnt, burst_len; @@ -223,16 +226,16 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( if(val < req_rate_i) begin dut_req_port_o.data_req = 1'b1; // generate random address base - void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<3);}); + void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<$clog2(CVA6Cfg.XLEN/8));}); // do a random burst void'(randomize(burst_len) with {burst_len >= 1; burst_len < 100;}); - for(int k=0; k=0 val<=8;};); - paddr += 8; + paddr += CVA6Cfg.XLEN/8; cnt ++; end end diff --git a/corev_apu/tb/tb_wb_dcache/Makefile b/corev_apu/tb/tb_wb_dcache/Makefile index 5877d27e6..81c6d411c 100755 --- a/corev_apu/tb/tb_wb_dcache/Makefile +++ b/corev_apu/tb/tb_wb_dcache/Makefile @@ -17,10 +17,10 @@ toplevel ?= tb src-list := tb.list inc-path := $(shell pwd)/hdl/ src := $(shell xargs printf '\n%s' < $(src-list) | cut -b 1-) -compile_flag += +cover+i_dut -incr -64 -nologo -svinputport=compat -override_timescale 1ns/1ps -suppress 2583 -suppress 13262 +cover +compile_flag += +cover+i_dut -incr -64 -nologo -svinputport=compat -override_timescale 1ns/1ps -suppress 2583 -suppress 13262 -suppress 2986 +cover sim_opts += -64 -coverage -classdebug -voptargs="+acc" questa_version ?= ${QUESTASIM_VERSION} -incdir += ../common/ ../../axi/include/ +incdir += ../common/ ../../../vendor/pulp-platform/axi/include/ # Iterate over all include directories and write them with +incdir+ prefixed # +incdir+ works for Verilator and QuestaSim diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv new file mode 100644 index 000000000..d26138aeb --- /dev/null +++ b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv @@ -0,0 +1,159 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 32; + + localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 0; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 0; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigHExtEn = 0; // always disabled + localparam CVA6ConfigBExtEn = 0; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigRVZiCond = 0; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 32768; + localparam CVA6ConfigDcacheSetAssoc = 8; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheIdWidth = 1; + localparam CVA6ConfigMemTidWidth = 2; + + localparam CVA6ConfigWtDcacheWbufDepth = 8; + + localparam CVA6ConfigSuperscalarEn = 0; + localparam CVA6ConfigNrCommitPorts = 2; + localparam CVA6ConfigNrScoreboardEntries = 8; + + localparam CVA6ConfigFpgaEn = 0; + + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 2; + + localparam CVA6ConfigInstrTlbEntries = 2; + localparam CVA6ConfigDataTlbEntries = 2; + + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + + localparam CVA6ConfigTvalEn = 1; + + localparam CVA6ConfigNrPMPEntries = 8; + + localparam CVA6ConfigPerfCounterEn = 1; + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WB; + + localparam CVA6ConfigMmuPresent = 1; + + localparam CVA6ConfigRvfiTrace = 1; + + // memory configuration (XLEN words) + localparam MemBytes = CVA6ConfigDcacheByteSize / CVA6ConfigDcacheSetAssoc * 4 * 32; + localparam MemWords = MemBytes>>($clog2(CVA6ConfigXlen/8)); + + // noncacheable portion + localparam CachedAddrBeg = MemBytes >> ($clog2(CVA6ConfigXlen/8)); + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + FpgaEn: bit'(CVA6ConfigFpgaEn), + NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVF), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + RVZiCond: bit'(CVA6ConfigRVZiCond), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + DmBaseAddress: 64'h0, + TvalEn: bit'(CVA6ConfigTvalEn), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'(CachedAddrBeg), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(CVA6ConfigInstrTlbEntries), + DataTlbEntries: int'(CVA6ConfigDataTlbEntries), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv new file mode 100644 index 000000000..0633b97eb --- /dev/null +++ b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv @@ -0,0 +1,158 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + + localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 1; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 1; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigBExtEn = 1; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigHExtEn = 0; + localparam CVA6ConfigRVZiCond = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 32768; + localparam CVA6ConfigDcacheSetAssoc = 8; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheIdWidth = 1; + localparam CVA6ConfigMemTidWidth = 2; + + localparam CVA6ConfigWtDcacheWbufDepth = 8; + + localparam CVA6ConfigSuperscalarEn = 0; + localparam CVA6ConfigNrCommitPorts = 2; + localparam CVA6ConfigNrScoreboardEntries = 8; + + localparam CVA6ConfigFpgaEn = 0; + + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 2; + + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + + localparam CVA6ConfigTvalEn = 1; + + localparam CVA6ConfigNrPMPEntries = 8; + + localparam CVA6ConfigPerfCounterEn = 1; + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WB; + + localparam CVA6ConfigMmuPresent = 1; + + localparam CVA6ConfigRvfiTrace = 1; + + // memory configuration (XLEN words) + localparam MemBytes = CVA6ConfigDcacheByteSize / CVA6ConfigDcacheSetAssoc * 4 * 32; + localparam MemWords = MemBytes>>($clog2(CVA6ConfigXlen/8)); + + // noncacheable portion + localparam CachedAddrBeg = MemBytes >> ($clog2(CVA6ConfigXlen/8)); + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + FpgaEn: bit'(CVA6ConfigFpgaEn), + NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVF), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + RVZiCond: bit'(CVA6ConfigRVZiCond), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + DmBaseAddress: 64'h0, + TvalEn: bit'(CVA6ConfigTvalEn), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'(CachedAddrBeg), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage diff --git a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv index 8634a60c2..37e992c22 100644 --- a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv +++ b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv @@ -17,19 +17,20 @@ `include "assign.svh" `include "axi/typedef.svh" -module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()(); +module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #( + // CVA6 config + parameter config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config( + cva6_config_pkg::cva6_cfg + ) +)(); // leave this timeunit 1ps; timeprecision 1ps; - // memory configuration (64bit words) - parameter MemBytes = 2**CVA6Cfg.DCACHE_INDEX_WIDTH * 4 * 32; - parameter MemWords = MemBytes>>3; - // noncacheable portion - parameter logic [63:0] CachedAddrBeg = MemBytes>>3;//1/8th of the memory is NC - parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF; + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrBeg = cva6_config_pkg::CachedAddrBeg; + parameter logic [CVA6Cfg.PLEN-1:0] CachedAddrEnd = {CVA6Cfg.XLEN{1'b1}}; // contention and invalidation rates (in %) parameter MemRandHitRate = 75; @@ -60,6 +61,29 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() parameter time TbTestTime = 8ns; + // D$ data requests + localparam type dcache_req_i_t = struct packed { + logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] address_index; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] address_tag; + logic [CVA6Cfg.XLEN-1:0] data_wdata; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_wuser; + logic data_req; + logic data_we; + logic [(CVA6Cfg.XLEN/8)-1:0] data_be; + logic [1:0] data_size; + logic [CVA6Cfg.DcacheIdWidth-1:0] data_id; + logic kill_req; + logic tag_valid; + }; + + localparam type dcache_req_o_t = struct packed { + logic data_gnt; + logic data_rvalid; + logic [CVA6Cfg.DcacheIdWidth-1:0] data_rid; + logic [CVA6Cfg.XLEN-1:0] data_rdata; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser; + }; + /////////////////////////////////////////////////////////////////////////////// // MUT signal declarations /////////////////////////////////////////////////////////////////////////////// @@ -103,25 +127,26 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() logic tlb_rand_en; logic write_en; - logic [63:0] write_paddr, write_data; + logic [CVA6Cfg.PLEN-1:0] write_paddr; + logic [CVA6Cfg.XLEN-1:0] write_data; logic [7:0] write_be; typedef struct packed { logic [1:0] size; - logic [63:0] paddr; + logic [CVA6Cfg.PLEN-1:0] paddr; } resp_fifo_t; typedef struct packed { logic valid; - logic [63:0] paddr; + logic [CVA6Cfg.PLEN-1:0] paddr; } reservation_t; - logic [63:0] act_paddr[1:0]; - logic [63:0] exp_rdata[1:0]; - logic [63:0] exp_paddr[1:0]; - logic [63:0] amo_act_mem; - logic [63:0] amo_shadow; - logic [63:0] amo_exp_result; + logic [CVA6Cfg.PLEN-1:0] act_paddr[1:0]; + logic [CVA6Cfg.XLEN-1:0] exp_rdata[1:0]; + logic [CVA6Cfg.PLEN-1:0] exp_paddr[1:0]; + logic [CVA6Cfg.XLEN-1:0] amo_act_mem; + logic [CVA6Cfg.XLEN-1:0] amo_shadow; + logic [CVA6Cfg.XLEN-1:0] amo_exp_result; resp_fifo_t fifo_data_in[1:0]; resp_fifo_t fifo_data[1:0]; logic [1:0] fifo_push, fifo_pop, fifo_flush; @@ -152,19 +177,19 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() `AXI_ASSIGN_TO_RESP(axi_bypass_i, axi_bypass_dv) typedef tb_mem_port #( - .AW ( TbAxiAddrWidthFull ), - .DW ( TbAxiDataWidthFull ), - .IW ( TbAxiIdWidthFull + 32'd1 ), - .UW ( TbAxiUserWidthFull ), - .TA ( TbApplTime ), - .TT ( TbTestTime ), - .AX_MIN_WAIT_CYCLES ( 0 ), - .AX_MAX_WAIT_CYCLES ( 50 ), - .R_MIN_WAIT_CYCLES ( 10 ), - .R_MAX_WAIT_CYCLES ( 20 ), - .RESP_MIN_WAIT_CYCLES ( 10 ), - .RESP_MAX_WAIT_CYCLES ( 20 ), - .MEM_BYTES ( MemBytes ) + .AW ( TbAxiAddrWidthFull ), + .DW ( TbAxiDataWidthFull ), + .IW ( TbAxiIdWidthFull + 32'd1 ), + .UW ( TbAxiUserWidthFull ), + .TA ( TbApplTime ), + .TT ( TbTestTime ), + .AX_MIN_WAIT_CYCLES ( 0 ), + .AX_MAX_WAIT_CYCLES ( 50 ), + .R_MIN_WAIT_CYCLES ( 10 ), + .R_MAX_WAIT_CYCLES ( 20 ), + .RESP_MIN_WAIT_CYCLES ( 10 ), + .RESP_MAX_WAIT_CYCLES ( 20 ), + .MEM_BYTES ( cva6_config_pkg::MemBytes ) ) tb_mem_port_t; tb_mem_port_t data_mem_port; @@ -258,7 +283,7 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() // listen to the write/AMO ports and keep shadow memory up-to-date initial begin : p_mem - automatic logic[63:0] amo_result, amo_op_a, amo_op_b, amo_op_a_u, amo_op_b_u; + automatic logic[CVA6Cfg.XLEN-1:0] amo_result, amo_op_a, amo_op_b, amo_op_a_u, amo_op_b_u; reservation_t reservation; // Initialize @@ -330,12 +355,12 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() // Check whether we have a valid reservation. If so, do the store and return 0. if (reservation.valid && reservation.paddr == amo_req_i.operand_a) begin amo_result = amo_op_b; - amo_exp_result = 64'b0; + amo_exp_result = 'b0; // Else, leave the memory unchanged and return 1. end else begin amo_result = amo_shadow; - amo_exp_result = 64'b1; + amo_exp_result = 'b1; end // Either way, invalidate the reservation. @@ -394,10 +419,10 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #()() /////////////////////////////////////////////////////////////////////////////// std_nbdcache #( - .CVA6Cfg ( ArianeDefaultConfig ), - .AXI_ADDR_WIDTH ( TbAxiAddrWidthFull ), - .AXI_DATA_WIDTH ( TbAxiDataWidthFull ), - .AXI_ID_WIDTH ( TbAxiIdWidthFull ), + .CVA6Cfg ( CVA6Cfg ), + .dcache_req_i_t ( dcache_req_i_t ), + .dcache_req_o_t ( dcache_req_o_t ), + .NumPorts ( 3 ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_resp_t ) ) i_dut ( @@ -427,7 +452,7 @@ axi_riscv_atomics_wrap #( .AXI_ID_WIDTH ( TbAxiIdWidthFull + 32'd1 ), .AXI_USER_WIDTH ( TbAxiUserWidthFull ), .AXI_MAX_WRITE_TXNS ( 1 ), - .RISCV_WORD_WIDTH ( 64 ) + .RISCV_WORD_WIDTH ( CVA6Cfg.XLEN ) ) i_amo_adapter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -453,8 +478,8 @@ axi_riscv_atomics_wrap #( assign fifo_data_in[k] = {req_ports_i[k].data_size, exp_paddr[k]}; - for (genvar l=0; l<8; l++) - assign exp_rdata[k][l*8 +: 8] = tb_mem_port_t::shadow_q[{fifo_data[k].paddr[63:3], 3'b0} + l]; + for (genvar l=0; l all requests should use bypass port - bypass_mem_port.set_region(0, MemBytes - 1); + bypass_mem_port.set_region(0, cva6_config_pkg::MemBytes - 1); data_mem_port.set_region(0, 0); runSeq(nReadVectors); @@ -708,7 +744,7 @@ axi_riscv_atomics_wrap #( // cache enabled ~> requests to cached region should use cache port, // those to uncached regions should use bypass port bypass_mem_port.set_region(0, CachedAddrBeg - 1); - data_mem_port.set_region(CachedAddrBeg, MemBytes - 1); + data_mem_port.set_region(CachedAddrBeg, cva6_config_pkg::MemBytes - 1); runSeq(nReadVectors); flushCache(); @@ -781,7 +817,7 @@ axi_riscv_atomics_wrap #( req_rate = '{default: 7'd25}; // cache disabled ~> all requests should use bypass port - bypass_mem_port.set_region(0, MemBytes - 1); + bypass_mem_port.set_region(0, cva6_config_pkg::MemBytes - 1); data_mem_port.set_region(0, 0); runSeq(nReadVectors,nWriteVectors); @@ -802,7 +838,7 @@ axi_riscv_atomics_wrap #( // cache enabled ~> requests to cached region should use cache port, // those to uncached regions should use bypass port bypass_mem_port.set_region(0, CachedAddrBeg - 1); - data_mem_port.set_region(CachedAddrBeg, MemBytes - 1); + data_mem_port.set_region(CachedAddrBeg, cva6_config_pkg::MemBytes - 1); runSeq(nReadVectors,2*nWriteVectors); flushCache(); @@ -849,9 +885,9 @@ axi_riscv_atomics_wrap #( seq_type = '{IDLE_SEQ, IDLE_SEQ, LINEAR_SEQ}; req_rate = '{default:100}; - runSeq((CachedAddrBeg>>3)+(2**(CVA6Cfg.DCACHE_INDEX_WIDTH-3))*DCACHE_SET_ASSOC); + runSeq((CachedAddrBeg>>3)+(2**(CVA6Cfg.DCACHE_INDEX_WIDTH-3))*CVA6Cfg.DCACHE_SET_ASSOC); seq_type = '{LINEAR_SEQ, IDLE_SEQ, IDLE_SEQ}; - runSeq(0,(CachedAddrBeg>>3)+(2**(CVA6Cfg.DCACHE_INDEX_WIDTH-3))*DCACHE_SET_ASSOC); + runSeq(0,(CachedAddrBeg>>3)+(2**(CVA6Cfg.DCACHE_INDEX_WIDTH-3))*CVA6Cfg.DCACHE_SET_ASSOC); flushCache(); tb_mem_port_t::check_mem(); @@ -958,7 +994,7 @@ axi_riscv_atomics_wrap #( req_rate = '{50,0,2}; // AMOs should use cache port - bypass_mem_port.set_region(0, MemBytes-1); + bypass_mem_port.set_region(0, cva6_config_pkg::MemBytes-1); data_mem_port.set_region(0, 0); runAMOs(nAMOs,1); // Last sequence flag, terminates agents diff --git a/corev_apu/tb/tb_wb_dcache/tb.list b/corev_apu/tb/tb_wb_dcache/tb.list index 05180e4ee..d08c0adae 100644 --- a/corev_apu/tb/tb_wb_dcache/tb.list +++ b/corev_apu/tb/tb_wb_dcache/tb.list @@ -1,4 +1,5 @@ -../../../core/include/cv64a6_imafdc_sv39_config_pkg.sv +../../../core/include/config_pkg.sv +hdl/cv64a6_config_pkg.sv ../../../core/include/riscv_pkg.sv ../common_verification/src/clk_rst_gen.sv ../common_verification/src/rand_id_queue.sv @@ -9,15 +10,18 @@ ../common_verification/src/rand_synch_driver.sv ../common_verification/src/rand_stream_slv.sv ../../riscv-dbg/src/dm_pkg.sv -../../axi/src/axi_pkg.sv -../../axi/src/axi_intf.sv -../../axi/src/axi_test.sv +../../../vendor/pulp-platform/axi/src/axi_pkg.sv +../../../vendor/pulp-platform/axi/src/axi_intf.sv +../../../vendor/pulp-platform/axi/src/axi_test.sv ../../../core/include/ariane_pkg.sv +../../../core/include/build_config_pkg.sv +../ariane_axi_pkg.sv ../ariane_soc_pkg.sv ../ariane_axi_soc_pkg.sv -../../../core/include/ariane_axi_pkg.sv ../../../core/include/std_cache_pkg.sv -../../../common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv +../../../vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv +../../../common/local/util/tc_sram_wrapper.sv +../../../vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv ../../../core/cache_subsystem/cache_ctrl.sv ../../../core/cache_subsystem/miss_handler.sv ../../../core/cache_subsystem/std_nbdcache.sv @@ -33,7 +37,7 @@ ../../../vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv ../../../vendor/pulp-platform/common_cells/src/stream_mux.sv ../../../vendor/pulp-platform/common_cells/src/stream_demux.sv -../../../core/axi_adapter.sv +../../../core/cache_subsystem/axi_adapter.sv ../../../common/local/util/sram.sv ../../src/axi_riscv_atomics/src/axi_res_tbl.sv ../../src/axi_riscv_atomics/src/axi_riscv_amos.sv