From 4c663fc164dfa3cfe22afc5bec4f37cbd703da45 Mon Sep 17 00:00:00 2001 From: Moritz Schneider Date: Thu, 7 Sep 2023 14:35:03 +0200 Subject: [PATCH] Hardwire the reserved bits of the PMPCFG CSR to 0 This realigns CVA6 with spike (#1346) Signed-off-by: Moritz Schneider --- core/csr_regfile.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index fe2022bcd..d2767a8c7 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -908,6 +908,9 @@ module csr_regfile import ariane_pkg::*; #( // hardwired extension registers mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty); + // reserve PMPCFG bits 5 and 6 (hardwire to 0) + for (int i = 0; i < NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0; + // write the floating point status register if (csr_write_fflags_i) begin fcsr_d.fflags = csr_wdata_i[4:0] | fcsr_q.fflags;