diff --git a/.github/workflows/dashboard-done.yml b/.github/workflows/dashboard-done.yml new file mode 100644 index 000000000..07682978d --- /dev/null +++ b/.github/workflows/dashboard-done.yml @@ -0,0 +1,42 @@ +# Copyright 2023 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme ALLART - Thales + +on: + workflow_dispatch: + inputs: + pr_number: + description: 'ID of the PR to comment' + required: true + type: string + success: + description: 'Is the workflow successful?' + required: true + type: boolean + +permissions: + pull-requests: write + +jobs: + welcome: + runs-on: ubuntu-latest + steps: + - uses: actions/github-script@v6 + with: + script: | + const inputs = context.payload.inputs + const pr = inputs.pr_number + const success = inputs.success == 'true' + const status_text = success ? ":heavy_check_mark: successful" : ":x: failed" + const url = `https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_core-v-verif_${pr}.html` + await github.rest.issues.createComment({ + issue_number: pr, + owner: context.repo.owner, + repo: context.repo.repo, + body: `${status_text} run, report available [here](${url}).` + }) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c905d5a16..da31d2b7e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -36,6 +36,9 @@ variables: workflow: rules: + - if: '$CI_WEIGHT == "forced" && $CI_COMMIT_REF_NAME =~ /^cvvdev\/.*/' #bypass workflow + cvvdev + variables: + CVA6_BRANCH: $CI_COMMIT_REF_NAME - if: '$CI_WEIGHT == "forced"' #bypass workflow - if: '$CI_COMMIT_REF_NAME =~ /^master.*|^hotfix.*|^rc.*|^cva6\/dev.*|^github-pr.*/' variables: diff --git a/.gitlab-ci/cva6.yml b/.gitlab-ci/cva6.yml index b9442f7d2..fce1cab9f 100644 --- a/.gitlab-ci/cva6.yml +++ b/.gitlab-ci/cva6.yml @@ -66,6 +66,7 @@ variables: stages: - .pre + - build_tools - one - two - three @@ -91,9 +92,8 @@ initjob: reports: dotenv: .env - pub_check_env: - stage: one + stage: .pre extends: - .template_job_low_footprint - .template_job_full_ci @@ -102,7 +102,9 @@ pub_check_env: - echo $RISCV - echo $RISCV_PREFIX - echo $VERILATOR_ROOT + - echo $VERILATOR_INSTALL_DIR - echo $SPIKE_ROOT + - echo $SPIKE_INSTALL_DIR - echo $BBL_ROOT - echo $SYN_VCS_BASHRC - echo $SYN_DCSHELL_BASHRC @@ -133,12 +135,36 @@ pub_check_env: - echo $SYNTH_PERIOD - echo $LIB_VERILOG +pub_build_tools: + stage: build_tools + extends: + - .template_job_full_ci + needs: [] + script: + # ROOT_PROJECT is used by Spike installer and designates the toplevel of core-v-verif tree. + - 'export ROOT_PROJECT=$(pwd)' + # If a local build of Spike is requested, clean up build and installation directories. + - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf vendor/riscv/riscv-isa-sim/build' + - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf tools/spike' + # Create default directory corresponding to the artifact path. + - mkdir -p tools/spike + # Set up Spike, whether locally built or pre-installed. + # If initially set to "__local__", SPIKE_INSTALL_DIR will be resolved + # to an absolute path by the installation script. + - source cva6/regress/install-spike.sh + # Strip locally built binaries and customext library to reduce artifact size. + - '[ -f $(pwd)/tools/spike/bin/spike ] && strip $(pwd)/tools/spike/bin/spike* $(pwd)/tools/spike/lib/libcustomext.so' + artifacts: + paths: + - tools/spike/ pub_smoke: stage: one extends: - .template_job_full_ci - needs: [] + needs: + - job: pub_build_tools + artifacts: true parallel: matrix: - DV_SIMULATORS: ["veri-testharness,spike","vcs-testharness,spike","vcs-uvm,spike" ] @@ -148,21 +174,87 @@ pub_smoke: DASHBOARD_SORT_INDEX: 0 DASHBOARD_JOB_CATEGORY: "Basic" script: - - mkdir -p artifacts/reports + - mkdir -p artifacts/reports artifacts/logs - python3 .gitlab-ci/scripts/report_fail.py - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC - - source cva6/regress/smoke-tests.sh + # In order to capture logs in case of test failure, the test script cannot fail. + - source cva6/regress/smoke-tests.sh || true + # The list of files must NOT fail on various DV_SIMULATORS values, so use 'v*_sim' to match + # 'veri-testharness_sim', 'vcs-testharness_sim' and 'vcs-uvm_sim' (one of them always applies, + # at least until new RTL simulator configurations are added.) + - for i in cva6/sim/*/v*_sim/*.log.iss ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log artifacts: when: always paths: - artifacts/reports/*.yml + - artifacts/logs/*.log.iss.head + +pub_riscv_arch_test: + stage: two + extends: + - .template_job_short_ci + needs: + - job: pub_build_tools + artifacts: true + - job: pub_smoke + artifacts: false + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - source cva6/regress/dv-riscv-arch-test.sh + - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" + +csr_test: + stage: two + extends: + - .template_job_short_ci + needs: + - job: pub_build_tools + artifacts: true + - job: pub_smoke + artifacts: false + parallel: + matrix: + - DV_TARGET: [cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "csr_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "CSR regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - source cva6/regress/dv-riscv-csr-access-test.sh + - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" pub_hwconfig: stage: two extends: - .template_job_short_ci needs: + - job: pub_build_tools + artifacts: true - job: pub_smoke artifacts: false parallel: @@ -191,6 +283,8 @@ pub_compliance: extends: - .template_job_short_ci needs: + - job: pub_build_tools + artifacts: true - job: pub_smoke artifacts: false parallel: @@ -219,6 +313,8 @@ pub_tests-v: extends: - .template_job_short_ci needs: + - job: pub_build_tools + artifacts: true - job: pub_smoke artifacts: false parallel: @@ -248,6 +344,8 @@ pub_tests-p: extends: - .template_job_short_ci needs: + - job: pub_build_tools + artifacts: true - job: pub_smoke artifacts: false parallel: @@ -274,6 +372,7 @@ pub_tests-p: pub_synthesis: stage: two + timeout: 2 hours extends: - .template_job_always_manual needs: @@ -285,6 +384,8 @@ pub_synthesis: PERIOD: ["1.1"] - TARGET: [cv32a60x] PERIOD: ["0.95"] + - TARGET: [cv32a6_embedded] + PERIOD: ["0.85"] variables: INPUT_DELAY: "0.46" OUTPUT_DELAY: "0.11" @@ -365,7 +466,9 @@ pub_benchmarks: DASHBOARD_JOB_DESCRIPTION: "Performance indicator of some benchmark" DASHBOARD_SORT_INDEX: 7 DASHBOARD_JOB_CATEGORY: "Test suites" - needs: [] + needs: + - job: pub_build_tools + artifacts: true script: - mkdir -p artifacts/reports - python3 .gitlab-ci/scripts/report_fail.py @@ -379,11 +482,61 @@ pub_benchmarks: paths: - "artifacts/reports/*.yml" +pub_coremark: + stage: two + extends: + - .template_job_full_ci + needs: + - job: pub_build_tools + artifacts: true + - job: pub_smoke + artifacts: false + variables: + DASHBOARD_JOB_TITLE: "CoreMark" + DASHBOARD_JOB_DESCRIPTION: "Performance indicator" + DASHBOARD_SORT_INDEX: 5 + DASHBOARD_JOB_CATEGORY: "Performance" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - bash cva6/regress/coremark.sh --no-print + - python3 .gitlab-ci/scripts/report_benchmark.py --coremark cva6/sim/out_*/veri-testharness_sim/core_main.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" + +pub_dhrystone: + stage: two + extends: + - .template_job_full_ci + needs: + - job: pub_build_tools + artifacts: true + - job: pub_smoke + artifacts: false + variables: + DASHBOARD_JOB_TITLE: "Dhrystone" + DASHBOARD_JOB_DESCRIPTION: "Performance indicator" + DASHBOARD_SORT_INDEX: 5 + DASHBOARD_JOB_CATEGORY: "Performance" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - bash cva6/regress/dhrystone.sh + - python3 .gitlab-ci/scripts/report_benchmark.py --dhrystone cva6/sim/out_*/veri-testharness_sim/dhrystone_main.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" + pub_wb_dcache: stage: three extends: - .template_job_always_manual - needs: [] + needs: + - job: pub_build_tools + artifacts: true variables: DASHBOARD_JOB_TITLE: "Writeback Data Cache test" DASHBOARD_JOB_DESCRIPTION: "Test of IP wb_dcache" @@ -397,7 +550,8 @@ pub_wb_dcache: - source ci/make-tmp.sh - source ci/build-riscv-tests.sh - cd ../../../ - - make run-asm-tests-verilator defines=WB_DCACHE + # Use 'verilator --no-timing' until the timing issues in corev_apu RTL are fixed. + - make verilator="verilator --no-timing" run-asm-tests-verilator defines=WB_DCACHE - cd ../.. - python3 .gitlab-ci/scripts/report_pass.py artifacts: @@ -440,6 +594,8 @@ pub_generated_tests: stage: two tags: [$TAGS_RUNNER] needs: + - job: pub_build_tools + artifacts: true - job: pub_smoke artifacts: false variables: @@ -486,8 +642,8 @@ pub_fpga-boot: - job: pub_fpga-build artifacts: true variables: - VERILATOR_ROOT: "/shares/tools/dummy/verilator" # to avoid install of verilator - SPIKE_ROOT: "/shares/tools/dummy/spike" # to avoid install of spike + VERILATOR_INSTALL_DIR: "NO" # Skip install and checks of verilator + SPIKE_ROOT: "NO" # Skip install and checks of spike DASHBOARD_JOB_TITLE: "FPGA Linux64 Boot " DASHBOARD_JOB_DESCRIPTION: "Test of Linux 64 bits boot on FPGA Genesys2" DASHBOARD_SORT_INDEX: 10 diff --git a/.gitlab-ci/scripts/github_integration.py b/.gitlab-ci/scripts/github_integration.py new file mode 100644 index 000000000..c49c5b798 --- /dev/null +++ b/.gitlab-ci/scripts/github_integration.py @@ -0,0 +1,63 @@ +""" +This module makes it possible to trigger GitHub workflows. +""" + +from os import environ as env +import requests + +def api_url(owner, repo): + "Build API url for a given repository" + return f"https://api.github.com/repos/{owner}/{repo}" + +def pulls(owner, repo): + "Get (public) pull requests from a given repository" + url = api_url(owner, repo) + '/pulls' + headers = {} + if 'GH_TOKEN' in env: + headers["Authorization"] = f"Token {env['GH_TOKEN']}" + response = requests.get(url, headers=headers) + assert response.status_code == 200 + return response.json() + +class Workflow: + "GitHub Workflow that can be triggered on a dispatch event" + def __init__(self, owner, repo, workflow_id, ref): + dispatches = f"/actions/workflows/{workflow_id}/dispatches" + self.url = api_url(owner, repo) + dispatches + self.ref = ref + + def _trigger(self, inputs): + "Trigger the workflow" + data = { + 'ref': self.ref, + 'inputs': inputs, + } + token = env['GH_TOKEN'] + headers = { + 'Accept': 'application/vnd.github+json', + 'Authorization': f"Bearer {token}", + 'X-GitHub-Api-Version': '2022-11-28', + } + return requests.post(url=self.url, json=data, headers=headers) + +class DashboardDone(Workflow): + "`dashboard-done.yml` GitHub workflow" + def __init__(self, owner, repo, ref): + workflow_id = 'dashboard-done.yml' + Workflow.__init__(self, owner, repo, workflow_id, ref) + + def send(self, pr, success): + "Send success or failure message" + inputs = { + 'pr_number': str(pr), + 'success': success, + } + return self._trigger(inputs) + + def send_success(self, pr): + "Send message stating that job is successful" + return self.send(pr, True) + + def send_failure(self, pr): + "Send message stating that job is failed" + return self.send(pr, False) diff --git a/.gitlab-ci/scripts/merge_job_reports.py b/.gitlab-ci/scripts/merge_job_reports.py index 00d79b3d0..5b1e5f833 100644 --- a/.gitlab-ci/scripts/merge_job_reports.py +++ b/.gitlab-ci/scripts/merge_job_reports.py @@ -14,6 +14,7 @@ import yaml import datetime import sys import subprocess +import github_integration as gh # arguments: inputdir outputfile @@ -105,12 +106,14 @@ pipeline = { 'jobs': [] } +success = True dir_list = os.listdir(sys.argv[1]) for f in dir_list: with open(sys.argv[1] + "/" + f, 'r') as job_report: report = safe_load(job_report) pipeline["jobs"].append(report) if report['status'] != 'pass': + success = False pipeline["status"] = 'fail' pipeline["label"] = 'FAIL' @@ -139,3 +142,20 @@ cd - ''', shell=True)) except subprocess.CalledProcessError as e: print(f"Error: {e.output}") + +def find_pr(branch, prs): + match = re.search(r'(.*)_PR_([a-zA-Z0-9](?:[a-zA-Z0-9]|[-_](?=[a-zA-Z0-9])){0,38})', branch) + if match: + label = f'{match.group(2)}:{match.group(1)}' + for pr in prs: + if label == pr['head']['label']: + return pr + return None + +pulls = gh.pulls('openhwgroup', workflow_repo) +pr = find_pr(workflow_commit_ref_name, pulls) +if pr is not None: + ref_branch = pr['base']['ref'] + wf = gh.DashboardDone('openhwgroup', workflow_repo, ref_branch) + response = wf.send(pr['number'], success) + print(response.text) diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py new file mode 100644 index 000000000..92e192bd2 --- /dev/null +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -0,0 +1,65 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme Allart + +import sys +import report_builder as rb + +path = None +mode = None +iterations = None + +# Keep it up-to-date with compiler version and core performance improvements +# Will fail if the number of cycles is different from this one +valid_cycles = { + 'dhrystone': 221425, + 'coremark': 697868, +} + +for arg in sys.argv[1:]: + if arg == '--dhrystone': + mode = 'dhrystone' + iterations = 500 + elif arg == '--coremark': + mode = 'coremark' + # Too few iterations to consider a score + else: + path = arg + +# We do not want to have a report without a check +assert mode is not None + +with open(path, 'r') as f: + log = [l.strip() for l in f.readlines()] + +stopwatch = [] +for index, line in enumerate(log): + if line.split()[-1] == 'mcycle': + stopwatch.append(int(log[index + 1].split()[-1], 16)) +# There might be > 2 matches, we use the two at the center +N = len(stopwatch) +assert N % 2 == 0 +cycles = stopwatch[N//2] - stopwatch[N//2-1] + +score_metric = rb.TableMetric('Performance results') +score_metric.add_value('cycles', cycles) + +if iterations is not None: + ipmhz = iterations * 1000000 / cycles + if mode == 'dhrystone': + score_metric.add_value('Dhrystone/MHz', ipmhz) + score_metric.add_value('DMIPS/MHz', ipmhz / 1757) + +diff = cycles - valid_cycles[mode] +if diff != 0: + score_metric.fail() + score_metric.add_value('Cycles diff', diff) + +report = rb.Report(f'{cycles//1000} kCycles') +report.add_metric(score_metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_builder.py b/.gitlab-ci/scripts/report_builder.py new file mode 100644 index 000000000..a34c8b265 --- /dev/null +++ b/.gitlab-ci/scripts/report_builder.py @@ -0,0 +1,161 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme Allart + +""" +Helpers to build CI reports +""" + +import os +import re +from datetime import datetime as dt +import yaml + +class Metric: + "A metric is a part of the body of the report" + + def __init__(self, name): + self.name = name + self.sort_index = None + self.failed = False + self.values = [] + + def to_doc(self): + "Transform to a dictionary" + return { + 'display_name': self.name, + 'sort_index': self.sort_index, + 'type': self._t(), + 'status': "fail" if self.failed else "pass", + 'value': self._values_to_doc(), + } + + def fail(self): + "Mark metric as failed" + self.failed = True + + def _values_to_doc(self): + raise NotImplementedError() + + def _t(self): + raise NotImplementedError() + +class LogMetric(Metric): + "Log lines" + + def add_value(self, line): + "Insert a line in the log" + self.values.append(line) + + def _values_to_doc(self): + return self.values + + def _t(self): + return 'log' + +class TableMetric(Metric): + "Table" + + def add_value(self, *col): + "Insert a line in the table" + self.values.append(list(col)) + + def _values_to_doc(self): + return [{'col': v} for v in self.values] + + def _t(self): + return 'table' + +class TableStatusMetric(Metric): + "Table with status label for each line" + + def add_pass_label(self, label, *col): + "Insert a 'pass' line with given label in the table" + self._add_value('pass', label, *col) + + def add_fail_label(self, label, *col): + "Insert a 'fail' line with given label in the table" + self._add_value('fail', label, *col) + self.fail() + + def add_pass(self, *col): + "Insert a 'pass' line in the table" + self.add_pass_label("PASS", *col) + + def add_fail(self, *col): + "Insert a 'fail' line in the table" + self.add_fail_label("FAIL", *col) + + def _add_value(self, status, label, *col): + self.values.append((status, label, list(col))) + + def _values_to_doc(self): + return [{'status': s, 'label': l, 'col': c} for (s,l,c) in self.values] + + def _t(self): + return 'table_status' + +class Report: + "A report is the top level entity of the document" + + def __init__(self, label=None): + self.label = label + self.failed = False + self.metrics = [] + + def add_metric(self, *metric): + "Add one or more metric(s) to the report body" + for m in metric: + if m.sort_index is None: + if len(self.metrics) > 0: + m.sort_index = self.metrics[-1].sort_index + 1 + else: + m.sort_index = 1 + self.metrics.append(m) + if m.failed: + self.fail() + + def fail(self): + "Mark report as failed" + self.failed = True + + def to_doc(self): + "Transform to a dictionary" + assert len(self.metrics) > 0, "A report must have at least one metric" + start = os.environ['CI_JOB_STARTED_AT'] + start_fmt = '%Y-%m-%dT%H:%M:%S%z' + start = dt.strptime(start, start_fmt).timestamp() + pass_label = "FAIL" if self.failed else "PASS" + label = pass_label if self.label is None else self.label + return { + 'title': os.environ["DASHBOARD_JOB_TITLE"], + 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], + 'category': os.environ["DASHBOARD_JOB_CATEGORY"], + 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], + 'job_id': os.environ["CI_JOB_ID"], + 'job_url': os.environ["CI_JOB_URL"], + 'job_stage_name': os.environ["CI_JOB_STAGE"], + 'job_started_at': int(start), + 'job_end_at': int(dt.now().timestamp()), + 'token': 'YC' + str(dt.now().timestamp()).replace('.', ''), + 'status': "fail" if self.failed else "pass", + 'metrics': [m.to_doc() for m in self.metrics], + 'label': label, + } + + def dump(self, path=None): + """ + Create report file + + By default the output path is build from $CI_JOB_NAME + """ + if path is None: + filename = re.sub(r'[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) + path = 'artifacts/reports/'+filename+'.yml' + with open(path, 'w') as f: + yaml.dump(self.to_doc(), f) diff --git a/.gitlab-ci/scripts/report_fail.py b/.gitlab-ci/scripts/report_fail.py index 787c4fd80..a59a14c80 100644 --- a/.gitlab-ci/scripts/report_fail.py +++ b/.gitlab-ci/scripts/report_fail.py @@ -7,40 +7,11 @@ # # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) -import re -from pprint import pprint -import yaml -import datetime -import os +import report_builder as rb -report = {'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "fail", - 'label': "FAIL", - 'metrics': [{'display_name': '', - 'sort_index': 1, - 'type': 'table_status', - 'status': "fail", - 'value': [{ - 'status': 'fail', - 'label': 'FAIL', - 'col': ['Job has failed before end of script'], - }], - }], - } +metric = rb.TableStatusMetric('') +metric.add_fail('Job has failed before end of script') -pprint(report) - -filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_fpga.py b/.gitlab-ci/scripts/report_fpga.py index fce12f162..a1f48c7fa 100644 --- a/.gitlab-ci/scripts/report_fpga.py +++ b/.gitlab-ci/scripts/report_fpga.py @@ -8,32 +8,13 @@ # Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com) import re -from pprint import pprint -import yaml -import datetime import sys -import os + +import report_builder as rb with open(str(sys.argv[1]), "r") as f: log = f.read() -global_pass = "pass" - -report = { - 'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "pass", - 'metrics': [] -} - pattern = re.compile( "\|(?P +)(?P[\w()\[\].]+) +\| +(?P[\w()\[\].]+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \| +(?P\d+) \|" ) @@ -45,36 +26,26 @@ for line in pattern.finditer(log): break data.append(l) - -metric = { - 'display_name': 'Utilization Results', - 'sort_index': 1, - 'type': 'table', - 'status': 'pass', - 'value': [], -} +report = rb.Report() +metric = rb.TableMetric('Utilization Results') for i in data: - value = {"col": []} if (i["ind"]).count(" ") < 10: - value["col"].append(i["Instance"]) if i["Instance"] == "ariane_xilinx": - report["label"] = i["TotalLUTs"] + " TotalLUTs" - value["col"].append(i["Module"]) - value["col"].append(i["TotalLUTs"] + " TotalLUTs") - value["col"].append(i["LogicLUTs"] + " LogicLUTs") - value["col"].append(i["LUTRAMs"] + " LUTRAMs") - value["col"].append(i["SRLs"] + " SRLs") - value["col"].append(i["FFs"] + " FFs") - value["col"].append(i["RAMB36"] + " RAMB36") - value["col"].append(i["RAMB18"] + " RAMB18") - value["col"].append(i["DSP48Blocks"] + " DSP48Blocks") - metric["value"].append(value) + total = int(i["TotalLUTs"]) // 1000 + report.label = f"{total} kLUTs" + metric.add_value( + i["Instance"], + i["Module"], + i["TotalLUTs"] + " TotalLUTs", + i["LogicLUTs"] + " LogicLUTs", + i["LUTRAMs"] + " LUTRAMs", + i["SRLs"] + " SRLs", + i["FFs"] + " FFs", + i["RAMB36"] + " RAMB36", + i["RAMB18"] + " RAMB18", + i["DSP48Blocks"] + " DSP48Blocks", + ) -report["metrics"].append(metric) - -filename = re.sub("[^\w\.\\\/]", "_", os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_fpga_boot.py b/.gitlab-ci/scripts/report_fpga_boot.py index 1d6b4ec30..aca42327a 100644 --- a/.gitlab-ci/scripts/report_fpga_boot.py +++ b/.gitlab-ci/scripts/report_fpga_boot.py @@ -7,12 +7,8 @@ # # Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com) -import re -from pprint import pprint -import yaml -import datetime import sys -import os +import report_builder as rb with open(str(sys.argv[1]), "r") as f: lastline = f.readlines()[-1] @@ -20,52 +16,12 @@ with open(str(sys.argv[1]), "r") as f: with open(str(sys.argv[1]), "r") as f: log = f.read() -global_pass = "pass" - -report = { - 'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "pass", - 'metrics': [] -} - -metric = { - 'display_name': 'Linux boot log', - 'sort_index': 1, - 'type': 'table_status', - 'status': 'pass', - 'value': [], -} - -value = {} -print(lastline) +metric = rb.TableStatusMetric('Linux boot log') if not ("Linux buildroot" in lastline and "riscv" in lastline): - value["status"] = "fail" - value["label"] = "FAIL" - report["status"] = "fail" - report["label"] = "FAIL" - metric["status"] = "fail" + metric.add_fail(lastline) else: - value["status"] = "pass" - value["label"] = "PASS" - report["status"] = "pass" - report["label"] = "PASS" + metric.add_pass(lastline) -value["col"] = [lastline] -metric["value"].append(value) - -report["metrics"].append(metric) - -filename = re.sub("[^\w\.\\\/]", "_", os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_pass.py b/.gitlab-ci/scripts/report_pass.py index 2168b842d..a458d0608 100644 --- a/.gitlab-ci/scripts/report_pass.py +++ b/.gitlab-ci/scripts/report_pass.py @@ -7,41 +7,11 @@ # # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) -import re -from pprint import pprint -import yaml -import datetime -import os +import report_builder as rb -report = {'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "pass", - 'label': "PASS", - 'metrics': [{'display_name': '', - 'sort_index': 1, - 'type': 'table_status', - 'status': "fail", - 'value': [{ - 'status': 'pass', - 'label': 'PASS', - 'col': ['Job completed without error. No metric extraction is configured'], - }], - }], - } - -pprint(report) - -filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +metric = rb.TableStatusMetric('') +metric.add_pass('Job completed without error. No metric extraction is configured') +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_simu.py b/.gitlab-ci/scripts/report_simu.py index abdb17724..620356a75 100644 --- a/.gitlab-ci/scripts/report_simu.py +++ b/.gitlab-ci/scripts/report_simu.py @@ -7,75 +7,34 @@ # # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) -import re -from pprint import pprint -import yaml -import datetime import sys -import os +import re +import report_builder as rb with open(str(sys.argv[1]), 'r') as f: log = f.read() -global_pass = "pass" - -report = {'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "pass", - 'metrics': [] - } - pattern = re.compile( "^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Compiling (.*) : .*(tests\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?$", re.MULTILINE) - list_of_tests = pattern.findall(log) +metric = rb.TableStatusMetric('') + job_test_pass = 0 job_test_total = 0 - -metric = {'display_name': '', - 'sort_index': 1, - 'type': 'table_status', - 'status': "pass", - 'value': [] - } - for i in list_of_tests: - value = {} job_test_total += 1 + col = [i[3], i[2], i[0], i[1]] # isa testbench testsuite test if i[4] == "PASSED": - value['status'] = "pass" - value['label'] = "PASS" + metric.add_pass(*col) job_test_pass += 1 else: - value['status'] = "fail" # row level - value['label'] = "FAIL" - metric['status'] = "fail" # table_status level - report['status'] = "fail" # job level - value['col'] = [] - value['col'].append(i[3]) # isa - value['col'].append(i[2]) # testbench - value['col'].append(i[0]) # testsuite - value['col'].append(i[1]) # test - metric['value'].append(value) + metric.add_fail(*col) -report['metrics'].append(metric) +if job_test_total == 0: + metric.fail() -report['label'] = f'{job_test_pass}/{job_test_total}' - -pprint(report) - -filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +report = rb.Report(f'{job_test_pass}/{job_test_total}') +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_synth.py b/.gitlab-ci/scripts/report_synth.py index 223c1097f..8a70fda79 100644 --- a/.gitlab-ci/scripts/report_synth.py +++ b/.gitlab-ci/scripts/report_synth.py @@ -8,11 +8,9 @@ # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) import re -from pprint import pprint -import yaml -import datetime import sys import os +import report_builder as rb with open(str(sys.argv[1]), 'r') as f: log = f.read() @@ -22,31 +20,8 @@ with open(str(sys.argv[2]), 'r') as f: kgate_ratio = int(os.environ["NAND2_AREA"]) -global_pass = "pass" - -report = {'title': os.environ["DASHBOARD_JOB_TITLE"], - 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], - 'category': os.environ["DASHBOARD_JOB_CATEGORY"], - 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], - 'job_id': os.environ["CI_JOB_ID"], - 'job_url': os.environ["CI_JOB_URL"], - 'job_stage_name': os.environ["CI_JOB_STAGE"], - 'job_started_at': int(datetime.datetime.strptime(os.environ['CI_JOB_STARTED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()), - 'job_end_at': int(datetime.datetime.now().timestamp()), - 'token': 'YC' + str(datetime.datetime.now().timestamp()).replace('.', ''), - 'status': "pass", - 'metrics': [] - } - #Compile & elaborate log: - -metric = {'display_name': 'Synthesis full log', - 'sort_index': 3, - 'type': 'log', - 'status': "pass", - 'value': [] - } - +log_metric = rb.LogMetric('Synthesis full log') error_log = [] warning_log = [] for line in synthesis_log.splitlines(): @@ -58,14 +33,9 @@ for line in synthesis_log.splitlines(): error_log.append(line) if 'Warning: ' in line: warning_log.append(line) - -metric['value'] = error_log + warning_log - -report['metrics'].append(metric) - +log_metric.values = error_log + warning_log # Area repport: - pattern = re.compile( "^(Combinational area|Buf/Inv area|Noncombinational area|Macro/Black Box area):\ *(\d*\.\d*)$", re.MULTILINE) @@ -78,57 +48,24 @@ hier = pattern.findall(log) total_area = float(hier[0][1]) - -metric = {'display_name': 'Global results', - 'sort_index': 1, - 'type': 'table', - 'status': "pass", - 'value': [] - } - -value = {'col': []} -value['col'].append("Total area") # Name -value['col'].append(f'{int(total_area/kgate_ratio)} kGates') # value -metric['value'].append(value) - +result_metric = rb.TableMetric('Global results') +label = f'{int(total_area/kgate_ratio)} kGates' +result_metric.add_value("Total area", label) for i in global_val: - value = {'col': []} - value['col'].append(i[0]) # Name - if total_area == 0: - value['col'].append('0 %') - else: - value['col'].append(f'{int(float((i[1]))/total_area*100)} %') # value - - metric['value'].append(value) - -report['metrics'].append(metric) - -metric = {'display_name': 'Hierarchies details', - 'sort_index': 2, - 'type': 'table', - 'status': "pass", - 'value': [] - } + rel_area = 0 if total_area == 0 else int(float(i[1]) / total_area * 100) + result_metric.add_value(i[0], f'{rel_area} %') +hier_metric = rb.TableMetric('Hierarchies details') for i in hier: - value = {} - value['col'] = [] - value['col'].append(i[0]) # hier - value['col'].append(f"{int(float(i[1])/kgate_ratio)} kGates") # area - value['col'].append(f"{int(float(i[2]))} %") # % - #value['col'].append(int(float(i[3]))/int(float(i[1])*100)) # % combi - #value['col'].append(int(float(i[4]))/int(float(i[1])*100)) # % reg - #value['col'].append(int(float(i[5]))/int(float(i[1])*100)) # % black box - metric['value'].append(value) + hier_metric.add_value( + i[0], # hier + f"{int(float(i[1])/kgate_ratio)} kGates", # area + f"{int(float(i[2]))} %", # % + #int(float(i[3]))/int(float(i[1])*100), # % combi + #int(float(i[4]))/int(float(i[1])*100), # % reg + #int(float(i[5]))/int(float(i[1])*100), # % black box + ) -report['metrics'].append(metric) - -report['label'] = f'{int(total_area/kgate_ratio)} kGates' - -pprint(report) - -filename = re.sub('[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) -print(filename) - -with open('artifacts/reports/'+filename+'.yml', 'w+') as f: - yaml.dump(report, f) +report = rb.Report(label) +report.add_metric(result_metric, hier_metric, log_metric) +report.dump() diff --git a/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml b/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml index 30538e931..a43b7c60b 100644 --- a/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml +++ b/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml @@ -15,8 +15,8 @@ variables: COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437 COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch TESTS_REPO: https://github.com/riscv/riscv-tests.git - TEST_BRANCH: master - TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec + TESTS_BRANCH: master + TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec DV_REPO: https://github.com/google/riscv-dv.git DV_BRANCH: master NUM_JOBS: 24 diff --git a/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml index ab5d5f98e..a0553c582 100644 --- a/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml +++ b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml @@ -16,8 +16,8 @@ variables: COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437 COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch TESTS_REPO: https://github.com/riscv/riscv-tests.git - TEST_BRANCH: master - TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec + TESTS_BRANCH: master + TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec DV_REPO: https://github.com/google/riscv-dv.git DV_BRANCH: master NUM_JOBS: 24 diff --git a/bin/ci_check b/bin/ci_check index 362e7c60c..42cf58c12 100755 --- a/bin/ci_check +++ b/bin/ci_check @@ -47,7 +47,7 @@ import subprocess import pprint import yaml import re -import distutils.spawn +import shutil if (sys.version_info < (3,0,0)): print ('Requires python 3') @@ -243,7 +243,7 @@ if (args.verilator): elif (args.simulator == None): print ('Must specify a simulator. Type `ci_check -h` to see how') exit(0) -elif (not(distutils.spawn.find_executable(args.simulator))): +elif (not(shutil.which(args.simulator))): print ('ERROR: simulator='+args.simulator+' but executable not found') exit(0) else: diff --git a/cv32e40p/bsp/Makefile b/cv32e40p/bsp/Makefile index f2e0ed69c..ee05577a8 100644 --- a/cv32e40p/bsp/Makefile +++ b/cv32e40p/bsp/Makefile @@ -6,7 +6,7 @@ RISCV_AR = $(RISCV_EXE_PREFIX)ar SRC = crt0.S handlers.S syscalls.c vectors.S OBJ = crt0.o handlers.o syscalls.o vectors.o LIBCV-VERIF = libcv-verif.a -CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic +CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic all: $(LIBCV-VERIF) @@ -26,6 +26,7 @@ clean: vars: @echo "make bsp variables:" @echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)" + @echo " CV_SW_MARCH = $(CV_SW_MARCH)" @echo " RISCV = $(RISCV)" @echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)" @echo " RISCV_GCC = $(RISCV_GCC)" diff --git a/cva6/docs/UVM_verif_env.md b/cva6/docs/UVM_verif_env.md new file mode 100644 index 000000000..cbd638e45 --- /dev/null +++ b/cva6/docs/UVM_verif_env.md @@ -0,0 +1,222 @@ + +# The CVA6 UVM Verification Environment + + +This document describes the uvm verification environment of the CVA6 core. This environment is intended to be able to verify the CVA6 core and run different test cases by the minimal modification to the environment itself. The environment is shown below: + +![alt_text](images/CVA6_env.drawio.drawio.png "image_tooltip") + +*** + +This environment consist of the following + +1. Simple two uvm agents for the uvma_clknrst_if and uvma_cvxif_intf . +2. Result checking capability is built into the environment so the test cases do not need to determine and check for the pass/fail criteria. + +The environment consists of disjoint components. When a user invokes a command to run a test case a set of scripts and makefile rules are invoked to compile the environment and tests, run the simulation and check the results. On running a particular test it generates a .bin file which then is loaded into the main memory in the tb_top at the Boot_address of the core and the instructions are then start executing. + +## uvmt_cva6_tb + +In this module we instantiate the agent interfaces and the `uvmt_cva6_dut_wrap` module. We set the interfaces for the uvma_clknrst and uvma_cvxif using the configuration database set method. In this module we get the `sim_finished` database object set in the `uvmt_cva6_base_test_c` class. To check whether the simulation passed or failed we check the `err_count` and `fatal_count` along with `sim_finished`. + +## uvmt_cva6_base_test_c + +This class extends from `uvm_test`. It randomise the `uvmt_cva6_test_cfg_c` and `uvme_cva6_cfg_c` objects. The class's build_phase, connect_phase functions handle the setup and configuration of the testbench environment, connecting it to the CVA6, and executing the test. We start the `uvme_cva6_reset_vseq_c` sequence in the reset phase on the `uvme_cva6_vsqr_c` sequencer. + +## uvme_cva6_env_c + +This class extends from the `uvm_env` class. The class's build_phase,connect_phase functions handle the setup and configuration of the `uvma_clknrst_agent_c`,`uvma_cvxif_agent_c` agents.The class's run_phase task start the `cvxif_seq` sequence on the uvma_cvxif_agent sequencer. We get the configuration and context information for the environment in this class using the get method. + +### Environment_objects + +There are two uvm_objects that are `uvme_cva6_cfg_c` and `uvme_cva6_cntxt_c`. The Objects contain configuration and context information for the environment. + +### uvme_cva6_cfg_c + +This class extends from the `uvm_object` class. The object encapsulates all parameters for creating, connecting and running CVA6 environment (`uvme_cva6_env_c`) components. This class also includes a constraint block that defines default values for some of its fields and other constraints on its fields such as, `enabled` and `is_active` fields are set to 0 and 'UVM_PASSIVE' respectively by default. `clknrst_cfg.enabled` and `clknrst_cfg.is_active` are set to 1 if `enabled` and `is_active` fields are set to 1. `clknrst_cfg.trn_log_enabled` is set to 1 if `trn_log_enabled` is set to 1. `cvxif_cfg.cov_model_enabled` is set to 1 if `cov_model_enabled` is set to 1. + + + + + + + + + + + + + + + + + + + + + + + + + + +
signal + Description +
enabled + is set to 1, the environment is enabled and the components within the environment can be instantiated, built, and connected. +
is_active + This is set to UVM_PASSIVE. +
scoreboarding_enabled + It enables the scoreboard and predictor in the environment class. +
cov_model_enabled + It enables the coverage collection for environment and cvxif_agent. +
trn_log_enabled + It enables the trace log for the clk_rst_agent +
+ +### uvme_cva6_cntxt_c + +The class uvme_cva6_cntxt_c is an object that encapsulates all state variables for CVA6 environment (`uvme_cva6_env_c`) components. It inherits from the `uvm_object` base class.It also contains two events, `sample_cfg_e` and `sample_cntxt_e`, that can be used to synchronize the sampling of configuration and context information. + +### uvme_cva6_vsqr_c + +This class extends from the `uvm_sequencer` base class. It also has two sequencer handles, "clknrst_sequencer" and "cvxif_sequencer" of the types `uvma_clknrst_sqr_c` and `uvma_cvxif_sqr_c`, respectively. This class is used to start the virtual sequence. + +### uvme_cva6_reset_vseq_c + +This class `uvme_cva6_reset_vseq_c` extends a class called `uvme_cva6_base_vseq_c`. The purpose of this sequence is to start the system clock and issue the initial reset pulse to the Device Under Test (DUT). The class has three random variables, `num_clk_before_reset`, `rst_deassert_period`, and `post_rst_wait`. These variables are used to specify the number of clock cycles between the start of the clock and the reset assert.The class has a default constructor and a virtual task called "body" which is responsible for starting the clock, waiting for a specified amount of time, and then resetting the DUT. + +## Clock & Reset Agent + + This agent controls the clock and reset signal of the CVA6 core. + +### uvma_clknrst_if + +The `uvma_clknrst_if` interface has two logic signals, `clk` and `reset_n`. The `clk` signal represents the system clock, while the `reset_n` signal is the active-low reset signal.The interface includes an initial block that contains a forever loop that generates the clock signal, based on the value of `clk_active` and `clk_period`. If `clk_active` is set to 1 and `clk_period` is 0, the function will raise a fatal error. The interface also includes three functions: set_period, which sets the value of `clk_period`; start_clk, which sets `clk_active` to 1; and stop_clk, which sets `clk_active` to 0. + + + + + + + + + + + + + + +
signal + Description +
clk + Controls the Clock fed to the design under test. +
reset_n + Control the reset state of the design under test. +
+ +### uvma_clknrst_uvm_objects + +The uvm_objects `uvma_clknrst_cfg_c` , `uvma_clknrst_cntxt_c` contain the configuration and context information of the uvma_clknrst_agent. + +### uvma_clknrst_seq_item_c + +The class represents an object created by Clock & Reset agent sequences that extend the `uvma_clknrst_seq_base_c` class. + +The class contains several randomized variables: + +* `action` is an enumerated variable of type "uvma_clknrst_seq_item_action_enum" that represents the operation to perform (e.g. start clock, stop clock, assert reset, de-assert reset). +* `initial_value` is an enumerated variable of type "uvma_clknrst_seq_item_initial_value_enum" that represents the initial value of the signals (if starting or asserting). +* `clk_period` is an unsigned 32-bit integer variable representing the period of the clock signal. +* `rst_deassert_period` is an unsigned 32-bit integer variable representing the amount of time (in picoseconds) after which to de-assert reset. +* The class also includes a constraint "default_cons" which sets the default values for `clk_period` to 0 and `rst_deassert_period` to a value defined by `uvma_clknrst_default_rst_deassert_period` + +The class has a default constructor which calls the superclass constructor. + +### uvma_clknrst_Sequence + +It consists of two main sequences: `uvma_clknrst_stop_clk_seq_c` and `uvma_clknrst_restart_clk_seq_c`. + +* The `uvma_clknrst_stop_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_STOP_CLK` and start and finish the item. + +* The `uvma_clknrst_restart_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_RESTART_CLK` and start and finish the item. + +### uvma_clknrst_drv_c + +This class `uvma_clknrst_drv_c` is used for driving the interface of the clknrst agent. It get reqs from the sequence item port and calls the `drv_req` task. The `drv_req` task drives the virtual interface's (`cntxt.vif`) signals using req's contents. And then call the write method for the analysis port to send the req transaction to the coverage model. + +### uvma_clknrst_mon_c + +This class `uvma_clknrst_mon_c` is used for monitoring the virtual interface of the Clock & Reset agent. The class extends the `uvm_monitor` class and contains objects for configuration (cfg) and context (cntxt), as well as an analysis port (ap) for transaction analysis.The run_phase() task in the `uvma_clknrst_mon_c` class is responsible for overseeing the monitoring process of the Clock and Reset virtual interface. It does this by executing the monitor_clk() and monitor_reset() tasks in parallel forks. + +### uvma_clknrst_cov_model_c + +This class `uvma_clknrst_cov_model_c` extends from the `uvm_component` base class. The overall functionality of this class is to provide the coverage model for the clknrst_agent. It contains objects for configuration, context, monitor transaction, and sequence item, as well as two analysis FIFOs for holding transactions coming from the monitor and sequence item respectively. This section is in progress. + +### uvma_clknrst_agent_c + + This class `uvma_clknrst_agent_c` extends from `uvm_agent` base class. This class encapsulates ,builds and connects all the other components for driving and monitoring a Clock & reset interface. This class gets the `cfg` , `cntxt` using configuration database get method. It creates a driver,monitor,cov_model and sequencer. This class connects the driver with a sequencer. + +## Cvxif Agent + +Cv-xif agent supports custom instructions. Upon receiving the issue request it drives the response one clock cycle after the issue request. + +### uvma_cvxif_intf + +The interface includes inputs for clock and reset_n signal, as well as two data input/output called `cvxif_req_i` and `cvxif_resp_o`. It includes a clocking block for the monitor `monitor_cb` to sample the `cvxif_req_i` and `cvxif_resp_o` signal at the rising edge of the clock. + + + + + + + + + + + + + +
Enum Variable + Description +
Cvxif_req_i + The request is send to get a response +
Cvxif_resp_o + The response is generated according to the request. +
+ +### uvma_cvxif_uvm_objects + +There are two uvm_objects `uvma_cvxif_cfg_c` and `uvma_cvxif_cntxt_c`. `uvma_cvxif_cfg_c` encapsulates all the parameters for creating ,connecting and running the `uvma_cvxif_agent_c` agent . `uvma_cvxif_cntxt_c` confine all the state variables for all the CVXIF agent components. + +### uvma_cvxif_Sequence_items + +Cvxif agent has two sequence items one `uvma_cvxif_req_item_c`and `uvma_cvxif_resp_item_c` for the request and response transaction. + +### uvma_cvxif_sqr_c + +`uvma_cvxif_sqr_c` class extends from `uvm_sequencer` base class. It is a typical sequencer. This class instantiates a FIFO to receive the `uvma_cvxif_req_item_c`. + +### uvma_cvxif_sequences + +* `uvma_cvxif_base_seq_c` class extends from `uvm_sequence` . This class simply implements a decode function that checks whether the instructions are legal or illegal. + +* `uvma_cvxif_seq_c` class extends from `uvma_cvxif_base_seq_c` class. This class gets the `uvma_cvxif_req_item_c` from the FIFO in sequencer using the p_sequencer handle. In this sequence class, we send the response according to the request item received . If we receive an instruction from the req_item that is illegal then we drive zero's on the response signals. Otherwise we drive response accordingly. + +### uvma_cvxif_drv_c + +This class `uvma_cvxif_drv_c` extends from the `uvm_driver` class. This class has several tasks that perform different actions such as generating a random ready signal, getting response_item, driving an issue response to the `VIF` , driving results in order and out of order fashion, and de-asserting signals. + +### uvma_cvxif_mon_c + +`uvma_cvxif_mon_c` class extends from the `uvm_monitor` . It monitors the virtual interface `vif`. It monitors transaction requests and responses, and sends transaction requests to `uvma_cvxif_sqr_c` and responses to the coverage model. It has several fields, including objects for configuration and context, and analysis ports for transaction requests and responses. + +### uvma_cvxif_cov_model_c + +`uvma_cvxif_cov_model_c` is derived from the `uvm_component` class. This class defines various objects and covergroups with different coverpoints, and it also uses the UVM library to sample these coverpoints and measure coverage.The main purpose of this class is to measure the functional coverage of a specific interface in the design and ensure that it has been fully tested. + +### uvma_cvxif_agent_c + +`uvma_cvxif_agent_c` class extends from `uvm_agent` class. This class represents an agent that is responsible for the test execution and communication between the virtual interface (VIF) and the testbench components. The main role of this class is to create and connect the different components of the testbench and manage the communication between them and the virtual interface (VIF) during the test execution. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/AXI/VP_IP005.yml b/cva6/docs/VerifPlans/AXI/VP_IP005.yml new file mode 100644 index 000000000..05353b025 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP005.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 2 +name: Burst +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_Control_Signals: !Subfeature + name: 000_Control_Signals + tag: VP_IP005_P000 + next_elt_id: 12 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F005_S000_I000 + description: All transaction performed by CVA6 are of type INCR. AxBURST = + 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxBURST == 0b01 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F005_S000_I001 + description: All Read transaction performed by CVA6 are of burst lenght less + or equal to 2. ARLEN = 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F005_S000_I002 + description: All write transaction performed by CVA6 are of burst lenght equal + to 1. AWLEN = 0b00 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F005_S000_I003 + description: The size of a read transfer does not exceed the width of the + data interface. The maximum value can be taking by AxSIZE is 3. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '007': !VerifItem + name: '007' + tag: VP_1_F005_S000_I007 + description: Exclusive access transactions cannot have a length greater than + 16 beats + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID + is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP006.yml b/cva6/docs/VerifPlans/AXI/VP_IP006.yml new file mode 100644 index 000000000..768ff9560 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP006.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 9 +name: Signals +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_ID: !Subfeature + name: 000_ID + tag: VP_IP006_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S000_I000 + description: The CVA6 identify read transaction with an ID equal to 0 or 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S000_I001 + description: The CVA6 identify write transaction with an ID equal to 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWID == 0b01 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_User: !Subfeature + name: 001_User + tag: VP_IP006_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S001_I000 + description: User-defined extension for the write and read address channel + is not supported. AxUSER = 0b00 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S001_I001 + description: User-defined extension for the write response channel is not + supported. + reqt_doc: AXI Design doc - (table 2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that BUSER = 0b00 is always true while B_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 002_Quality_of_Service: !Subfeature + name: 002_Quality_of_Service + tag: VP_IP006_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S002_I000 + description: Quality of Service identifier is not supported. AxQOS = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 003_Cache: !Subfeature + name: 003_Cache + tag: VP_IP006_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S003_I000 + description: AxCACHE always take 0b0000. + reqt_doc: 'AXI Design Doc - Transaction Attributes: Memory types' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxCACHE = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 004_Protection: !Subfeature + name: 004_Protection + tag: VP_IP006_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S004_I000 + description: Protection attributes always take the 0b000 + reqt_doc: AXI Design Doc - (Table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 008_Region: !Subfeature + name: 008_Region + tag: VP_IP006_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S008_I000 + description: Region indicator is not supported. AxREGION = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxREGION = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP007.yml b/cva6/docs/VerifPlans/AXI/VP_IP007.yml new file mode 100644 index 000000000..202bd170b --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP007.yml @@ -0,0 +1,64 @@ +!Feature +next_elt_id: 1 +name: Clock and Reset +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_Signals_Value: !Subfeature + name: 000_Signals_Value + tag: VP_IP007_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F007_S000_I000 + description: A value of X on [Ax | x]VALID is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]VALID != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F007_S000_I001 + description: A value of X on [Ax | x]READY is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]READY != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F007_S000_I002 + description: '[Ax | x]VALID is LOW for the first cycle after RESET goes HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID is low the first cycle after RESET + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP008.yml b/cva6/docs/VerifPlans/AXI/VP_IP008.yml new file mode 100644 index 000000000..642c70531 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP008.yml @@ -0,0 +1,141 @@ +!Feature +next_elt_id: 3 +name: Handshake_Process +id: 8 +display_order: 8 +subfeatures: !!omap +- '000_Stability ': !Subfeature + name: '000_Stability ' + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S000_I000 + description: All signals must remain stable when [Ax | x]VALID is asserted + and [Ax | x]READY is LOW + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that all the signals does not change while [Ax | x]VALID + is asserted and [Ax | x]READY not yet asserted. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F008_S000_I001 + description: '[Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID does not change while [Ax | x]READY + is low. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_Timing: !Subfeature + name: 001_Timing + tag: VP_IP008_P001 + next_elt_id: 8 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S001_I000 + description: The Manager must not wait for the Subordinate to assert ARREADY + before asserting ARVALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY\ + \ is asserted on or after same cycle as ARVALID\nARREADY is asserted and\ + \ deasserted during an interval when ARVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F008_S001_I002 + description: The Manager must not wait for the Subordinate to assert AWREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nAWREADY is asserted on or after\ + \ same cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on\ + \ or after same cycle as WVALID and AWVALID is de-asserted\nAWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nAWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F008_S001_I003 + description: The Manager must not wait for the Subordinate to assert WREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nWREADY is asserted on or\ + \ after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted\ + \ on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '005': !VerifItem + name: '005' + tag: VP_1_F008_S001_I005 + description: The Subordinate must not wait for the Manager to assert [B | + R]READY before asserting [B | R]VALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: No specific “observable checks” to be made in simulation. Testbench + will always provide response data independently of [B | R]READY. + pfc: 0 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/runme.sh b/cva6/docs/VerifPlans/AXI/runme.sh new file mode 100644 index 000000000..e2cfd351f --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="AXI" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="AXI" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck new file mode 100644 index 000000000..575c69110 --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck @@ -0,0 +1,998 @@ +(VIssue Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I9 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I0 +sVwid_order +p12 +I0 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_issue_req signals stable +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F000_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F000_S000_I000 +p34 +sVdescription +p35 +VThe \u201cinstr\u201d and \u201cmode\u201d signals remain stable during an Issue request transaction. +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VCheck that \u201cmode\u201d and \u201cinstr\u201d are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process) +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I4 +sVtest_type +p49 +I3 +sVcov_method +p50 +I2 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_mode signal value +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I2 +sg8 +g67 +sg23 +VVP_CVXIF_F000_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F000_S001_I000 +p79 +sg35 +VWhen issue transaction starts, instruction and current CPU mode are provided +p80 +sg37 +g38 +sg39 +VCheck that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +a(V001 +p87 +g1 +(g29 +g3 +Ntp88 +Rp89 +(dp90 +g8 +V001 +p91 +sg23 +VVP_CVXIF_F000_S001_I001 +p92 +sg35 +VCheck \u201cmode\u201d signal values. +p93 +sg37 +g38 +sg39 +VCheck that mode take a value that the CPU supports : Privilege level (2\u2019b00 = User, 2\u2019b01 = Supervisor, 2\u2019b10 = Reserved,\u000a 2\u2019b11 = Machine). +p94 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp95 +sg15 +(lp96 +sg57 +(lp97 +sg13 +(dp98 +g60 +I0 +ssbtp99 +asg62 +(lp100 +sg57 +(lp101 +sg13 +(dp102 +sbtp103 +a(V002_rs_valid signal transition order +p104 +g1 +(g18 +g3 +Ntp105 +Rp106 +(dp107 +g22 +I1 +sg8 +g104 +sg23 +VVP_CVXIF_F000_S002 +p108 +sg25 +(dp109 +sg12 +I2 +sg15 +(lp110 +(V000 +p111 +g1 +(g29 +g3 +Ntp112 +Rp113 +(dp114 +g8 +V000 +p115 +sg23 +VVP_CVXIF_F000_S002_I000 +p116 +sg35 +VDuring a transaction, each bit of \u201crs_valid\u201d can transition from 0 to 1 but are not allowed to transition back to 0. +p117 +sg37 +g38 +sg39 +VFor issue transaction which lasts more than one cycle, check that asserted \u201crs_valid\u201d signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] \u2192 0 cannot happen) +p118 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp119 +sg15 +(lp120 +sg57 +(lp121 +sg13 +(dp122 +g60 +I0 +ssbtp123 +asg62 +(lp124 +sg57 +(lp125 +sg13 +(dp126 +sbtp127 +a(V003_rs signal value +p128 +g1 +(g18 +g3 +Ntp129 +Rp130 +(dp131 +g22 +I3 +sg8 +g128 +sg23 +VVP_CVXIF_F000_S003 +p132 +sg25 +(dp133 +sg12 +I3 +sg15 +(lp134 +(V000 +p135 +g1 +(g29 +g3 +Ntp136 +Rp137 +(dp138 +g8 +V000 +p139 +sg23 +VVP_CVXIF_F000_S003_I000 +p140 +sg35 +VIf XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3). +p141 +sg37 +g38 +sg39 +VFor every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file. +p142 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp143 +sg15 +(lp144 +sg57 +(lp145 +sg13 +(dp146 +g60 +I0 +ssbtp147 +a(V001 +p148 +g1 +(g29 +g3 +Ntp149 +Rp150 +(dp151 +g8 +V001 +p152 +sg23 +VVP_CVXIF_F000_S003_I001 +p153 +sg35 +Vrs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid. +p154 +sg37 +g38 +sg39 +VCheck that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1. +p155 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I-1 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp156 +sg15 +(lp157 +sg57 +(lp158 +sg13 +(dp159 +g60 +I0 +ssbtp160 +a(V002 +p161 +g1 +(g29 +g3 +Ntp162 +Rp163 +(dp164 +g8 +V002 +p165 +sg23 +VVP_CVXIF_F000_S003_I002 +p166 +sg35 +VIf XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal. +p167 +sg37 +g38 +sg39 +VFor every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs. +p168 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp169 +sg15 +(lp170 +sg57 +(lp171 +sg13 +(dp172 +g60 +I0 +ssbtp173 +asg62 +(lp174 +sg57 +(lp175 +sg13 +(dp176 +sbtp177 +a(V004_Default value for unaccepted instruction +p178 +g1 +(g18 +g3 +Ntp179 +Rp180 +(dp181 +g22 +I1 +sg8 +g178 +sg23 +VVP_CVXIF_F000_S004 +p182 +sg25 +(dp183 +sg12 +I4 +sg15 +(lp184 +(V000 +p185 +g1 +(g29 +g3 +Ntp186 +Rp187 +(dp188 +g8 +V000 +p189 +sg23 +VVP_CVXIF_F000_S004_I000 +p190 +sg35 +VIf accept == 0 :\u000aWriteback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0. +p191 +sg37 +g38 +sg39 +VCheck that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0. +p192 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp193 +sg15 +(lp194 +sg57 +(lp195 +sg13 +(dp196 +g60 +I0 +ssbtp197 +asg62 +(lp198 +sg57 +(lp199 +sg13 +(dp200 +sbtp201 +a(V005_Illegal Instruction causes +p202 +g1 +(g18 +g3 +Ntp203 +Rp204 +(dp205 +g22 +I1 +sg8 +g202 +sg23 +VVP_CVXIF_F000_S005 +p206 +sg25 +(dp207 +sg12 +I5 +sg15 +(lp208 +(V000 +p209 +g1 +(g29 +g3 +Ntp210 +Rp211 +(dp212 +g8 +V000 +p213 +sg23 +VVP_CVXIF_F000_S005_I000 +p214 +sg35 +VThe CPU shall cause an illegal instruction if:\u000a- an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1)\u000a- neither to be valid by the CPU nor accepted by the coprocessor (accept = 0) +p215 +sg37 +g38 +sg39 +V- CPU causes illegal instruction for instruction accepted by the core and the coprocessor.\u000a- CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU +p216 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp217 +sg15 +(lp218 +sg57 +(lp219 +sg13 +(dp220 +g60 +I0 +ssbtp221 +asg62 +(lp222 +sg57 +(lp223 +sg13 +(dp224 +sbtp225 +a(V006_issue uniquness +p226 +g1 +(g18 +g3 +Ntp227 +Rp228 +(dp229 +g22 +I1 +sg8 +g226 +sg23 +VVP_CVXIF_F000_S006 +p230 +sg25 +(dp231 +sg12 +I6 +sg15 +(lp232 +(V000 +p233 +g1 +(g29 +g3 +Ntp234 +Rp235 +(dp236 +g8 +V000 +p237 +sg23 +VVP_CVXIF_F000_S006_I000 +p238 +sg35 +VCheck for issue id validity. +p239 +sg37 +g38 +sg39 +VCheck that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed). +p240 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I3 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp241 +sg15 +(lp242 +sg57 +(lp243 +sg13 +(dp244 +g60 +I0 +ssbtp245 +asg62 +(lp246 +sg57 +(lp247 +sg13 +(dp248 +sbtp249 +a(V007_coprocessor decoding +p250 +g1 +(g18 +g3 +Ntp251 +Rp252 +(dp253 +g22 +I1 +sg8 +g250 +sg23 +VVP_CVXIF_F000_S007 +p254 +sg25 +(dp255 +sg12 +I7 +sg15 +(lp256 +(V000 +p257 +g1 +(g29 +g3 +Ntp258 +Rp259 +(dp260 +g8 +V000 +p261 +sg23 +VVP_CVXIF_F000_S007_I000 +p262 +sg35 +VAccept = 1 if: \u000a- coprocessor can handle the instruction based on decoding \u201cinstr\u201dand "mode".\u000a- \u201cissue_valid\u201d == 1 and required bit(s) of \u201crs_valid\u201d are 1. +p263 +sg37 +g38 +sg39 +VTo be checked in coprocessor. +p264 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp265 +sg15 +(lp266 +sg57 +(lp267 +sg13 +(dp268 +g60 +I0 +ssbtp269 +asg62 +(lp270 +sg57 +(lp271 +sg13 +(dp272 +sbtp273 +a(V008_Transaction definition +p274 +g1 +(g18 +g3 +Ntp275 +Rp276 +(dp277 +g22 +I1 +sg8 +g274 +sg23 +VVP_CVXIF_F000_S008 +p278 +sg25 +(dp279 +sg12 +I8 +sg15 +(lp280 +(V000 +p281 +g1 +(g29 +g3 +Ntp282 +Rp283 +(dp284 +g8 +V000 +p285 +sg23 +VVP_CVXIF_F000_S008_I000 +p286 +sg35 +V\u201cissue_resp\u201d signals and \u201cissue_req\u201d signals are accepted when \u201cissue_valid\u201d == \u201cissue_ready\u201d == 1\u000a\u201cissue_resp\u201d is valid when "valid==ready==1".\u000a\u201cissue_req\u201d is valid when "valid==1" +p287 +sg37 +g38 +sg39 +VThe definition of a transaction. \u000aNot to be verified. +p288 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp289 +sg15 +(lp290 +sg57 +(lp291 +sg13 +(dp292 +g60 +I0 +ssbtp293 +asg62 +(lp294 +sg57 +(lp295 +sg13 +(dp296 +sbtp297 +asVrfu_list_0 +p298 +(lp299 +sg62 +(lp300 +sVvptool_gitrev +p301 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p302 +sVio_fmt_gitrev +p303 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p304 +sVconfig_gitrev +p305 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p306 +sVymlcfg_gitrev +p307 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p308 +sbtp309 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck new file mode 100644 index 000000000..1a42a8fd3 --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck @@ -0,0 +1,418 @@ +(VCommit Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I4 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I1 +sVwid_order +p12 +I1 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_commit_valid pulse +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F001_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F001_S000_I000 +p34 +sVdescription +p35 +VThe \u201ccommit_valid\u201d == 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not). +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VFor every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ). +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I4 +sVtest_type +p49 +I3 +sVcov_method +p50 +I2 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_commit transaction uniquness +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I1 +sg8 +g67 +sg23 +VVP_CVXIF_F001_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F001_S001_I000 +p79 +sg35 +VThere is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted). +p80 +sg37 +g38 +sg39 +VCheck that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed). +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I1 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +asg62 +(lp87 +sg57 +(lp88 +sg13 +(dp89 +sbtp90 +a(V002_commit transaction for every issue transaction +p91 +g1 +(g18 +g3 +Ntp92 +Rp93 +(dp94 +g22 +I1 +sg8 +g91 +sg23 +VVP_CVXIF_F001_S002 +p95 +sg25 +(dp96 +sg12 +I2 +sg15 +(lp97 +(V000 +p98 +g1 +(g29 +g3 +Ntp99 +Rp100 +(dp101 +g8 +V000 +p102 +sg23 +VVP_CVXIF_F001_S002_I000 +p103 +sg35 +V- The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction.\u000a- For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_validis 1 andcommit_killis 0) or that the instruction must be killed (commit_validis 1 andcommit_killis 1). +p104 +sg37 +g38 +sg39 +VCheck that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction. +p105 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp106 +sg15 +(lp107 +sg57 +(lp108 +sg13 +(dp109 +g60 +I0 +ssbtp110 +asg62 +(lp111 +sg57 +(lp112 +sg13 +(dp113 +sbtp114 +a(V003_Transaction definition +p115 +g1 +(g18 +g3 +Ntp116 +Rp117 +(dp118 +g22 +I1 +sg8 +g115 +sg23 +VVP_CVXIF_F001_S003 +p119 +sg25 +(dp120 +sg12 +I3 +sg15 +(lp121 +(V000 +p122 +g1 +(g29 +g3 +Ntp123 +Rp124 +(dp125 +g8 +V000 +p126 +sg23 +VVP_CVXIF_F001_S003_I000 +p127 +sg35 +VThe signals incommitare valid whencommit_validis 1. +p128 +sg37 +g38 +sg39 +VThe definition of a transaction.\u000aNot to be verified. +p129 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I-1 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp130 +sg15 +(lp131 +sg57 +(lp132 +sg13 +(dp133 +g60 +I0 +ssbtp134 +asg62 +(lp135 +sg57 +(lp136 +sg13 +(dp137 +sbtp138 +asVrfu_list_0 +p139 +(lp140 +sg62 +(lp141 +sVvptool_gitrev +p142 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p143 +sVio_fmt_gitrev +p144 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p145 +sVconfig_gitrev +p146 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p147 +sVymlcfg_gitrev +p148 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p149 +sbtp150 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck new file mode 100644 index 000000000..7211f1b9e --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck @@ -0,0 +1,860 @@ +(VResult Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I8 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I2 +sVwid_order +p12 +I2 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_no speculative result transaction +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F002_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F002_S000_I000 +p34 +sVdescription +p35 +VA coprocessor is not allowed to perform speculative result transactions. +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VThere is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0). +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I11 +sVtest_type +p49 +I10 +sVcov_method +p50 +I10 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_out of order result transaction +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I1 +sg8 +g67 +sg23 +VVP_CVXIF_F002_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F002_S001_I000 +p79 +sg35 +VA coprocessor is allowed to provide results to the core in an out of order fashion. +p80 +sg37 +g38 +sg39 +VCheck that the CPU is able to receive the result in an out of order fashion. +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +asg62 +(lp87 +sg57 +(lp88 +sg13 +(dp89 +sbtp90 +a(V002_result transaction uniquness +p91 +g1 +(g18 +g3 +Ntp92 +Rp93 +(dp94 +g22 +I1 +sg8 +g91 +sg23 +VVP_CVXIF_F002_S002 +p95 +sg25 +(dp96 +sg12 +I2 +sg15 +(lp97 +(V000 +p98 +g1 +(g29 +g3 +Ntp99 +Rp100 +(dp101 +g8 +V000 +p102 +sg23 +VVP_CVXIF_F002_S002_I000 +p103 +sg35 +VEach accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU\u2019s register file). +p104 +sg37 +g38 +sg39 +VThere is an unique result transaction for every accepted and commit instruction. +p105 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp106 +sg15 +(lp107 +sg57 +(lp108 +sg13 +(dp109 +g60 +I0 +ssbtp110 +asg62 +(lp111 +sg57 +(lp112 +sg13 +(dp113 +sbtp114 +a(V003_result packet stability +p115 +g1 +(g18 +g3 +Ntp116 +Rp117 +(dp118 +g22 +I1 +sg8 +g115 +sg23 +VVP_CVXIF_F002_S003 +p119 +sg25 +(dp120 +sg12 +I3 +sg15 +(lp121 +(V000 +p122 +g1 +(g29 +g3 +Ntp123 +Rp124 +(dp125 +g8 +V000 +p126 +sg23 +VVP_CVXIF_F002_S003_I000 +p127 +sg35 +VThe signals in result shall remain stable during a result transaction (except data ...) +p128 +sg37 +g38 +sg39 +VCheck that result signals (except data) are stable during result transaction (result_valid==1 jusqu' valid==ready ==1) +p129 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp130 +sg15 +(lp131 +sg57 +(lp132 +sg13 +(dp133 +g60 +I0 +ssbtp134 +asg62 +(lp135 +sg57 +(lp136 +sg13 +(dp137 +sbtp138 +a(V004_data stability +p139 +g1 +(g18 +g3 +Ntp140 +Rp141 +(dp142 +g22 +I1 +sg8 +g139 +sg23 +VVP_CVXIF_F002_S004 +p143 +sg25 +(dp144 +sg12 +I4 +sg15 +(lp145 +(V000 +p146 +g1 +(g29 +g3 +Ntp147 +Rp148 +(dp149 +g8 +V000 +p150 +sg23 +VVP_CVXIF_F002_S004_I000 +p151 +sg35 +VData is only required to remain stable during result transactions in which "we" is not 0. +p152 +sg37 +g38 +sg39 +VCheck that "data" remains stable when we==1. +p153 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp154 +sg15 +(lp155 +sg57 +(lp156 +sg13 +(dp157 +g60 +I0 +ssbtp158 +asg62 +(lp159 +sg57 +(lp160 +sg13 +(dp161 +sbtp162 +a(V005_synchronous exception +p163 +g1 +(g18 +g3 +Ntp164 +Rp165 +(dp166 +g22 +I3 +sg8 +g163 +sg23 +VVP_CVXIF_F002_S005 +p167 +sg25 +(dp168 +sg12 +I5 +sg15 +(lp169 +(V000 +p170 +g1 +(g29 +g3 +Ntp171 +Rp172 +(dp173 +g8 +V000 +p174 +sg23 +VVP_CVXIF_F002_S005_I000 +p175 +sg35 +VTheexcis used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed. +p176 +sg37 +g38 +sg39 +VCheck that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed. +p177 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp178 +sg15 +(lp179 +sg57 +(lp180 +sg13 +(dp181 +g60 +I0 +ssbtp182 +a(V001 +p183 +g1 +(g29 +g3 +Ntp184 +Rp185 +(dp186 +g8 +V001 +p187 +sg23 +VVP_CVXIF_F002_S005_I001 +p188 +sg35 +Vexccodeprovides the least significant bits of the exception code bitfield of themcauseCSR. +p189 +sg37 +g38 +sg39 +VCheck that exccode signal is the value of the mcause CSR when exc == 1. +p190 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp191 +sg15 +(lp192 +sg57 +(lp193 +sg13 +(dp194 +g60 +I0 +ssbtp195 +a(V002 +p196 +g1 +(g29 +g3 +Ntp197 +Rp198 +(dp199 +g8 +V002 +p200 +sg23 +VVP_CVXIF_F002_S005_I002 +p201 +sg35 +V"we"shall be driven to 0 by the coprocessor for synchronous exceptions. +p202 +sg37 +g38 +sg39 +VCheck that "we" signal == 0 when exc == 1. +p203 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I-1 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp204 +sg15 +(lp205 +sg57 +(lp206 +sg13 +(dp207 +g60 +I0 +ssbtp208 +asg62 +(lp209 +sg57 +(lp210 +sg13 +(dp211 +sbtp212 +a(V006_"we" value when dualwrite +p213 +g1 +(g18 +g3 +Ntp214 +Rp215 +(dp216 +g22 +I1 +sg8 +g213 +sg23 +VVP_CVXIF_F002_S006 +p217 +sg25 +(dp218 +sg12 +I6 +sg15 +(lp219 +(V000 +p220 +g1 +(g29 +g3 +Ntp221 +Rp222 +(dp223 +g8 +V000 +p224 +sg23 +VVP_CVXIF_F002_S006_I000 +p225 +sg35 +Vweis 2 bits wide whenXLEN`= 32 andX_RFW_WIDTH= 64, and 1 bit wide otherwise. If"we"is 2 bits wide, thenwe[1]is only allowed to be 1 ifwe[0]is 1 as well (i.e. for dual writeback). +p226 +sg37 +g38 +sg39 +VFor dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1. +p227 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp228 +sg15 +(lp229 +sg57 +(lp230 +sg13 +(dp231 +g60 +I0 +ssbtp232 +asg62 +(lp233 +sg57 +(lp234 +sg13 +(dp235 +sbtp236 +a(V007_proper result transaction +p237 +g1 +(g18 +g3 +Ntp238 +Rp239 +(dp240 +g22 +I1 +sg8 +g237 +sg23 +VVP_CVXIF_F002_S007 +p241 +sg25 +(dp242 +sg12 +I7 +sg15 +(lp243 +(V000 +p244 +g1 +(g29 +g3 +Ntp245 +Rp246 +(dp247 +g8 +V000 +p248 +sg23 +VVP_CVXIF_F002_S007_I000 +p249 +sg35 +VResult transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1. +p250 +sg37 +g38 +sg39 +VCheck that result transaction ends properly. +p251 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp252 +sg15 +(lp253 +sg57 +(lp254 +sg13 +(dp255 +g60 +I0 +ssbtp256 +asg62 +(lp257 +sg57 +(lp258 +sg13 +(dp259 +sbtp260 +asVrfu_list_0 +p261 +(lp262 +sg62 +(lp263 +sVvptool_gitrev +p264 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p265 +sVio_fmt_gitrev +p266 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p267 +sVconfig_gitrev +p268 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p269 +sVymlcfg_gitrev +p270 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p271 +sbtp272 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/runme.sh b/cva6/docs/VerifPlans/CVXIF/runme.sh new file mode 100644 index 000000000..1701a0ebe --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="CVXIF" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="CVXIF" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP000.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP000.yml new file mode 100644 index 000000000..aa8e96505 --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP000.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: 'Fetching ' +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_Fetching: !Subfeature + name: 000_Fetching + tag: VP_FENCEI_F000_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F000_S000_I000 + description: Instruction data for the next PC must be fetched after the fence.i + instruction has executed (because only then can data-side stores have completed + and caches have been updated). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that after a fence.i instruction retires then instr-side + obi fetches the next instruction to be executed. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP001.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP001.yml new file mode 100644 index 000000000..b779d3615 --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP001.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 1 +name: StoresVisible +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_StoresVisible: !Subfeature + name: 000_StoresVisible + tag: VP_FENCEI_F001_S000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F001_S000_I000 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Do a fencei, but right before the fencei do a store to the instruction + following the fencei, then see that the newly stored value is executed instead + of the old instruction (e.g. change addi to use a different immediate). + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO must be added to regression lists! + - '001': !VerifItem + name: '001' + tag: VP_FENCEI_F001_S000_I001 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Do a fencei followed by any instruction, but let the environment + detect when the fencei is being executed and change the memory holding the + next instruction, then see that the old instruction is not executed. + pfc: -1 + test_type: 2 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! + - '002': !VerifItem + name: '002' + tag: VP_FENCEI_F001_S000_I002 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Let the instruction right before a fence.i write a different + instruction to the address following the fence.i, then observe that the + written instruction is executed instead of the original one and that no + side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit + instructions to force a noticable difference). + pfc: 1 + test_type: 1 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FENCEI_F001_S000_I003 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Check that after having read one value from an address, then + after storing a value to that same address, if executing that address then + the value shall always be that which was written (should work well in both + sim/formal). + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: TODO missing assert. (Note was ignored because of the difficulty + of writing this as an assert for fv.)! +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP002.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP002.yml new file mode 100644 index 000000000..5d4385775 --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP002.yml @@ -0,0 +1,279 @@ +!Feature +next_elt_id: 10 +name: ExternalHandshake +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_ReqHigh: !Subfeature + name: 000_ReqHigh + tag: VP_FENCEI_F002_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S000_I000 + description: When executing a fence.i instruction, fencei_flush_req_o shall + rise sometime before executing the next instruction. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when executing a fence.i instruction there will be + a rising req before has retired. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_ReqWaitLsu: !Subfeature + name: 001_ReqWaitLsu + tag: VP_FENCEI_F002_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S001_I000 + description: When executing a fence.i instruction, if there is an ongoing + store instruction (not limited to rv32i) that has not completed (data_rvalid_i + clocked in as 1), then fencei_flush_req_o shall be low. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Make sure a store instruction is run right before a fence.i, + and (possibly using obi stalls) ensure that the fence.i is pending retirement + but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o + was low until this point where it now goes high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! +- 002_ReqWaitWritebuffer: !Subfeature + name: 002_ReqWaitWritebuffer + tag: VP_FENCEI_F002_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S002_I000 + description: When executing a fence.i instruction, if the write buffer is + not empty, then fencei_flush_req_o shall be low until the write buffer has + been emptied and the corresponding data_rvalid_i have been clocked in as + 1. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Fill up the write buffer prior to executing a fence.i and ensure + that fencei_flush_req_o holds off going high until the write buffer to has + been emptied. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! +- 003_ReqWaitXinterface: !Subfeature + name: 003_ReqWaitXinterface + tag: VP_FENCEI_F002_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S003_I000 + description: When executing a fence.i instruction, if the X interface is busy + with any store operations, then fencei_flush_req_o shall be low until all + the store operations are done + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Issue one or more store instructions that uses the X interface + and ensure that fencei_flush_req_o waits until the stores have all completed + before going high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_ReqWaitObi: !Subfeature + name: 004_ReqWaitObi + tag: VP_FENCEI_F002_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S004_I000 + description: fencei_flush_req_o shall not go high while there are outstanding + stores on the obi bus. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check vs the OBI monitors that there are no outstanding stores + at the time fencei_flush_req_o goes high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_ReqLow: !Subfeature + name: 005_ReqLow + tag: VP_FENCEI_F002_S005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S005_I000 + description: When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o + and fencei_flush_ack_i has been sampled high simultaneously, and then then + it shall go low. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when fencei_flush_req_o is high, then it behaves correctly + with regards to fencei_flush_ack_i. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AckChange: !Subfeature + name: 006_AckChange + tag: VP_FENCEI_F002_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S006_I000 + description: 'fencei_flush_ack_i is allowed to change freely on any clock + cycle: It can be permanently high, go high without fence.i and retract, + go high at the same cycle as the req, it can delay arbitrarily after req + and then go high, etc' + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Drive ack to test all permutations of rising/falling before/after/on + req, acking without req, retracting an early ack, delaying ack after req, + etc. + pfc: 0 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AckWithold: !Subfeature + name: 007_AckWithold + tag: VP_FENCEI_F002_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S007_I000 + description: If req is high, but ack never comes, then the core keeps on stalling + and the fence.i is blocked from completing. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Upon a req, try witholding ack for a long time and see that the + fence.i can be stalled arbitrarily long (should have covers for ack delays + of at least {[0:5]}). + pfc: 4 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_BranchInitiated: !Subfeature + name: 008_BranchInitiated + tag: VP_FENCEI_F002_S008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S008_I000 + description: After req and ack has been sampled simultaneously high and when + req is low again, then the core takes a branch to the instruction after + the fence.i instruction. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that the branch is taken at the point after req and ack + has been simultaneously high. + pfc: 4 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_ShadowingBranch: !Subfeature + name: 009_ShadowingBranch + tag: VP_FENCEI_F002_S009 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S009_I000 + description: If the fence.i ends up not retiring because it was preceeded + by a taken branch or a jump, then the fencei_flush_req_o shall not go high + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Take a branch or do a jump to skip a fence.i, and ensure that + fencei_flush_req_o doesn't go high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP003.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP003.yml new file mode 100644 index 000000000..86c8993b5 --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP003.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: MultiCycle +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_MultiCycle: !Subfeature + name: 000_MultiCycle + tag: VP_FENCEI_F003_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F003_S000_I000 + description: Given zero stalls on neither instr-side and data-side obi nor + on fencei_flush_ack_i, then the execution of fence.i takes a fixed number + of cycles. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that, given ideal conditions, the cycle count of fence.i + is as expected. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP004.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP004.yml new file mode 100644 index 000000000..00b4775d3 --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP004.yml @@ -0,0 +1,69 @@ +!Feature +next_elt_id: 2 +name: StoresComplete +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_StoresComplete: !Subfeature + name: 000_StoresComplete + tag: VP_FENCEI_F004_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F004_S000_I000 + description: Any store instruction that is successfully executed before a + fence.i will fully complete and have its effect visible (this is not about + syncronization with instruction fetch, but rather seeing that the stores + are not aborted). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that all stores (either to next pc or other places) preceding + a fence.i will complete on the bus (excluding exceptions/interrupts/etc) + and be readable afterwards (particularly, ensure that the write buffer isn't + just purged). + pfc: 1 + test_type: 1 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' +- 001_StoresComplete: !Subfeature + name: 001_StoresComplete + tag: VP_FENCEI_F004_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F004_S001_I000 + description: Any store instruction that is successfully executed before a + fence.i will fully complete and have its effect visible (this is not about + syncronization with instruction fetch, but rather seeing that the stores + are not aborted). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that all stores (either to next pc or other places) preceding + a fence.i will complete on the bus (excluding exceptions/interrupts/etc) + and be readable afterwards (particularly, ensure that the write buffer isn't + just purged). + pfc: 3 + test_type: 3 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP005.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP005.yml new file mode 100644 index 000000000..65fe3432f --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP005.yml @@ -0,0 +1,37 @@ +!Feature +next_elt_id: 1 +name: Flush +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_Flush: !Subfeature + name: 000_Flush + tag: VP_FENCEI_F005_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F005_S000_I000 + description: When fence.i is executed, then any prefetched instructions shall + be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, + write buffer is flushed, and data_req_o is eventually supressed. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that a fence.i will cause flushing of the pipeline, prefetcher, + write buffer, and data_req_o. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: TODO missing assert. (Have not checked/covered that the pipeline/writebuffer + content is actually purged. Or that any memory change WILL be the next instr + word.)! +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/VP_IP006.yml b/cva6/docs/VerifPlans/FENCEI/VP_IP006.yml new file mode 100644 index 000000000..76415753b --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/VP_IP006.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: UnusedFields +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_UnusedFields: !Subfeature + name: 000_UnusedFields + tag: VP_FENCEI_F006_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F006_S000_I000 + description: imm[11:0], rs1, rd are reserved for future extensions, and implementations + shall ignore them + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Try giving random values in those fields and see that all else + works as expected + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FENCEI/runme.sh b/cva6/docs/VerifPlans/FENCEI/runme.sh new file mode 100644 index 000000000..1a172b8ae --- /dev/null +++ b/cva6/docs/VerifPlans/FENCEI/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="FENCEI" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="FENCEI" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck deleted file mode 100644 index a5d1c4861..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck +++ /dev/null @@ -1,1198 +0,0 @@ -(VPC generation stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_BTB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I6 -sg8 -g17 -sVtag -p23 -VVP_IP003_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F003_S001_I000 -p34 -sVdescription -p35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p38 -sVverif_goals -p39 -VExecute a JALR instruction with a valid address in BTB which is not a misprediction. Check that instruction queue is not flushed. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I4 -sVtest_type -p44 -I0 -sVcov_method -p45 -I1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F003_S001_I001 -p62 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p63 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p64 -sg39 -VExecute a JALR instruction with a valid address in BTB which is a misprediction. -p65 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_FRONTEND_F003_S001_I002 -p76 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB.\u000a\u000aElse JALR is not considered as a control flow instruction, which will generate a mispredict. -p77 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p78 -sg39 -VExecute test with JALR instructions. Functional cov: JALR is executed and BTB output is not valid. -p79 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V002_BHT -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I4 -sg8 -g90 -sg23 -VVP_IP003_P002 -p94 -sg25 -(dp95 -sg12 -I2 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_FRONTEND_F003_S002_I000 -p102 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p103 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p104 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is not a misprediction. Check that instruction queue is not flushed. -p105 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -Vlock_status -p110 -I0 -ssbtp111 -a(V001 -p112 -g1 -(g29 -g3 -Ntp113 -Rp114 -(dp115 -g8 -V001 -p116 -sg23 -VVP_FRONTEND_F003_S002_I001 -p117 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p118 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p119 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is a misprediction. -p120 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp121 -sg15 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -Vlock_status -p125 -I0 -ssbtp126 -a(V002 -p127 -g1 -(g29 -g3 -Ntp128 -Rp129 -(dp130 -g8 -V002 -p131 -sg23 -VVP_FRONTEND_F003_S002_I002 -p132 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p133 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p134 -sg39 -VExecute test with BRANCH instructions. Functional cov: a BRANCH is executed, BTB output is not valid and the branch is taken. -p135 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp136 -sg15 -(lp137 -sg52 -(lp138 -sg13 -(dp139 -g125 -I0 -ssbtp140 -asg85 -(lp141 -sg52 -(lp142 -sg13 -(dp143 -sbtp144 -a(V003_RAS -p145 -g1 -(g18 -g3 -Ntp146 -Rp147 -(dp148 -g22 -I4 -sg8 -g145 -sg23 -VVP_IP003_P003 -p149 -sg25 -(dp150 -sg12 -I3 -sg15 -(lp151 -(V000 -p152 -g1 -(g29 -g3 -Ntp153 -Rp154 -(dp155 -g8 -V000 -p156 -sg23 -VVP_FRONTEND_F003_S003_I000 -p157 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p158 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p159 -sg39 -VExecute a RET instruction with a valid address in RAS. Check that instruction queue is not flushed. -p160 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp161 -sg15 -(lp162 -sg52 -(lp163 -sg13 -(dp164 -g125 -I0 -ssbtp165 -a(V001 -p166 -g1 -(g29 -g3 -Ntp167 -Rp168 -(dp169 -g8 -V001 -p170 -sg23 -VVP_FRONTEND_F003_S003_I001 -p171 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p172 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p173 -sg39 -VExecute a RET instruction with a valid address in RAS which is a misprediction. -p174 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp175 -sg15 -(lp176 -sg52 -(lp177 -sg13 -(dp178 -g125 -I0 -ssbtp179 -a(V002 -p180 -g1 -(g29 -g3 -Ntp181 -Rp182 -(dp183 -g8 -V002 -p184 -sg23 -VVP_FRONTEND_F003_S003_I002 -p185 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p186 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p187 -sg39 -VExecute test with RET instructions. Functional cov: RET is executed and RAS output is not valid. -p188 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp189 -sg15 -(lp190 -sg52 -(lp191 -sg13 -(dp192 -g125 -I0 -ssbtp193 -asg85 -(lp194 -sg52 -(lp195 -sg13 -(dp196 -sbtp197 -a(V004_Return from environment call -p198 -g1 -(g18 -g3 -Ntp199 -Rp200 -(dp201 -g22 -I2 -sg8 -g198 -sg23 -VVP_IP003_P004 -p202 -sg25 -(dp203 -sg12 -I4 -sg15 -(lp204 -(V000 -p205 -g1 -(g29 -g3 -Ntp206 -Rp207 -(dp208 -g8 -V000 -p209 -sg23 -VVP_FRONTEND_F003_S004_I000 -p210 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p211 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p212 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call.\u000a\u000a* Check by assertion that when machine return occurs the mepc address is fetched.\u000a* Functional cov: execute a machine return. -p213 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp214 -sg15 -(lp215 -sg52 -(lp216 -sg13 -(dp217 -g125 -I0 -ssbtp218 -a(V001 -p219 -g1 -(g29 -g3 -Ntp220 -Rp221 -(dp222 -g8 -V001 -p223 -sg23 -VVP_FRONTEND_F003_S004_I001 -p224 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p225 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p226 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call.\u000a\u000a* Check by assertion that when supervisor return occurs the sepc address is fetched.\u000a* Functional cov: execute a supervisor return. -p227 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I24 -sg47 -g42 -sg48 -g42 -sg49 -(lp228 -sg15 -(lp229 -sg52 -(lp230 -sg13 -(dp231 -g125 -I0 -ssbtp232 -asg85 -(lp233 -sg52 -(lp234 -sg13 -(dp235 -sbtp236 -a(V005_Exception/Interrupt -p237 -g1 -(g18 -g3 -Ntp238 -Rp239 -(dp240 -g22 -I2 -sg8 -g237 -sg23 -VVP_IP003_P005 -p241 -sg25 -(dp242 -sg12 -I5 -sg15 -(lp243 -(V000 -p244 -g1 -(g29 -g3 -Ntp245 -Rp246 -(dp247 -g8 -V000 -p248 -sg23 -VVP_FRONTEND_F003_S005_I000 -p249 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p250 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p251 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in machine mode and generates a machine exception by UVM. Check by assertion that when machine exception occurs the machine address is fetched. Functional cov: exception occurs in machine mode. -p252 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp253 -sg15 -(lp254 -sg52 -(lp255 -sg13 -(dp256 -g125 -I0 -ssbtp257 -a(V001 -p258 -g1 -(g29 -g3 -Ntp259 -Rp260 -(dp261 -g8 -V001 -p262 -sg23 -VVP_FRONTEND_F003_S005_I001 -p263 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p264 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p265 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in supervisor mode and generates a supervisor exception by UVM. Check by assertion that when supervisor exception occurs the supervisor address is fetched. functional cov: exception occurs in supervisor mode. -p266 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp267 -sg15 -(lp268 -sg52 -(lp269 -sg13 -(dp270 -g125 -I0 -ssbtp271 -asg85 -(lp272 -sg52 -(lp273 -sg13 -(dp274 -sbtp275 -a(V006_Pipeline flush -p276 -g1 -(g18 -g3 -Ntp277 -Rp278 -(dp279 -g22 -I2 -sg8 -g276 -sg23 -VVP_IP003_P006 -p280 -sg25 -(dp281 -sg12 -I6 -sg15 -(lp282 -(V000 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V000 -p287 -sg23 -VVP_FRONTEND_F003_S006_I000 -p288 -sg35 -VFRONTEND starts fetching from the next instruction again in order to take the up-dated information into account -p289 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Pipeline flush -p290 -sg39 -V[no need to verify this point] -p291 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp292 -sg15 -(lp293 -sg52 -(lp294 -sg13 -(dp295 -g125 -I0 -ssbtp296 -asg85 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -sbtp300 -a(V007_Debug -p301 -g1 -(g18 -g3 -Ntp302 -Rp303 -(dp304 -g22 -I1 -sg8 -g301 -sg23 -VVP_IP003_P007 -p305 -sg25 -(dp306 -sg12 -I7 -sg15 -(lp307 -(V000 -p308 -g1 -(g29 -g3 -Ntp309 -Rp310 -(dp311 -g8 -V000 -p312 -sg23 -VVP_FRONTEND_F003_S007_I000 -p313 -sg35 -VThe debug jump is requested by CSR. The address to be jumped into is HW coded. -p314 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Debug -p315 -sg39 -VUVM generates a debug request to jump into debug handler. Check by assertion that the HW coded debug address is fetched. Functional cov: debug mode occurs -p316 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp317 -sg15 -(lp318 -sg52 -(lp319 -sg13 -(dp320 -g125 -I0 -ssbtp321 -asg85 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -sbtp325 -a(V008_Address mapping change -p326 -g1 -(g18 -g3 -Ntp327 -Rp328 -(dp329 -g22 -I1 -sg8 -g326 -sg23 -VVP_IP003_P008 -p330 -sg25 -(dp331 -sg12 -I8 -sg15 -(lp332 -(V000 -p333 -g1 -(g29 -g3 -Ntp334 -Rp335 -(dp336 -g8 -V000 -p337 -sg23 -VVP_FRONTEND_F003_S008_I000 -p338 -sg35 -VAll program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline and TLBs -p339 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p340 -sg39 -VExecute a address mapping change, then execute a fence.vm instruction, and continue the execution. -p341 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp342 -sg15 -(lp343 -sg52 -(lp344 -sg13 -(dp345 -g125 -I0 -ssbtp346 -asg85 -(lp347 -sg52 -(lp348 -sg13 -(dp349 -sbtp350 -a(V009_Pc gen priority -p351 -g1 -(g18 -g3 -Ntp352 -Rp353 -(dp354 -g22 -I3 -sg8 -g351 -sg23 -VVP_IP003_P009 -p355 -sg25 -(dp356 -sg12 -I9 -sg15 -(lp357 -(V000 -p358 -g1 -(g29 -g3 -Ntp359 -Rp360 -(dp361 -g8 -V000 -p362 -sg23 -VVP_FRONTEND_F003_S009_I000 -p363 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p364 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p365 -sg39 -VUse arc_test executing return from env call and generate Exceptions by UVM during reset, Branch predict, default, mispredict, replay and return from env call. Functional cov: monitor the 6 events -p366 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp367 -sg15 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -g125 -I0 -ssbtp371 -a(V002 -p372 -g1 -(g29 -g3 -Ntp373 -Rp374 -(dp375 -g8 -V002 -p376 -sg23 -VVP_FRONTEND_F003_S009_I002 -p377 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p378 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p379 -sg39 -V[other cases to be elaborated] -p380 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp381 -sg15 -(lp382 -sg52 -(lp383 -sg13 -(dp384 -g125 -I0 -ssbtp385 -asg85 -(lp386 -sg52 -(lp387 -sg13 -(dp388 -sbtp389 -asVrfu_list_0 -p390 -(lp391 -sg85 -(lp392 -sVvptool_gitrev -p393 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p394 -sVio_fmt_gitrev -p395 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p396 -sVconfig_gitrev -p397 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p398 -sVymlcfg_gitrev -p399 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p400 -sbtp401 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml new file mode 100644 index 000000000..83439bc39 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml @@ -0,0 +1,422 @@ +!Feature +next_elt_id: 10 +name: PC generation stage +id: 3 +display_order: 3 +subfeatures: !!omap +- 001_BTB: !Subfeature + name: 001_BTB + tag: VP_IP003_P001 + next_elt_id: 6 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S001_I000 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S001_I001 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S001_I002 + description: "If instruction is a JALR and BTB (Branch Target Buffer) returns\ + \ a valid address, next PC is predicted by BTB.\n\nElse JALR is not considered\ + \ as a control flow instruction, which will generate a mispredict." + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with JALR instructions. Functional cov: JALR is + executed and BTB output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 002_BHT: !Subfeature + name: 002_BHT + tag: VP_IP003_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S002_I000 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S002_I001 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S002_I002 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with BRANCH instructions. Functional cov: a BRANCH + is executed, BTB output is not valid and the branch is taken.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 003_RAS: !Subfeature + name: 003_RAS + tag: VP_IP003_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S003_I000 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS. Check + that instruction queue is not flushed. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S003_I001 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS which is + a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S003_I002 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with RET instructions. Functional cov: RET is executed + and RAS output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 004_Return from environment call: !Subfeature + name: 004_Return from environment call + tag: VP_IP003_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S004_I000 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a arc_test returning from machine env call.\n\n* Check by assertion\ + \ that when machine return occurs the mepc address is fetched.\n* Functional\ + \ cov: execute a machine return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S004_I001 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a returning from supervisor env call.\n\n* Check by assertion that\ + \ when supervisor return occurs the sepc address is fetched.\n* Functional\ + \ cov: execute a supervisor return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 24 + coverage_loc: '' + comments: '' +- 005_Exception/Interrupt: !Subfeature + name: 005_Exception/Interrupt + tag: VP_IP003_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S005_I000 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in machine mode and generates + a machine exception by UVM. Check by assertion that when machine exception + occurs the machine address is fetched. Functional cov: exception occurs + in machine mode.' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S005_I001 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in supervisor mode and generates + a supervisor exception by UVM. Check by assertion that when supervisor exception + occurs the supervisor address is fetched. functional cov: exception occurs + in supervisor mode.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' +- 006_Pipeline flush: !Subfeature + name: 006_Pipeline flush + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S006_I000 + description: FRONTEND starts fetching from the next instruction again in order + to take the up-dated information into account + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Pipeline flush + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[no need to verify this point]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +- 007_Debug: !Subfeature + name: 007_Debug + tag: VP_IP003_P007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S007_I000 + description: The debug jump is requested by CSR. The address to be jumped + into is HW coded. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Debug + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'UVM generates a debug request to jump into debug handler. Check + by assertion that the HW coded debug address is fetched. Functional cov: + debug mode occurs' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 32 + coverage_loc: '' + comments: '' +- 008_Address mapping change: !Subfeature + name: 008_Address mapping change + tag: VP_IP003_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S008_I000 + description: All program counters are logical addressed. If the logical to + physical mapping changes a fence.vm instruction should used to flush the + pipeline and TLBs + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a address mapping change, then execute a fence.vm instruction, + and continue the execution. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 009_Pc gen priority: !Subfeature + name: 009_Pc gen priority + tag: VP_IP003_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S009_I000 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Use arc_test executing return from env call and generate Exceptions + by UVM during reset, Branch predict, default, mispredict, replay and return + from env call. Functional cov: monitor the 6 events' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S009_I002 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[other cases to be elaborated]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck deleted file mode 100644 index 7af6e80e4..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VBTB -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F004_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BTB -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP004_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F004_S001_I000 -p74 -sg35 -VThe information is stored in a 8 entry table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p76 -sg39 -VConfirm that the best configuration for BTB entry number is 8 by monitoring the Coremark performance and silicon footprint, the configuration without BTB is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP004_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F004_S002_I000 -p99 -sg35 -VWhen a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p101 -sg39 -VWhen a mis predict occurs caused by JALR, check that info is stored in BTB -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP004_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F004_S003_I000 -p124 -sg35 -VThe BTB is not updated if processor is in debug mode. -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml new file mode 100644 index 000000000..9b39ea709 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: BTB +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP004_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S001_I000 + description: The information is stored in a 8 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BTB entry number is 8 + by monitoring the Coremark performance and silicon footprint, the configuration + without BTB is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP004_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S002_I000 + description: When a unconditional jumps to a register (JALR instruction) is + mispredicted by the EXECUTE, the relative information is stored into the + BTB, that is to say the JALR PC and the target address. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by JALR, check that info is + stored in BTB + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_debug is not intrusive: !Subfeature + name: 003_debug is not intrusive + tag: VP_IP004_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S003_I000 + description: The BTB is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck deleted file mode 100644 index 56b70c2b1..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck +++ /dev/null @@ -1,508 +0,0 @@ -(VBHT -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F005_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BHT -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V002_table update -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP005_P002 -p66 -sg25 -(dp67 -sg12 -I2 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F005_S002_I000 -p74 -sg35 -VWhen a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p76 -sg39 -VWhen a mis predict occurs caused by BRANCH, check that info is stored in BHT -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V003_saturation -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I2 -sg8 -g87 -sg23 -VVP_IP005_P003 -p91 -sg25 -(dp92 -sg12 -I3 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F005_S003_I000 -p99 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p101 -sg39 -VExecute a serie of taken and not taken branch to check the saturation mechanism -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I-1 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -a(V001 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V001 -p112 -sg23 -VVP_FRONTEND_F005_S003_I001 -p113 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p114 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p115 -sg39 -VVerify the saturation mechnism is optimal. Modify the saturation mechanism by removing/adding one stage, and check the Coremark performance evolution -p116 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -asg57 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -sbtp125 -a(V004_Table depth -p126 -g1 -(g18 -g3 -Ntp127 -Rp128 -(dp129 -g22 -I1 -sg8 -g126 -sg23 -VVP_IP005_P004 -p130 -sg25 -(dp131 -sg12 -I4 -sg15 -(lp132 -(V000 -p133 -g1 -(g29 -g3 -Ntp134 -Rp135 -(dp136 -g8 -V000 -p137 -sg23 -VVP_FRONTEND_F005_S004_I000 -p138 -sg35 -VThe information is stored in a 1024 entry table. -p139 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p140 -sg39 -VConfirm that the best configuration for BHT entry number is 1024 by monitoring the Coremark performance and silicon footprint, the configuration without BHT is to be challenged too. -p141 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp142 -sg15 -(lp143 -sg52 -(lp144 -sg13 -(dp145 -g55 -I0 -ssbtp146 -asg57 -(lp147 -sg52 -(lp148 -sg13 -(dp149 -sbtp150 -a(V005_Debug is not intrusive -p151 -g1 -(g18 -g3 -Ntp152 -Rp153 -(dp154 -g22 -I1 -sg8 -g151 -sg23 -VVP_IP005_P005 -p155 -sg25 -(dp156 -sg12 -I5 -sg15 -(lp157 -(V000 -p158 -g1 -(g29 -g3 -Ntp159 -Rp160 -(dp161 -g8 -V000 -p162 -sg23 -VVP_FRONTEND_F005_S005_I000 -p163 -sg35 -VThe BHT is not updated if processor is in debug mode. -p164 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p165 -sg39 -VExecute a debug session, check that the table content is not modified -p166 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp167 -sg15 -(lp168 -sg52 -(lp169 -sg13 -(dp170 -g55 -I0 -ssbtp171 -asg57 -(lp172 -sg52 -(lp173 -sg13 -(dp174 -sbtp175 -asVrfu_list_0 -p176 -(lp177 -sg57 -(lp178 -sVvptool_gitrev -p179 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p180 -sVio_fmt_gitrev -p181 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p182 -sVconfig_gitrev -p183 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p184 -sVymlcfg_gitrev -p185 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p186 -sbtp187 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml new file mode 100644 index 000000000..df4babd4d --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml @@ -0,0 +1,152 @@ +!Feature +next_elt_id: 6 +name: BHT +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP005_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 002_table update: !Subfeature + name: 002_table update + tag: VP_IP005_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S002_I000 + description: When a branch instruction is resolved by the EXECUTE, the relative + information is stored in the Branch History Table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by BRANCH, check that info is + stored in BHT + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_saturation: !Subfeature + name: 003_saturation + tag: VP_IP005_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S003_I000 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a serie of taken and not taken branch to check the saturation + mechanism + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F005_S003_I001 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Verify the saturation mechnism is optimal. Modify the saturation + mechanism by removing/adding one stage, and check the Coremark performance + evolution + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 004_Table depth: !Subfeature + name: 004_Table depth + tag: VP_IP005_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S004_I000 + description: The information is stored in a 1024 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BHT entry number is 1024 + by monitoring the Coremark performance and silicon footprint, the configuration + without BHT is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 005_Debug is not intrusive: !Subfeature + name: 005_Debug is not intrusive + tag: VP_IP005_P005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S005_I000 + description: The BHT is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck deleted file mode 100644 index 2fdde8008..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VRAS -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F006_S000_I000 -p34 -sVdescription -p35 -VThe RAS is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/RAS -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP006_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F006_S001_I000 -p74 -sg35 -VThe RAS FIFO depth is 2. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p76 -sg39 -VConfirm that the best configuration for RAS entry number is 2 by monitoring the Coremark performance and silicon footprint, the configuration without RAS is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP006_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F006_S002_I000 -p99 -sg35 -VWhen an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p101 -sg39 -VWhen a JAL instruction is executed, check that info is stored in RAS -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_Debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP006_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F006_S003_I000 -p124 -sg35 -VNo dedicated specification -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml new file mode 100644 index 000000000..76b06d498 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: RAS +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S000_I000 + description: The RAS is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP006_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S001_I000 + description: The RAS FIFO depth is 2. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for RAS entry number is 2 + by monitoring the Coremark performance and silicon footprint, the configuration + without RAS is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP006_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S002_I000 + description: When an unconditional jumps to a known target address (JAL instruction) + is consummed by the instr_queue, the next pc after the JAL instruction and + the return address are stored into a FIFO. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a JAL instruction is executed, check that info is stored + in RAS + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_Debug is not intrusive: !Subfeature + name: 003_Debug is not intrusive + tag: VP_IP006_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S003_I000 + description: No dedicated specification + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck deleted file mode 100644 index 92ea00422..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck +++ /dev/null @@ -1,232 +0,0 @@ -(VInstr_realign -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C extension -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F007_S000_I000 -p34 -sVdescription -p35 -VThe 32-bit aligned block coming from the CACHE sub-system enters the instr_realign module. This module extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign module provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign module before being provided in the next cycles. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p38 -sVverif_goals -p39 -VExecute program compiled with C extension. Cover the case when 2 instructions are fetched in the same cache block and when an instruction is interleaved with two cache block\u000a\u000a[NO NEED TO VERIFY THIS CASE] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Flush -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP007_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F007_S001_I000 -p74 -sg35 -VIn case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p76 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -asVrfu_list_0 -p87 -(lp88 -sg57 -(lp89 -sVvptool_gitrev -p90 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p91 -sVio_fmt_gitrev -p92 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p93 -sVconfig_gitrev -p94 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p95 -sVymlcfg_gitrev -p96 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p97 -sbtp98 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml new file mode 100644 index 000000000..365f818e3 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml @@ -0,0 +1,66 @@ +!Feature +next_elt_id: 2 +name: Instr_realign +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_C extension: !Subfeature + name: 000_C extension + tag: VP_IP007_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S000_I000 + description: The 32-bit aligned block coming from the CACHE sub-system enters + the instr_realign module. This module extracts the instructions from the + 32-bit blocks, up to two instructions because it is possible to fetch two + instructions when C extension is used. If the instructions are not compressed, + it is possible that the instruction is not aligned on the block size but + rather interleaved with two cache blocks. In that case, two cache accesses + are needed. The instr_realign module provides at maximum one instruction + per cycle. Not complete instruction is stored in instr_realign module before + being provided in the next cycles. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Execute program compiled with C extension. Cover the case when\ + \ 2 instructions are fetched in the same cache block and when an instruction\ + \ is interleaved with two cache block\n\n[NO NEED TO VERIFY THIS CASE]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_Flush: !Subfeature + name: 001_Flush + tag: VP_IP007_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S001_I000 + description: In case of mispredict, flush, replay or branch predict, the instr_realign + is re-initialized, the internal register storing the instruction alignment + state is reset. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck deleted file mode 100644 index dc4ea8eef..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck +++ /dev/null @@ -1,308 +0,0 @@ -(VInstr_queue -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FIFO depth -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F008_S000_I000 -p34 -sVdescription -p35 -VThe instruction queue contains max 4 instructions. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p38 -sVverif_goals -p39 -VConfirm that the best configuration for instruction queue entry number is 4 by monitoring the Coremark performance and silicon footprint -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I11 -sVtest_type -p44 -I10 -sVcov_method -p45 -I10 -sVcores -p46 -I8 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Page fault exception -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP008_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F008_S001_I000 -p74 -sg35 -VIn instruction queue, exception can only correspond to page-fault exception. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p76 -sg39 -VExecute following exception and check that only page-fault can be stored in instruction queue: bus errors, invalid accesses or instruction page faults. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Flush -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP008_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F008_S002_I000 -p99 -sg35 -VThe instruction queue can be flushed by CONTROLLER. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p101 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -asVrfu_list_0 -p112 -(lp113 -sg57 -(lp114 -sVvptool_gitrev -p115 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p116 -sVio_fmt_gitrev -p117 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p118 -sVconfig_gitrev -p119 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p120 -sVymlcfg_gitrev -p121 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p122 -sbtp123 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml new file mode 100644 index 000000000..0559c2d9d --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml @@ -0,0 +1,80 @@ +!Feature +next_elt_id: 3 +name: Instr_queue +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_FIFO depth: !Subfeature + name: 000_FIFO depth + tag: VP_IP008_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S000_I000 + description: The instruction queue contains max 4 instructions. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for instruction queue entry + number is 4 by monitoring the Coremark performance and silicon footprint + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +- 001_Page fault exception: !Subfeature + name: 001_Page fault exception + tag: VP_IP008_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S001_I000 + description: In instruction queue, exception can only correspond to page-fault + exception. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute following exception and check that only page-fault can + be stored in instruction queue: bus errors, invalid accesses or instruction + page faults.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Flush: !Subfeature + name: 002_Flush + tag: VP_IP008_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S002_I000 + description: The instruction queue can be flushed by CONTROLLER. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck deleted file mode 100644 index ac1287a8b..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck +++ /dev/null @@ -1,59 +0,0 @@ -(VInstr_scan -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I0 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -sVrfu_list_0 -p17 -(lp18 -sVrfu_list_1 -p19 -(lp20 -sVvptool_gitrev -p21 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p22 -sVio_fmt_gitrev -p23 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p24 -sVconfig_gitrev -p25 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p26 -sVymlcfg_gitrev -p27 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p28 -sbtp29 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml new file mode 100644 index 000000000..6ec7a33b7 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml @@ -0,0 +1,10 @@ +!Feature +next_elt_id: 0 +name: Instr_scan +id: 9 +display_order: 9 +subfeatures: !!omap [] +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck deleted file mode 100644 index db23b5ab5..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck +++ /dev/null @@ -1,376 +0,0 @@ -(VFetch stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_MMU translation -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP010_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F010_S001_I000 -p34 -sVdescription -p35 -VThe Fetch stage asks the MMU to translate the requested address. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/Fetch stage -p38 -sVverif_goals -p39 -VExecute a program with virtual PC -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F010_S001_I001 -p62 -sg35 -VThe Fetch stage asks the MMU to translate the requested address. -p63 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p64 -sg39 -VCheck the translation does not impact execution time by executing Coremark in pphysical and virtual modes. -p65 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V002_Exceptions -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I4 -sg8 -g76 -sg23 -VVP_IP010_P002 -p80 -sg25 -(dp81 -sg12 -I2 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_FRONTEND_F010_S002_I000 -p88 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p89 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p90 -sg39 -VGenerate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs. -p91 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V002 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V002 -p101 -sg23 -VVP_FRONTEND_F010_S002_I002 -p102 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p103 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p104 -sg39 -VGenerate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs. -p105 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V003 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V003 -p115 -sg23 -VVP_FRONTEND_F010_S002_I003 -p116 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p117 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p118 -sg39 -VGenerate an instruction page faults and check that the exception is triggered -p119 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg71 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -asVrfu_list_0 -p129 -(lp130 -sg71 -(lp131 -sVvptool_gitrev -p132 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p133 -sVio_fmt_gitrev -p134 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p135 -sVconfig_gitrev -p136 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p137 -sVymlcfg_gitrev -p138 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p139 -sbtp140 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml new file mode 100644 index 000000000..fe95149ac --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml @@ -0,0 +1,114 @@ +!Feature +next_elt_id: 3 +name: Fetch stage +id: 10 +display_order: 10 +subfeatures: !!omap +- 001_MMU translation: !Subfeature + name: 001_MMU translation + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S001_I000 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a program with virtual PC + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F010_S001_I001 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Check the translation does not impact execution time by executing + Coremark in pphysical and virtual modes. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Exceptions: !Subfeature + name: 002_Exceptions + tag: VP_IP010_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S002_I000 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate a bus error exception by UVM or by test (to be decided) + and check that the exception address is fetched. Functional cov: a bus error + exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F010_S002_I002 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate an invalid access exception by UVM or by test (to be + decided) and check that the exception address is fetched. Functional cov: + an invalid access exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FRONTEND_F010_S002_I003 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Generate an instruction page faults and check that the exception + is triggered + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/runme.sh b/cva6/docs/VerifPlans/FRONTEND/runme.sh index 3a79359e9..b808624f8 100644 --- a/cva6/docs/VerifPlans/FRONTEND/runme.sh +++ b/cva6/docs/VerifPlans/FRONTEND/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst b/cva6/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst new file mode 100644 index 000000000..7d3eca777 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst @@ -0,0 +1,1365 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales DIS design services SAS + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions: + +RISC-V Instructions +=================== + +Introduction +------------------ + +In this document, we present ISA (Instruction Set Architecture) for C32VA6_v5.0.0, illustrating different supported instructions, the Base Integer Instruction set RV32I, and also other instructions in some extensions supported by the core as: + +* RV32M – Standard Extension for Integer Multiplication and Division Instructions +* RV32A – Standard Extension for Atomic Instructions +* RV32C – Standard Extension for Compressed Instructions +* RV32Zicsr – Standard Extension for CSR Instructions +* RV32Zifencei – Standard Extension for Instruction-Fetch Fence + +The base RISC-V ISA has fixed-length 32-bit instructions or 16-bit instructions (the C32VA6_v5.0.0 support C extension), so that must be naturally aligned on 4-byte boundary or 2-byte boundary. +The C32VA6_v5.0.0 supports: + +* Only 1 hart, +* No misaligned memory accesses. + +General purpose registers +-------------------------- + +As shown in the Table 1.1, there are 31 general-purpose registers x1–x31, which hold integer values. Register x0 is hardwired to the constant 0. There is no hardwired subroutine return address link register, but the standard software calling convention uses register x1 to hold the return address on a call. For C32VA6_v5.0.0, the x registers are 32 bits wide. There is one additional register also 32 bits wide: the program counter pc holds the address of the current instruction. + +Table 1.1 shows the general-purpose registers : + +.. list-table:: + :widths: 20 20 15 15 20 + :header-rows: 1 + + * - **5-bit Encoding (rx)** + - **3-bit Compressed Encoding (rx')** + - **Register (ISA name)** + - **Register (ABI name)** + - **Description** + * - 0 + - + - x0 + - zero + - Hardwired zero + * - 1 + - + - x1 + - ra + - Return address (link register) + * - 2 + - + - x2 + - sp + - Stack pointer + * - 3 + - + - x3 + - gp + - Global pointer + * - 4 + - + - x4 + - tp + - Thread pointer + * - 5 + - + - x5 + - t0 + - Temporaries/alternate link register + * - 6 - 7 + - + - x6 - x7 + - t1 - t2 + - Temporaries + * - 8 + - 0 + - x8 + - s0/fp + - Saved register/frame pointer + * - 9 + - 1 + - x9 + - s1 + - Saved registers + * - 10 - 11 + - 2 - 3 + - x10 - x11 + - a0 - a1 + - Function arguments/return value + * - 12 - 15 + - 4 - 7 + - x12 - x15 + - a2 - a5 + - Function arguments + * - 16 - 17 + - + - x16 - x17 + - a6 - a7 + - Function arguments + * - 18 - 27 + - + - x18 - x27 + - s2 - s11 + - Saved registers + * - 28 - 31 + - + - x28 - x31 + - t3 - t6 + - Temporaries + +Conventions and Terminology +----------------------------- + +- **sext(val)**: Sign Extension is the operation of increasing the number of bits of a binary number while preserving the number's sign (positive(0)/negative(1)) and value. this is done by appending digits to the most significant side of the number. + +- **zext(val)**: Zero Extension is the operation of increasing the number of bits of a binary number with zeros. this is done by appending digits to the most significant side of the number. + +- **>s**: Right shift of 2 signed values. + +- **>>u**: Right shift of 2 unsigned values. + +- **M[address]**: Value existe in the address of the memory. + +- **/s**: Division of 2 signed values. + +- **/u**: Division of 2 unsigned values. + +- **%s**: Remainder of the Division of 2 signed values. + +- **%u**: Remainder of the Division of 2 unsigned values. + +- **AMO32**: Atomic Memory Operation (word). + +- **rx'**: rd', rs1' or rs2', stand for the 3-bit Compressed Encoding registers. + +RV32I Base Integer Instruction Set +----------------------------------- + +This section describes the RV32I base integer instruction set. + +Integer Register-Immediate Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ADDI**: Add Immediate + + **Format**: addi rd, rs1, imm[11:0] + + **Description**: add sign-extended 12-bit immediate to register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] + sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **ANDI**: AND Immediate + + **Format**: andi rd, rs1, imm[11:0] + + **Description**: perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] & sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **ORI**: OR Immediate + + **Format**: ori rd, rs1, imm[11:0] + + **Description**: perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] | sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **XORI**: XOR Immediate + + **Format**: xori rd, rs1, imm[11:0] + + **Description**: perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] ^ sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTI**: Set Less Then Immediate + + **Format**: slti rd, rs1, imm[11:0] + + **Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] < sext(imm[11:0]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTIU**: Set Less Then Immediate Unsigned + + **Format**: sltiu rd, rs1, imm[11:0] + + **Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] > imm[4:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRAI**: Shift Right Arithmetic Immediate + + **Format**: srai rd, rs1, imm[4:0] + + **Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits). + + **Pseudocode**: x[rd] = x[rs1] >>s imm[4:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **LUI**: Load Upper Immediate + + **Format**: lui rd, imm[19:0] + + **Description**: place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. + + **Pseudocode**: x[rd] = sext(imm[31:12] << 12) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AUIPC**: Add Upper Immediate to PC + + **Format**: auipc rd, imm[19:0] + + **Description**: form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd. + + **Pseudocode**: x[rd] = pc + sext(immediate[31:12] << 12) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Integer Register-Register Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ADD**: Addition + + **Format**: add rd, rs1, rs2 + + **Description**: add rs2 to register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SUB**: Subtraction + + **Format**: sub rd, rs1, rs2 + + **Description**: subtract rs2 from register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] - x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AND**: AND logical operator + + **Format**: and rd, rs1, rs2 + + **Description**: perform bitwise AND on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] & x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **OR**: OR logical operator + + **Format**: or rd, rs1, rs2 + + **Description**: perform bitwise OR on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] | x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **XOR**: XOR logical operator + + **Format**: xor rd, rs1, rs2 + + **Description**: perform bitwise XOR on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] ^ x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLT**: Set Less Then + + **Format**: slt rd, rs1, rs2 + + **Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTU**: Set Less Then Unsigned + + **Format**: sltu rd, rs1, rs2 + + **Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] > x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRA**: Shift Right Arithmetic + + **Format**: sra rd, rs1, rs2 + + **Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits). + + **Pseudocode**: x[rd] = x[rs1] >>s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +Control Transfer Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Unconditional Jumps** + +- **JAL**: Jump and Link + + **Format**: jal rd, imm[20:1] + + **Description**: offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. + + **Pseudocode**: x[rd] = pc+4; pc += sext(imm[20:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **JALR**: Jump and Link Register + + **Format**: jalr rd, rs1, imm[11:0] + + **Description**: target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. + + **Pseudocode**: t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +**Conditional Branches** + +- **BEQ**: Branch Equal + + **Format**: beq rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal. + + **Invalid values**: NONE + + **Pseudocode**: if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BNE**: Branch Not Equal + + **Format**: bne rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal. + + **Invalid values**: NONE + + **Pseudocode**: if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BLT**: Branch Less Than + + **Format**: blt rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison). + + **Invalid values**: NONE + + **Pseudocode**: if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BLTU**: Branch Less Than Unsigned + + **Format**: bltu rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison). + + **Invalid values**: NONE + + **Pseudocode**: if (x[rs1] = x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BGEU**: Branch Greater or Equal Unsigned + + **Format**: bgeu rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison). + + **Invalid values**: NONE + + **Pseudocode**: if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +Load and Store Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **LB**: Load Byte + + **Format**: lb rd, imm(rs1) + + **Description**: loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. + +- **LH**: Load Halfword + + **Format**: lh rd, imm(rs1) + + **Description**: loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **LW**: Load Word + + **Format**: lw rd, imm(rs1) + + **Description**: loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Invalid values**: NONE + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0]) + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary). + +- **LBU**: Load Byte Unsigned + + **Format**: lbu rd, imm(rs1) + + **Description**: loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. + +- **LHU**: Load Halfword Unsigned + + **Format**: lhu rd, imm(rs1) + + **Description**: loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **SB**: Store Byte + + **Format**: sb rs2, imm(rs1) + + **Description**: stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SH**: Store Halfword + + **Format**: sh rs2, imm(rs1) + + **Description**: stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0] + + **Invalid values**: NONE + + **Exception raised**: an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **SW**: Store Word + + **Format**: sw rs2, imm(rs1) + + **Description**: stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0] + + **Invalid values**: NONE + + **Exception raised**: an exception is raised if the memory address isn't aligned (4-byte boundary). + +Memory Ordering +^^^^^^^^^^^^^^^^^^ + +- **FENCE**: Fence Instruction + + **Format**: fence pre, succ + + **Description**: order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction. + + **Pseudocode**: No operation (nop) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Environment Call and Breakpoints +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ECALL**: Environment Call + + **Format**: ecall + + **Description**: make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file. + + **Pseudocode**: RaiseException(EnvironmentCall) + + **Invalid values**: NONE + + **Exception raised**: Raise an Environment Call exception. + +- **EBREAK**:Environment Break + + **Format**: ebreak + + **Description**: cause control to be transferred back to a debugging environment. + + **Pseudocode**: RaiseException(Breakpoint) + + **Invalid values**: NONE + + **Exception raised**: Raise a Breakpoint exception. + +RV32M Multiplication and Division Instructions +------------------------------------------------------ + +This chapter describes the standard integer multiplication and division instruction extension, which +is named “M” and contains instructions that multiply or divide values held in two integer registers. + +Multiplication Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **MUL**: Multiplication + + **Format**: mul rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers). + + **Pseudocode**: x[rd] = x[rs1] * x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULH**: Multiplication Higher + + **Format**: mulh rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers). + + **Pseudocode**: x[rd] = (x[rs1] s*s x[rs2]) >>s 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULHU**: Multiplication Higher Unsigned + + **Format**: mulhu rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers). + + **Pseudocode**: x[rd] = (x[rs1] u*u x[rs2]) >>u 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULHSU**: Multiplication Higher Signed Unsigned + + **Format**: mulhsu rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number). + + **Pseudocode**: x[rd] = (x[rs1] s*u x[rs2]) >>s 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +Division Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **DIV**: Division + + **Format**: div rd, rs1, rs2 + + **Description**: perform signed integer division of 32 bits by 32 bits (rounding towards zero). + + **Pseudocode**: x[rd] = x[rs1] /s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **DIVU**: Division Unsigned + + **Format**: divu rd, rs1, rs2 + + **Description**: perform unsigned integer division of 32 bits by 32 bits (rounding towards zero). + + **Pseudocode**: x[rd] = x[rs1] /u x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **REM**: Remain + + **Format**: rem rd, rs1, rs2 + + **Description**: provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1). + + **Pseudocode**: x[rd] = x[rs1] %s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **REMU**: Remain Unsigned + + **Format**: rem rd, rs1, rs2 + + **Description**: provide the remainder of the corresponding division operation DIVU. + + **Pseudocode**: x[rd] = x[rs1] %u x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + + +RV32A Atomic Instructions +-------------------------------- + +The standard atomic instruction extension is denoted by instruction subset name “A”, and contains instructions that atomically read-modify-write memory to support synchronization between +multiple RISC-V harts running in the same memory space. The two forms of atomic instruction +provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings including +unordered, acquire, release, and sequentially consistent semantics. + +Load-Reserved/Store-Conditional Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **LR.W**: Load-Reserved Word + + **Format**: lr.w rd, (rs1) + + **Description**: LR loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation on the memory address. + + **Pseudocode**: x[rd] = LoadReserved32(M[x[rs1]]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a Load/AMO address misaligned exception will be generated. + +- **SC.W**: Store-Conditional Word + + **Format**: sc.w rd, rs2, (rs1) + + **Description**: SC writes a word in rs2 to the address in rs1, provided a valid reservation still exists on that address. SC writes zero to rd on success or a nonzero code on failure. + + **Pseudocode**: x[rd] = StoreConditional32(M[x[rs1]], x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a Store/AMO address misaligned exception will be generated. + +Atomic Memory Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **AMOADD.W**: Atomic Memory Operation: Add Word + + **Format**: amoadd.w rd, rs2, (rs1) + + **Description**: AMOADD.W atomically loads a data value from the address in rs1, places the value into register rd, then adds the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] + x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOAND.W**: Atomic Memory Operation: And Word + + **Format**: amoand.w rd, rs2, (rs1) + + **Description**: AMOAND.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an AND between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] & x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOOR.W**: Atomic Memory Operation: Or Word + + **Format**: amoor.w rd, rs2, (rs1) + + **Description**: AMOOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an OR between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] | x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOXOR.W**: Atomic Memory Operation: Xor Word + + **Format**: amoxor.w rd, rs2, (rs1) + + **Description**: AMOXOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a XOR between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] ^ x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOSWAP.W**: Atomic Memory Operation: Swap Word + + **Format**: amoswap.w rd, rs2, (rs1) + + **Description**: AMOSWAP.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a SWAP between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] SWAP x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMIN.W**: Atomic Memory Operation: Minimum Word + + **Format**: amomin.d rd, rs2, (rs1) + + **Description**: AMOMIN.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MIN x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMINU.W**: Atomic Memory Operation: Minimum Word, Unsigned + + **Format**: amominu.d rd, rs2, (rs1) + + **Description**: AMOMINU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MINU x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMAX.W**: Atomic Memory Operation: Maximum Word, Unsigned + + **Format**: amomax.d rd, rs2, (rs1) + + **Description**: AMOMAX.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAX x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMAXU.W**: Atomic Memory Operation: Maximum Word, Unsigned + + **Format**: amomaxu.d rd, rs2, (rs1) + + **Description**: AMOMAXU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAXU x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +RV32C Compressed Instructions +-------------------------------- + +RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V +instructions when: + + • the immediate or address offset is small; + • one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); + • the destination register and the first source register are identical; + • the registers used are the 8 most popular ones. + +The C extension is compatible with all other standard instruction extensions. The C extension +allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able +to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions +will no longer raise an instruction misaligned exception. + +Integer Computational Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.LI**: Compressed Load Immediate + + **Format**: c.li rd, imm[5:0] + + **Description**: loads the sign-extended 6-bit immediate, imm, into register rd. + + **Pseudocode**: x[rd] = sext(imm[5:0]) + + **Invalid values**: rd = x0 + + **Exception raised**: NONE + +- **C.LUI**: Compressed Load Upper Immediate + + **Format**: c.lui rd, nzimm[17:12] + + **Description**: loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. + + **Pseudocode**: x[rd] = sext(nzimm[17:12] << 12) + + **Invalid values**: rd = x0 & rd = x2 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI**: Compressed Addition Immediate + + **Format**: c.addi rd, nzimm[5:0] + + **Description**: adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. + + **Pseudocode**: x[rd] = x[rd] + sext(nzimm[5:0]) + + **Invalid values**: rd = x0 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI16SP**: Addition Immediate Scaled by 16, to Stack Pointer + + **Format**: c.addi16sp nzimm[9:4] + + **Description**: adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2. + + **Pseudocode**: x[2] = x[2] + sext(nzimm[9:4]) + + **Invalid values**: rd != x2 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI4SPN**: Addition Immediate Scaled by 4, to Stack Pointer + + **Format**: c.addi4spn nzimm[9:2] + + **Description**: adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. + + **Pseudocode**: x[8 + rd'] = x[2] + zext(nzimm[9:2]) + + **Invalid values**: nzimm = 0 + + **Exception raised**: NONE + +- **C.SLLI**: Compressed Shift Left Logic Immediate + + **Format**: c.slli rd, uimm[5:0] + + **Description**: performs a logical left shift (zeros are shifted into the lower bits). + + **Pseudocode**: x[rd] = x[rd] << uimm[5:0] + + **Invalid values**: rd = x0 & uimm[5] = 0 + + **Exception raised**: NONE + +- **C.SRLI**: Compressed Shift Right Logic Immediate + + **Format**: c.srli rd', uimm[5:0] + + **Description**: performs a logical right shift (zeros are shifted into the upper bits). + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] >> uimm[5:0] + + **Invalid values**: uimm[5] = 0 + + **Exception raised**: NONE + +- **C.SRAI**: Compressed Shift Right Arithmetic Immediate + + **Format**: c.srai rd', uimm[5:0] + + **Description**: performs an arithmetic right shift (sign bits are shifted into the upper bits). + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] >>s uimm[5:0] + + **Invalid values**: uimm[5] = 0 + + **Exception raised**: NONE + +- **C.ANDI**: Compressed AND Immediate + + **Format**: c.andi rd', imm[5:0] + + **Description**: computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] & sext(imm[5:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.ADD**: Compressed Addition + + **Format**: c.add rd, rs2 + + **Description**: adds the values in registers rd and rs2 and writes the result to register rd. + + **Pseudocode**: x[rd] = x[rd] + x[rs2] + + **Invalid values**: rd = x0 & rs2 = x0 + + **Exception raised**: NONE + +- **C.MV**: Move + + **Format**: c.mv rd, rs2 + + **Description**: copies the value in register rs2 into register rd. + + **Pseudocode**: x[rd] = x[rs2] + + **Invalid values**: rd = x0 & rs2 = x0 + + **Exception raised**: NONE + +- **C.AND**: Compressed AND + + **Format**: c.and rd', rs2' + + **Description**: computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] & x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.OR**: Compressed OR + + **Format**: c.or rd', rs2' + + **Description**: computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] | x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.XOR**: Compressed XOR + + **Format**: c.and rd', rs2' + + **Description**: computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.SUB**: Compressed Subtraction + + **Format**: c.sub rd', rs2' + + **Description**: subtracts the value in registers rs2' from value in rd' and writes the result to register rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] - x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.EBREAK**: Compressed Ebreak + + **Format**: c.ebreak + + **Description**: cause control to be transferred back to the debugging environment. + + **Pseudocode**: RaiseException(Breakpoint) + + **Invalid values**: NONE + + **Exception raised**: Raise a Breakpoint exception. + +Control Transfer Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.J**: Compressed Jump + + **Format**: c.j imm[11:1] + + **Description**: performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. + + **Pseudocode**: pc += sext(imm[11:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JAL**: Compressed Jump and Link + + **Format**: c.jal imm[11:1] + + **Description**: performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + + **Pseudocode**: x[1] = pc+2; pc += sext(imm[11:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JR**: Compressed Jump Register + + **Format**: c.jr rs1 + + **Description**: performs an unconditional control transfer to the address in register rs1. + + **Pseudocode**: pc = x[rs1] + + **Invalid values**: rs1 = x0 + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JALR**: Compressed Jump and Link Register + + **Format**: c.jalr rs1 + + **Description**: performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + + **Pseudocode**: t = pc+2; pc = x[rs1]; x[1] = t + + **Invalid values**: rs1 = x0 + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.BEQZ**: Branch if Equal Zero + + **Format**: c.beqz rs1', imm[8:1] + + **Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero. + + **Pseudocode**: if (x[8+rs1'] == 0) pc += sext(imm[8:1]) + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **C.BNEZ**: Branch if Not Equal Zero + + **Format**: c.bnez rs1', imm[8:1] + + **Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero. + + **Pseudocode**: if (x[8+rs1'] != 0) pc += sext(imm[8:1]) + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +Load and Store Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.LWSP**: Load Word Stack-Pointer + + **Format**: c.lwsp rd, uimm(x2) + + **Description**: loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. + + **Pseudocode**: x[rd] = M[x[2] + zext(uimm[7:2])][31:0] + + **Invalid values**: rd = x0 + + **Exception raised**: loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary). + +- **C.SWSP**: Store Word Stack-Pointer + + **Format**: c.swsp rd, uimm(x2) + + **Description**: stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. + + **Pseudocode**: M[x[2] + zext(uimm[7:2])][31:0] = x[rs2] + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +- **C.LW**: Compressed Load Word + + **Format**: c.lw rd', uimm(rs1') + + **Description**: loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. + + **Pseudocode**: x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0]) + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +- **C.SW**: Compressed Store Word + + **Format**: c.sw rs2', uimm(rs1') + + **Description**: stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. + + **Pseudocode**: M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2'] + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +RV32Zicsr Control and Status Register Instructions +--------------------------------------------------- + +All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. + +- **CSRRW**: Control and Status Register Read and Write + + **Format**: csrrw rd, csr, rs1 + + **Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd, the initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRS**: Control and Status Register Read and Set + + **Format**: csrrs rd, csr, rs1 + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRC**: Control and Status Register Read and Clear + + **Format**: csrrc rd, csr, rs1 + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRWI**: Control and Status Register Read and Write Immediate + + **Format**: csrrwi rd, csr, uimm[4:0] + + **Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. + + **Pseudocode**: x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0]) + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRSI**: Control and Status Register Read and Set Immediate + + **Format**: csrrsi rd, csr, uimm[4:0] + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | zext(uimm[4:0]); x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRCI**: Control and Status Register Read and Clear Immediate + + **Format**: csrrci rd, csr, uimm[4:0] + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +RV32Zifencei Instruction-Fetch Fence +-------------------------------------- + +- **FENCE.I**: Fence Instruction + + **Format**: fence.i + + **Description**: The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. + + **Pseudocode**: Fence(Store, Fetch) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Illegal Instruction +--------------------------- + +This section describe all kind of Illegal Instruction, in this case the Core generate an illegal instruction exception. + +- **ILLEGAL OPCODE**: any instruction (compressed or not compressed) with a non supported opcode is an illegal instruction + +- **ILLEGAL FUNCT2**: any instruction (R4type) with a non supported FUNCT2 is an illegal instruction + +- **ILLEGAL FUNCT3**: any instruction (Rtype, R4type, Itype, Stype or Atype) with a non supported FUNCT3 is an illegal instruction + +- **ILLEGAL FUNCT5**: any instruction (Atype) with a non supported FUNCT5 is an illegal instruction + +- **ILLEGAL FUNCT7**: any instruction (Rtype) with a non supported FUNCT7 is an illegal instruction + +- **ILLEGAL CSR**: any CSR instruction attempts to access a non-existent is an illegal instruction + +- **ILLEGAL PRIVILEGE LEVEL**: any CSR instruction attempts to access a CSR without appropriate privilege level is an illegal instruction + +- **ILLEGAL ACCESS TYPE CSR**: any CSR instruction attempts to write a read-only CSR a non-existent is an illegal instruction diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck deleted file mode 100644 index 01fe8aacb..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck +++ /dev/null @@ -1,1999 +0,0 @@ -(VRV32I Register-Immediate Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I11 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I0 -sVwid_order -p12 -I0 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADDI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP011_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F011_S000_I000 -p34 -sVdescription -p35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_addi_cg.cp_rs1\u000aisacov.rv32i_addi_cg.cp_rd\u000aisacov.rv32i_addi_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F011_S000_I001 -p63 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p64 -sg37 -VISA\u000aChapter 2.4 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_addi_cg.cp_rs1_value\u000aisacov.rv32i_addi_cg.cp_immi_value\u000aisacov.rv32i_addi_cg.cross_rs1_immi_value\u000aisacov.rv32i_addi_cg.cp_rs1_toggle\u000aisacov.rv32i_addi_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F011_S000_I002 -p78 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p79 -sg37 -VISA\u000aChapter 2.4 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_addi_cg.cp_rd_value\u000aisacov.rv32i_addi_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_XORI -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I5 -sg8 -g93 -sg23 -VVP_IP011_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F011_S001_I000 -p105 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p106 -sg37 -VISA\u000aChapter 2.4 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_xori_cg.cp_rs1\u000aisacov.rv32i_xori_cg.cp_rd\u000aisacov.rv32i_xori_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -g115 -sg23 -VVP_ISA_F011_S001_I001 -p119 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p120 -sg37 -VISA\u000aChapter 2.4 -p121 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p122 -sg41 -Visacov.rv32i_xori_cg.cp_rs1_value\u000aisacov.rv32i_xori_cg.cp_immi_value\u000aisacov.rv32i_xori_cg.cross_rs1_immi_value\u000aisacov.rv32i_xori_cg.cp_rs1_toggle\u000aisacov.rv32i_xori_cg.cp_immi_toggle -p123 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp124 -sg15 -(lp125 -sg53 -(lp126 -sg13 -(dp127 -g56 -I0 -ssbtp128 -a(V002 -p129 -g1 -(g29 -g3 -Ntp130 -Rp131 -(dp132 -g8 -g129 -sg23 -VVP_ISA_F011_S001_I002 -p133 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_xori_cg.cp_rd_value\u000aisacov.rv32i_xori_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg88 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_ORI -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I4 -sg8 -g147 -sg23 -VVP_IP011_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F011_S002_I000 -p159 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p162 -sg41 -Visacov.rv32i_ori_cg.cp_rs1\u000aisacov.rv32i_ori_cg.cp_rd\u000aisacov.rv32i_ori_cg.cp_rd_rs1_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -g169 -sg23 -VVP_ISA_F011_S002_I001 -p173 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p174 -sg37 -VISA\u000aChapter 2.4 -p175 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p176 -sg41 -Visacov.rv32i_ori_cg.cp_rs1_value\u000aisacov.rv32i_ori_cg.cp_immi_value\u000aisacov.rv32i_ori_cg.cross_rs1_immi_value\u000aisacov.rv32i_ori_cg.cp_rs1_toggle\u000aisacov.rv32i_ori_cg.cp_immi_toggle -p177 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp178 -sg15 -(lp179 -sg53 -(lp180 -sg13 -(dp181 -g56 -I0 -ssbtp182 -a(V002 -p183 -g1 -(g29 -g3 -Ntp184 -Rp185 -(dp186 -g8 -g183 -sg23 -VVP_ISA_F011_S002_I002 -p187 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p188 -sg37 -VISA\u000aChapter 2.4 -p189 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p190 -sg41 -Visacov.rv32i_ori_cg.cp_rd_value\u000aisacov.rv32i_ori_cg.cp_rd_toggle -p191 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp192 -sg15 -(lp193 -sg53 -(lp194 -sg13 -(dp195 -g56 -I0 -ssbtp196 -asg88 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -sbtp200 -a(V003_ANDI -p201 -g1 -(g18 -g3 -Ntp202 -Rp203 -(dp204 -g22 -I3 -sg8 -g201 -sg23 -VVP_IP011_P003 -p205 -sg25 -(dp206 -sg12 -I3 -sg15 -(lp207 -(V000 -p208 -g1 -(g29 -g3 -Ntp209 -Rp210 -(dp211 -g8 -V000 -p212 -sg23 -VVP_ISA_F011_S003_I000 -p213 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p214 -sg37 -VISA\u000aChapter 2.4 -p215 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p216 -sg41 -Visacov.rv32i_andi_cg.cp_rs1\u000aisacov.rv32i_andi_cg.cp_rd\u000aisacov.rv32i_andi_cg.cp_rd_rs1_hazard -p217 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp218 -sg15 -(lp219 -sg53 -(lp220 -sg13 -(dp221 -g56 -I0 -ssbtp222 -a(V001 -p223 -g1 -(g29 -g3 -Ntp224 -Rp225 -(dp226 -g8 -V001 -p227 -sg23 -VVP_ISA_F011_S003_I001 -p228 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p229 -sg37 -VISA\u000aChapter 2.4 -p230 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p231 -sg41 -Visacov.rv32i_andi_cg.cp_rs1_value\u000aisacov.rv32i_andi_cg.cp_immi_value\u000aisacov.rv32i_andi_cg.cross_rs1_immi_value\u000aisacov.rv32i_andi_cg.cp_rs1_toggle\u000aisacov.rv32i_andi_cg.cp_immi_toggle -p232 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp233 -sg15 -(lp234 -sg53 -(lp235 -sg13 -(dp236 -g56 -I0 -ssbtp237 -a(V002 -p238 -g1 -(g29 -g3 -Ntp239 -Rp240 -(dp241 -g8 -V002 -p242 -sg23 -VVP_ISA_F011_S003_I002 -p243 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p244 -sg37 -VISA\u000aChapter 2.4 -p245 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p246 -sg41 -Visacov.rv32i_andi_cg.cp_rd_value\u000aisacov.rv32i_andi_cg.cp_rd_toggle -p247 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp248 -sg15 -(lp249 -sg53 -(lp250 -sg13 -(dp251 -g56 -I0 -ssbtp252 -asg88 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -sbtp256 -a(V004_SLTI -p257 -g1 -(g18 -g3 -Ntp258 -Rp259 -(dp260 -g22 -I3 -sg8 -g257 -sg23 -VVP_IP011_P004 -p261 -sg25 -(dp262 -sg12 -I4 -sg15 -(lp263 -(V000 -p264 -g1 -(g29 -g3 -Ntp265 -Rp266 -(dp267 -g8 -V000 -p268 -sg23 -VVP_ISA_F011_S004_I000 -p269 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p270 -sg37 -VISA\u000aChapter 2.4 -p271 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p272 -sg41 -Visacov.rv32i_slti_cg.cp_rs1\u000aisacov.rv32i_slti_cg.cp_rd\u000aisacov.rv32i_slti_cg.cp_rd_rs1_hazard -p273 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp274 -sg15 -(lp275 -sg53 -(lp276 -sg13 -(dp277 -g56 -I0 -ssbtp278 -a(V001 -p279 -g1 -(g29 -g3 -Ntp280 -Rp281 -(dp282 -g8 -V001 -p283 -sg23 -VVP_ISA_F011_S004_I001 -p284 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p285 -sg37 -VISA\u000aChapter 2.4 -p286 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p287 -sg41 -Visacov.rv32i_slti_cg.cp_rs1_value\u000aisacov.rv32i_slti_cg.cp_immi_value\u000aisacov.rv32i_slti_cg.cross_rs1_immi_value\u000aisacov.rv32i_slti_cg.cp_rs1_toggle\u000aisacov.rv32i_slti_cg.cp_immi_toggle -p288 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp289 -sg15 -(lp290 -sg53 -(lp291 -sg13 -(dp292 -g56 -I0 -ssbtp293 -a(V002 -p294 -g1 -(g29 -g3 -Ntp295 -Rp296 -(dp297 -g8 -V002 -p298 -sg23 -VVP_ISA_F011_S004_I002 -p299 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p300 -sg37 -VISA\u000aChapter 2.4 -p301 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p302 -sg41 -Visacov.rv32i_slti_cg.cp_rd_value -p303 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp304 -sg15 -(lp305 -sg53 -(lp306 -sg13 -(dp307 -g56 -I0 -ssbtp308 -asg88 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -sbtp312 -a(V005_SLTIU -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP011_P005 -p317 -sg25 -(dp318 -sg12 -I5 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F011_S005_I000 -p325 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p326 -sg37 -VISA\u000aChapter 2.4 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p328 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1\u000aisacov.rv32i_sltiu_cg.cp_rd\u000aisacov.rv32i_sltiu_cg.cp_rd_rs1_hazard -p329 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp330 -sg15 -(lp331 -sg53 -(lp332 -sg13 -(dp333 -g56 -I0 -ssbtp334 -a(V001 -p335 -g1 -(g29 -g3 -Ntp336 -Rp337 -(dp338 -g8 -V001 -p339 -sg23 -VVP_ISA_F011_S005_I001 -p340 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p341 -sg37 -VISA\u000aChapter 2.4 -p342 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p343 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1_value\u000aisacov.rv32i_sltiu_cg.cp_immi_value\u000aisacov.rv32i_sltiu_cg.cross_rs1_immi_value\u000aisacov.rv32i_sltiu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltiu_cg.cp_immi_toggle -p344 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp345 -sg15 -(lp346 -sg53 -(lp347 -sg13 -(dp348 -g56 -I0 -ssbtp349 -a(V002 -p350 -g1 -(g29 -g3 -Ntp351 -Rp352 -(dp353 -g8 -V002 -p354 -sg23 -VVP_ISA_F011_S005_I002 -p355 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p356 -sg37 -VISA\u000aChapter 2.4 -p357 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p358 -sg41 -Visacov.rv32i_sltiu_cg.cp_rd_value -p359 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp360 -sg15 -(lp361 -sg53 -(lp362 -sg13 -(dp363 -g56 -I0 -ssbtp364 -asg88 -(lp365 -sg53 -(lp366 -sg13 -(dp367 -sbtp368 -a(V006_SLLI -p369 -g1 -(g18 -g3 -Ntp370 -Rp371 -(dp372 -g22 -I3 -sg8 -g369 -sg23 -VVP_IP011_P006 -p373 -sg25 -(dp374 -sg12 -I6 -sg15 -(lp375 -(V000 -p376 -g1 -(g29 -g3 -Ntp377 -Rp378 -(dp379 -g8 -V000 -p380 -sg23 -VVP_ISA_F011_S006_I000 -p381 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p382 -sg37 -VISA\u000aChapter 2.4 -p383 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p384 -sg41 -Visacov.rv32i_slli_cg.cp_rs1\u000aisacov.rv32i_slli_cg.cp_rd\u000aisacov.rv32i_slli_cg.cp_rd_rs1_hazard -p385 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp386 -sg15 -(lp387 -sg53 -(lp388 -sg13 -(dp389 -g56 -I0 -ssbtp390 -a(V001 -p391 -g1 -(g29 -g3 -Ntp392 -Rp393 -(dp394 -g8 -V001 -p395 -sg23 -VVP_ISA_F011_S006_I001 -p396 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p397 -sg37 -VISA\u000aChapter 2.4 -p398 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p399 -sg41 -Visacov.rv32i_slli_cg.cp_rs1_value\u000aisacov.rv32i_slli_cg.cp_immi_value\u000aisacov.rv32i_slli_cg.cross_rs1_immi_value\u000aisacov.rv32i_slli_cg.cp_rs1_toggle -p400 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp401 -sg15 -(lp402 -sg53 -(lp403 -sg13 -(dp404 -g56 -I0 -ssbtp405 -a(V002 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V002 -p410 -sg23 -VVP_ISA_F011_S006_I002 -p411 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p412 -sg37 -VISA\u000aChapter 2.4 -p413 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p414 -sg41 -Visacov.rv32i_slli_cg.cp_rd_value\u000aisacov.rv32i_slli_cg.cp_rd_toggle -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -asg88 -(lp421 -sg53 -(lp422 -sg13 -(dp423 -sbtp424 -a(V007_SRLI -p425 -g1 -(g18 -g3 -Ntp426 -Rp427 -(dp428 -g22 -I4 -sg8 -g425 -sg23 -VVP_IP011_P007 -p429 -sg25 -(dp430 -sg12 -I7 -sg15 -(lp431 -(V000 -p432 -g1 -(g29 -g3 -Ntp433 -Rp434 -(dp435 -g8 -V000 -p436 -sg23 -VVP_ISA_F011_S007_I000 -p437 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p438 -sg37 -VISA\u000aChapter 2.4 -p439 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p440 -sg41 -Visacov.rv32i_srli_cg.cp_rs1\u000aisacov.rv32i_srli_cg.cp_rd\u000aisacov.rv32i_srli_cg.cp_rd_rs1_hazard -p441 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp442 -sg15 -(lp443 -sg53 -(lp444 -sg13 -(dp445 -g56 -I0 -ssbtp446 -a(V001 -p447 -g1 -(g29 -g3 -Ntp448 -Rp449 -(dp450 -g8 -g447 -sg23 -VVP_ISA_F011_S007_I001 -p451 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p452 -sg37 -VISA\u000aChapter 2.4 -p453 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p454 -sg41 -Visacov.rv32i_srli_cg.cp_rs1_value\u000aisacov.rv32i_srli_cg.cp_immi_value\u000aisacov.rv32i_srli_cg.cross_rs1_immi_value\u000aisacov.rv32i_srli_cg.cp_rs1_toggle -p455 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp456 -sg15 -(lp457 -sg53 -(lp458 -sg13 -(dp459 -g56 -I0 -ssbtp460 -a(V002 -p461 -g1 -(g29 -g3 -Ntp462 -Rp463 -(dp464 -g8 -g461 -sg23 -VVP_ISA_F011_S007_I002 -p465 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p466 -sg37 -VISA\u000aChapter 2.4 -p467 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p468 -sg41 -Visacov.rv32i_srli_cg.cp_rd_value\u000aisacov.rv32i_srli_cg.cp_rd_toggle -p469 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp470 -sg15 -(lp471 -sg53 -(lp472 -sg13 -(dp473 -g56 -I0 -ssbtp474 -asg88 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -sbtp478 -a(V008_SRAI -p479 -g1 -(g18 -g3 -Ntp480 -Rp481 -(dp482 -g22 -I3 -sg8 -g479 -sg23 -VVP_IP011_P008 -p483 -sg25 -(dp484 -sg12 -I8 -sg15 -(lp485 -(V000 -p486 -g1 -(g29 -g3 -Ntp487 -Rp488 -(dp489 -g8 -V000 -p490 -sg23 -VVP_ISA_F011_S008_I000 -p491 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p492 -sg37 -VISA\u000aChapter 2.4 -p493 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p494 -sg41 -Visacov.rv32i_srai_cg.cp_rs1\u000aisacov.rv32i_srai_cg.cp_rd\u000aisacov.rv32i_srai_cg.cp_rd_rs1_hazard -p495 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp496 -sg15 -(lp497 -sg53 -(lp498 -sg13 -(dp499 -g56 -I0 -ssbtp500 -a(V001 -p501 -g1 -(g29 -g3 -Ntp502 -Rp503 -(dp504 -g8 -V001 -p505 -sg23 -VVP_ISA_F011_S008_I001 -p506 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p507 -sg37 -VISA\u000aChapter 2.4 -p508 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p509 -sg41 -Visacov.rv32i_srai_cg.cp_rs1_value\u000aisacov.rv32i_srai_cg.cp_immi_value\u000aisacov.rv32i_srai_cg.cross_rs1_immi_value\u000aisacov.rv32i_srai_cg.cp_rs1_toggle -p510 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp511 -sg15 -(lp512 -sg53 -(lp513 -sg13 -(dp514 -g56 -I0 -ssbtp515 -a(V002 -p516 -g1 -(g29 -g3 -Ntp517 -Rp518 -(dp519 -g8 -V002 -p520 -sg23 -VVP_ISA_F011_S008_I002 -p521 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p522 -sg37 -VISA\u000aChapter 2.4 -p523 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p524 -sg41 -Visacov.rv32i_srai_cg.cp_rd_value\u000aisacov.rv32i_srai_cg.cp_rd_toggle -p525 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp526 -sg15 -(lp527 -sg53 -(lp528 -sg13 -(dp529 -g56 -I0 -ssbtp530 -asg88 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -sbtp534 -a(V009_LUI -p535 -g1 -(g18 -g3 -Ntp536 -Rp537 -(dp538 -g22 -I3 -sg8 -g535 -sg23 -VVP_IP011_P009 -p539 -sg25 -(dp540 -sg12 -I9 -sg15 -(lp541 -(V000 -p542 -g1 -(g29 -g3 -Ntp543 -Rp544 -(dp545 -g8 -V000 -p546 -sg23 -VVP_ISA_F011_S009_I000 -p547 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p548 -sg37 -VISA\u000aChapter 2.4 -p549 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p550 -sg41 -Visacov.rv32i_lui_cg.cp_rd -p551 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp552 -sg15 -(lp553 -sg53 -(lp554 -sg13 -(dp555 -g56 -I0 -ssbtp556 -a(V001 -p557 -g1 -(g29 -g3 -Ntp558 -Rp559 -(dp560 -g8 -V001 -p561 -sg23 -VVP_ISA_F011_S009_I001 -p562 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p563 -sg37 -VISA\u000aChapter 2.4 -p564 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p565 -sg41 -Visacov.rv32i_lui_cg.cp_immu_value\u000aisacov.rv32i_lui_cg.cp_immu_toggle -p566 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp567 -sg15 -(lp568 -sg53 -(lp569 -sg13 -(dp570 -g56 -I0 -ssbtp571 -a(V002 -p572 -g1 -(g29 -g3 -Ntp573 -Rp574 -(dp575 -g8 -V002 -p576 -sg23 -VVP_ISA_F011_S009_I002 -p577 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p578 -sg37 -VISA\u000aChapter 2.4 -p579 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p580 -sg41 -Visacov.rv32i_lui_cg.cp_rd_value\u000aisacov.rv32i_lui_cg.cp_rd_toggle -p581 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp582 -sg15 -(lp583 -sg53 -(lp584 -sg13 -(dp585 -g56 -I0 -ssbtp586 -asg88 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -sbtp590 -a(V010_AUIPC -p591 -g1 -(g18 -g3 -Ntp592 -Rp593 -(dp594 -g22 -I3 -sg8 -g591 -sg23 -VVP_IP011_P010 -p595 -sg25 -(dp596 -sg12 -I10 -sg15 -(lp597 -(V000 -p598 -g1 -(g29 -g3 -Ntp599 -Rp600 -(dp601 -g8 -V000 -p602 -sg23 -VVP_ISA_F011_S010_I000 -p603 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p604 -sg37 -VISA\u000aChapter 2.4 -p605 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p606 -sg41 -Visacov.rv32i_auipc_cg.cp_rd -p607 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp608 -sg15 -(lp609 -sg53 -(lp610 -sg13 -(dp611 -g56 -I0 -ssbtp612 -a(V001 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V001 -p617 -sg23 -VVP_ISA_F011_S010_I001 -p618 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p619 -sg37 -VISA\u000aChapter 2.4 -p620 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p621 -sg41 -Visacov.rv32i_auipc_cg.cp_immu_value\u000aisacov.rv32i_auipc_cg.cp_immu_toggle -p622 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp623 -sg15 -(lp624 -sg53 -(lp625 -sg13 -(dp626 -g56 -I0 -ssbtp627 -a(V002 -p628 -g1 -(g29 -g3 -Ntp629 -Rp630 -(dp631 -g8 -V002 -p632 -sg23 -VVP_ISA_F011_S010_I002 -p633 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p634 -sg37 -VISA\u000aChapter 2.4 -p635 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p636 -sg41 -Visacov.rv32i_auipc_cg.cp_rd_value\u000aisacov.rv32i_auipc_cg.cp_rd_toggle -p637 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp638 -sg15 -(lp639 -sg53 -(lp640 -sg13 -(dp641 -g56 -I0 -ssbtp642 -asg88 -(lp643 -sg53 -(lp644 -sg13 -(dp645 -sbtp646 -asVrfu_list_0 -p647 -(lp648 -sg88 -(lp649 -sVvptool_gitrev -p650 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p651 -sVio_fmt_gitrev -p652 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p653 -sVconfig_gitrev -p654 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p655 -sVymlcfg_gitrev -p656 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p657 -sbtp658 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml new file mode 100644 index 000000000..ce490437a --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -0,0 +1,697 @@ +!Feature +next_elt_id: 11 +name: RV32I Register-Immediate Instructions +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_ADDI: !Subfeature + name: 000_ADDI + tag: VP_IP011_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S000_I000 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1\nisacov.rv32i_addi_cg.cp_rd\nisacov.rv32i_addi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S000_I001 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1_value\nisacov.rv32i_addi_cg.cp_immi_value\n\ + isacov.rv32i_addi_cg.cross_rs1_immi_value\nisacov.rv32i_addi_cg.cp_rs1_toggle\n\ + isacov.rv32i_addi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S000_I002 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rd_value\nisacov.rv32i_addi_cg.cp_rd_toggle" + comments: '' +- 001_XORI: !Subfeature + name: 001_XORI + tag: VP_IP011_P001 + next_elt_id: 5 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S001_I000 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1\nisacov.rv32i_xori_cg.cp_rd\nisacov.rv32i_xori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S001_I001 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1_value\nisacov.rv32i_xori_cg.cp_immi_value\n\ + isacov.rv32i_xori_cg.cross_rs1_immi_value\nisacov.rv32i_xori_cg.cp_rs1_toggle\n\ + isacov.rv32i_xori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S001_I002 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rd_value\nisacov.rv32i_xori_cg.cp_rd_toggle" + comments: '' +- 002_ORI: !Subfeature + name: 002_ORI + tag: VP_IP011_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S002_I000 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1\nisacov.rv32i_ori_cg.cp_rd\nisacov.rv32i_ori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S002_I001 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1_value\nisacov.rv32i_ori_cg.cp_immi_value\n\ + isacov.rv32i_ori_cg.cross_rs1_immi_value\nisacov.rv32i_ori_cg.cp_rs1_toggle\n\ + isacov.rv32i_ori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S002_I002 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rd_value\nisacov.rv32i_ori_cg.cp_rd_toggle" + comments: '' +- 003_ANDI: !Subfeature + name: 003_ANDI + tag: VP_IP011_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S003_I000 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1\nisacov.rv32i_andi_cg.cp_rd\nisacov.rv32i_andi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S003_I001 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1_value\nisacov.rv32i_andi_cg.cp_immi_value\n\ + isacov.rv32i_andi_cg.cross_rs1_immi_value\nisacov.rv32i_andi_cg.cp_rs1_toggle\n\ + isacov.rv32i_andi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S003_I002 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rd_value\nisacov.rv32i_andi_cg.cp_rd_toggle" + comments: '' +- 004_SLTI: !Subfeature + name: 004_SLTI + tag: VP_IP011_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S004_I000 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1\nisacov.rv32i_slti_cg.cp_rd\nisacov.rv32i_slti_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S004_I001 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1_value\nisacov.rv32i_slti_cg.cp_immi_value\n\ + isacov.rv32i_slti_cg.cross_rs1_immi_value\nisacov.rv32i_slti_cg.cp_rs1_toggle\n\ + isacov.rv32i_slti_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S004_I002 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slti_cg.cp_rd_value + comments: '' +- 005_SLTIU: !Subfeature + name: 005_SLTIU + tag: VP_IP011_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S005_I000 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1\nisacov.rv32i_sltiu_cg.cp_rd\n\ + isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S005_I001 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1_value\nisacov.rv32i_sltiu_cg.cp_immi_value\n\ + isacov.rv32i_sltiu_cg.cross_rs1_immi_value\nisacov.rv32i_sltiu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltiu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S005_I002 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltiu_cg.cp_rd_value + comments: '' +- 006_SLLI: !Subfeature + name: 006_SLLI + tag: VP_IP011_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S006_I000 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1\nisacov.rv32i_slli_cg.cp_rd\nisacov.rv32i_slli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S006_I001 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1_value\nisacov.rv32i_slli_cg.cp_immi_value\n\ + isacov.rv32i_slli_cg.cross_rs1_immi_value\nisacov.rv32i_slli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S006_I002 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rd_value\nisacov.rv32i_slli_cg.cp_rd_toggle" + comments: '' +- 007_SRLI: !Subfeature + name: 007_SRLI + tag: VP_IP011_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S007_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1\nisacov.rv32i_srli_cg.cp_rd\nisacov.rv32i_srli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S007_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1_value\nisacov.rv32i_srli_cg.cp_immi_value\n\ + isacov.rv32i_srli_cg.cross_rs1_immi_value\nisacov.rv32i_srli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S007_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rd_value\nisacov.rv32i_srli_cg.cp_rd_toggle" + comments: '' +- 008_SRAI: !Subfeature + name: 008_SRAI + tag: VP_IP011_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S008_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1\nisacov.rv32i_srai_cg.cp_rd\nisacov.rv32i_srai_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S008_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1_value\nisacov.rv32i_srai_cg.cp_immi_value\n\ + isacov.rv32i_srai_cg.cross_rs1_immi_value\nisacov.rv32i_srai_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S008_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rd_value\nisacov.rv32i_srai_cg.cp_rd_toggle" + comments: '' +- 009_LUI: !Subfeature + name: 009_LUI + tag: VP_IP011_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S009_I000 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_lui_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S009_I001 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_immu_value\nisacov.rv32i_lui_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S009_I002 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_rd_value\nisacov.rv32i_lui_cg.cp_rd_toggle" + comments: '' +- 010_AUIPC: !Subfeature + name: 010_AUIPC + tag: VP_IP011_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S010_I000 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_auipc_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S010_I001 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_immu_value\nisacov.rv32i_auipc_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S010_I002 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_rd_value\nisacov.rv32i_auipc_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck deleted file mode 100644 index 4c356dddb..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck +++ /dev/null @@ -1,1828 +0,0 @@ -(VRV32I Register-Register Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I1 -sVwid_order -p12 -I1 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADD -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP001_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F001_S000_I000 -p34 -sVdescription -p35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_add_cg.cp_rs1\u000aisacov.rv32i_add_cg.cp_rs2\u000aisacov.rv32i_add_cg.cp_rd\u000aisacov.rv32i_add_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_add_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -g58 -sg23 -VVP_ISA_F001_S000_I001 -p62 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p63 -sg37 -VISA\u000aChapter 2.4 -p64 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p65 -sg41 -Visacov.rv32i_add_cg.cp_rs1_value\u000aisacov.rv32i_add_cg.cp_rs2_value\u000aisacov.rv32i_add_cg.cross_rs1_rs2_value\u000aisacov.rv32i_add_cg.cp_rs1_toggle\u000aisacov.rv32i_add_cg.cp_rs2_toggle -p66 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp67 -sg15 -(lp68 -sg53 -(lp69 -sg13 -(dp70 -g56 -I0 -ssbtp71 -a(V002 -p72 -g1 -(g29 -g3 -Ntp73 -Rp74 -(dp75 -g8 -g72 -sg23 -VVP_ISA_F001_S000_I002 -p76 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p77 -sg37 -VISA\u000aChapter 2.4 -p78 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p79 -sg41 -Visacov.rv32i_add_cg.cp_rd_value\u000aisacov.rv32i_add_cg.cp_rd_toggle -p80 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp81 -sg15 -(lp82 -sg53 -(lp83 -sg13 -(dp84 -g56 -I0 -ssbtp85 -asVrfu_list_1 -p86 -(lp87 -sg53 -(lp88 -sg13 -(dp89 -sbtp90 -a(V001_SUB -p91 -g1 -(g18 -g3 -Ntp92 -Rp93 -(dp94 -g22 -I3 -sg8 -g91 -sg23 -VVP_IP001_P001 -p95 -sg25 -(dp96 -sg12 -I1 -sg15 -(lp97 -(V000 -p98 -g1 -(g29 -g3 -Ntp99 -Rp100 -(dp101 -g8 -V000 -p102 -sg23 -VVP_ISA_F001_S001_I000 -p103 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p104 -sg37 -VISA\u000aChapter 2.4 -p105 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p106 -sg41 -Visacov.rv32i_sub_cg.cp_rs1\u000aisacov.rv32i_sub_cg.cp_rs2\u000aisacov.rv32i_sub_cg.cp_rd\u000aisacov.rv32i_sub_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sub_cg.cp_rd_rs2_hazard -p107 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp108 -sg15 -(lp109 -sg53 -(lp110 -sg13 -(dp111 -g56 -I0 -ssbtp112 -a(V001 -p113 -g1 -(g29 -g3 -Ntp114 -Rp115 -(dp116 -g8 -V001 -p117 -sg23 -VVP_ISA_F001_S001_I001 -p118 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p119 -sg37 -VISA\u000aChapter 2.4 -p120 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p121 -sg41 -Visacov.rv32i_sub_cg.cp_rs1_value\u000aisacov.rv32i_sub_cg.cp_rs2_value\u000aisacov.rv32i_sub_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sub_cg.cp_rs1_toggle\u000aisacov.rv32i_sub_cg.cp_rs2_toggle -p122 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp123 -sg15 -(lp124 -sg53 -(lp125 -sg13 -(dp126 -g56 -I0 -ssbtp127 -a(V002 -p128 -g1 -(g29 -g3 -Ntp129 -Rp130 -(dp131 -g8 -V002 -p132 -sg23 -VVP_ISA_F001_S001_I002 -p133 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_sub_cg.cp_rd_value\u000aisacov.rv32i_sub_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg86 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_AND -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I3 -sg8 -g147 -sg23 -VVP_IP001_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F001_S002_I000 -p159 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p162 -sg41 -Visacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard\u000aisacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -V001 -p173 -sg23 -VVP_ISA_F001_S002_I001 -p174 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p175 -sg37 -VISA\u000aChapter 2.4 -p176 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p177 -sg41 -Visacov.rv32i_and_cg.cp_rs1_value\u000aisacov.rv32i_and_cg.cp_rs2_value\u000aisacov.rv32i_and_cg.cross_rs1_rs2_value\u000aisacov.rv32i_and_cg.cp_rs1_toggle\u000aisacov.rv32i_and_cg.cp_rs2_toggle -p178 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp179 -sg15 -(lp180 -sg53 -(lp181 -sg13 -(dp182 -g56 -I0 -ssbtp183 -a(V002 -p184 -g1 -(g29 -g3 -Ntp185 -Rp186 -(dp187 -g8 -V002 -p188 -sg23 -VVP_ISA_F001_S002_I002 -p189 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p190 -sg37 -VISA\u000aChapter 2.4 -p191 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p192 -sg41 -Visacov.rv32i_and_cg.cp_rd_value\u000aisacov.rv32i_and_cg.cp_rd_toggle -p193 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp194 -sg15 -(lp195 -sg53 -(lp196 -sg13 -(dp197 -g56 -I0 -ssbtp198 -asg86 -(lp199 -sg53 -(lp200 -sg13 -(dp201 -sbtp202 -a(V003_OR -p203 -g1 -(g18 -g3 -Ntp204 -Rp205 -(dp206 -g22 -I3 -sg8 -g203 -sg23 -VVP_IP001_P003 -p207 -sg25 -(dp208 -sg12 -I3 -sg15 -(lp209 -(V000 -p210 -g1 -(g29 -g3 -Ntp211 -Rp212 -(dp213 -g8 -V000 -p214 -sg23 -VVP_ISA_F001_S003_I000 -p215 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p216 -sg37 -VISA\u000aChapter 2.4 -p217 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p218 -sg41 -Visacov.rv32i_or_cg.cp_rs1\u000aisacov.rv32i_or_cg.cp_rs2\u000aisacov.rv32i_or_cg.cp_rd\u000aisacov.rv32i_or_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_or_cg.cp_rd_rs2_hazard -p219 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp220 -sg15 -(lp221 -sg53 -(lp222 -sg13 -(dp223 -g56 -I0 -ssbtp224 -a(V001 -p225 -g1 -(g29 -g3 -Ntp226 -Rp227 -(dp228 -g8 -V001 -p229 -sg23 -VVP_ISA_F001_S003_I001 -p230 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p231 -sg37 -VISA\u000aChapter 2.4 -p232 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p233 -sg41 -Visacov.rv32i_or_cg.cp_rs1_value\u000aisacov.rv32i_or_cg.cp_rs2_value\u000aisacov.rv32i_or_cg.cross_rs1_rs2_value\u000aisacov.rv32i_or_cg.cp_rs1_toggle\u000aisacov.rv32i_or_cg.cp_rs2_toggle -p234 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp235 -sg15 -(lp236 -sg53 -(lp237 -sg13 -(dp238 -g56 -I0 -ssbtp239 -a(V002 -p240 -g1 -(g29 -g3 -Ntp241 -Rp242 -(dp243 -g8 -V002 -p244 -sg23 -VVP_ISA_F001_S003_I002 -p245 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p246 -sg37 -VISA\u000aChapter 2.4 -p247 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p248 -sg41 -Visacov.rv32i_or_cg.cp_rd_value\u000aisacov.rv32i_or_cg.cp_rd_toggle -p249 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp250 -sg15 -(lp251 -sg53 -(lp252 -sg13 -(dp253 -g56 -I0 -ssbtp254 -asg86 -(lp255 -sg53 -(lp256 -sg13 -(dp257 -sbtp258 -a(V004_XOR -p259 -g1 -(g18 -g3 -Ntp260 -Rp261 -(dp262 -g22 -I3 -sg8 -g259 -sg23 -VVP_IP001_P004 -p263 -sg25 -(dp264 -sg12 -I4 -sg15 -(lp265 -(V000 -p266 -g1 -(g29 -g3 -Ntp267 -Rp268 -(dp269 -g8 -V000 -p270 -sg23 -VVP_ISA_F001_S004_I000 -p271 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p272 -sg37 -VISA\u000aChapter 2.4 -p273 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p274 -sg41 -Visacov.rv32i_xor_cg.cp_rs1\u000aisacov.rv32i_xor_cg.cp_rs2\u000aisacov.rv32i_xor_cg.cp_rd\u000aisacov.rv32i_xor_cg.rd_rs1_hazard\u000aisacov.rv32i_xor_cg.rd_rs2_hazard -p275 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp276 -sg15 -(lp277 -sg53 -(lp278 -sg13 -(dp279 -g56 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F001_S004_I001 -p286 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p287 -sg37 -VISA\u000aChapter 2.4 -p288 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p289 -sg41 -Visacov.rv32i_xor_cg.cp_rs1_value\u000aisacov.rv32i_xor_cg.cp_rs2_value\u000aisacov.rv32i_xor_cg.cross_rs1_rs2_value\u000aisacov.rv32i_xor_cg.cp_rs1_toggle\u000aisacov.rv32i_xor_cg.cp_rs2_toggle -p290 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp291 -sg15 -(lp292 -sg53 -(lp293 -sg13 -(dp294 -g56 -I0 -ssbtp295 -a(V002 -p296 -g1 -(g29 -g3 -Ntp297 -Rp298 -(dp299 -g8 -V002 -p300 -sg23 -VVP_ISA_F001_S004_I002 -p301 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p302 -sg37 -VISA\u000aChapter 2.4 -p303 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p304 -sg41 -Visacov.rv32i_xor_cg.cp_rd_value\u000aisacov.rv32i_xor_cg.cp_rd_toggle -p305 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp306 -sg15 -(lp307 -sg53 -(lp308 -sg13 -(dp309 -g56 -I0 -ssbtp310 -asg86 -(lp311 -sg53 -(lp312 -sg13 -(dp313 -sbtp314 -a(V005_SLT -p315 -g1 -(g18 -g3 -Ntp316 -Rp317 -(dp318 -g22 -I3 -sg8 -g315 -sg23 -VVP_IP001_P005 -p319 -sg25 -(dp320 -sg12 -I5 -sg15 -(lp321 -(V000 -p322 -g1 -(g29 -g3 -Ntp323 -Rp324 -(dp325 -g8 -V000 -p326 -sg23 -VVP_ISA_F001_S005_I000 -p327 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p328 -sg37 -VISA\u000aChapter 2.4 -p329 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p330 -sg41 -Visacov.rv32i_slt_cg.cp_rs1\u000aisacov.rv32i_slt_cg.cp_rs2\u000aisacov.rv32i_slt_cg.cp_rd\u000aisacov.rv32i_slt_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_slt_cg.cp_rd_rs2_hazard -p331 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp332 -sg15 -(lp333 -sg53 -(lp334 -sg13 -(dp335 -g56 -I0 -ssbtp336 -a(V001 -p337 -g1 -(g29 -g3 -Ntp338 -Rp339 -(dp340 -g8 -V001 -p341 -sg23 -VVP_ISA_F001_S005_I001 -p342 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p343 -sg37 -VISA\u000aChapter 2.4 -p344 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p345 -sg41 -Visacov.rv32i_slt_cg.cp_rs1_value\u000aisacov.rv32i_slt_cg.cp_rs2_value\u000aisacov.rv32i_slt_cg.cross_rs1_rs2_value\u000aisacov.rv32i_slt_cg.cp_rs1_toggle\u000aisacov.rv32i_slt_cg.cp_rs2_toggle -p346 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp347 -sg15 -(lp348 -sg53 -(lp349 -sg13 -(dp350 -g56 -I0 -ssbtp351 -a(V002 -p352 -g1 -(g29 -g3 -Ntp353 -Rp354 -(dp355 -g8 -V002 -p356 -sg23 -VVP_ISA_F001_S005_I002 -p357 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p358 -sg37 -VISA\u000aChapter 2.4 -p359 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p360 -sg41 -Visacov.rv32i_slt_cg.cp_rd_value -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg86 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_SLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP001_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F001_S006_I000 -p383 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p384 -sg37 -VISA\u000aChapter 2.4 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p386 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1\u000aisacov.rv32i_sltu_cg.cp_rs2\u000aisacov.rv32i_sltu_cg.cp_rd\u000aisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sltu_cg.cp_rd_rs2_hazard -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F001_S006_I001 -p398 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p399 -sg37 -VISA\u000aChapter 2.4 -p400 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1_value\u000aisacov.rv32i_sltu_cg.cp_rs2_value\u000aisacov.rv32i_sltu_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sltu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F001_S006_I002 -p413 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p414 -sg37 -VISA\u000aChapter 2.4 -p415 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p416 -sg41 -Visacov.rv32i_sltu_cg.cp_rd_value -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg86 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_SLL -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP001_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F001_S007_I000 -p439 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p440 -sg37 -VISA\u000aChapter 2.4 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p442 -sg41 -Visacov.rv32i_sll_cg.cp_rs1\u000aisacov.rv32i_sll_cg.cp_rs2\u000aisacov.rv32i_sll_cg.cp_rd\u000aisacov.rv32i_sll_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sll_cg.cp_rd_rs2_hazard -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F001_S007_I001 -p454 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p455 -sg37 -VISA\u000aChapter 2.4 -p456 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p457 -sg41 -Visacov.rv32i_sll_cg.cp_rs1_value\u000aisacov.rv32i_sll_cg.cp_rs2_value\u000aisacov.rv32i_sll_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sll_cg.cp_rs1_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F001_S007_I002 -p469 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p470 -sg37 -VISA\u000aChapter 2.4 -p471 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p472 -sg41 -Visacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle\u000aisacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg86 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -a(V008_SRL -p483 -g1 -(g18 -g3 -Ntp484 -Rp485 -(dp486 -g22 -I3 -sg8 -g483 -sg23 -VVP_IP001_P008 -p487 -sg25 -(dp488 -sg12 -I8 -sg15 -(lp489 -(V000 -p490 -g1 -(g29 -g3 -Ntp491 -Rp492 -(dp493 -g8 -V000 -p494 -sg23 -VVP_ISA_F001_S008_I000 -p495 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p496 -sg37 -VISA\u000aChapter 2.4 -p497 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p498 -sg41 -Visacov.rv32i_srl_cg.cp_rs1\u000aisacov.rv32i_srl_cg.cp_rs2\u000aisacov.rv32i_srl_cg.cp_rd\u000aisacov.rv32i_srl_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_srl_cg.cp_rd_rs2_hazard -p499 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp500 -sg15 -(lp501 -sg53 -(lp502 -sg13 -(dp503 -g56 -I0 -ssbtp504 -a(V001 -p505 -g1 -(g29 -g3 -Ntp506 -Rp507 -(dp508 -g8 -V001 -p509 -sg23 -VVP_ISA_F001_S008_I001 -p510 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p511 -sg37 -VISA\u000aChapter 2.4 -p512 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p513 -sg41 -Visacov.rv32i_srl_cg.cp_rs1_value\u000aisacov.rv32i_srl_cg.cp_rs2_value\u000aisacov.rv32i_srl_cg.cross_rs1_rs2_value\u000aisacov.rv32i_srl_cg.cp_rs1_toggle -p514 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp515 -sg15 -(lp516 -sg53 -(lp517 -sg13 -(dp518 -g56 -I0 -ssbtp519 -a(V002 -p520 -g1 -(g29 -g3 -Ntp521 -Rp522 -(dp523 -g8 -V002 -p524 -sg23 -VVP_ISA_F001_S008_I002 -p525 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p526 -sg37 -VISA\u000aChapter 2.4 -p527 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p528 -sg41 -Visacov.rv32i_srl_cg.cp_rd_value\u000aisacov.rv32i_srl_cg.cp_rd_toggle -p529 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp530 -sg15 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -g56 -I0 -ssbtp534 -asg86 -(lp535 -sg53 -(lp536 -sg13 -(dp537 -sbtp538 -a(V009_SRA -p539 -g1 -(g18 -g3 -Ntp540 -Rp541 -(dp542 -g22 -I3 -sg8 -g539 -sg23 -VVP_IP001_P009 -p543 -sg25 -(dp544 -sg12 -I9 -sg15 -(lp545 -(V000 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V000 -p550 -sg23 -VVP_ISA_F001_S009_I000 -p551 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p552 -sg37 -VISA\u000aChapter 2.4 -p553 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p554 -sg41 -Visacov.rv32i_sra_cg.cp_rs1\u000aisacov.rv32i_sra_cg.cp_rs2\u000aisacov.rv32i_sra_cg.cp_rd\u000aisacov.rv32i_sra_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sra_cg.cp_rd_rs2_hazard -p555 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp556 -sg15 -(lp557 -sg53 -(lp558 -sg13 -(dp559 -g56 -I0 -ssbtp560 -a(V001 -p561 -g1 -(g29 -g3 -Ntp562 -Rp563 -(dp564 -g8 -V001 -p565 -sg23 -VVP_ISA_F001_S009_I001 -p566 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p567 -sg37 -VISA\u000aChapter 2.4 -p568 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve, and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 +ve, -ve and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p569 -sg41 -Visacov.rv32i_sra_cg.cp_rs1_value\u000aisacov.rv32i_sra_cg.cp_rs2_value\u000aisacov.rv32i_sra_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sra_cg.cp_rs1_toggle -p570 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp571 -sg15 -(lp572 -sg53 -(lp573 -sg13 -(dp574 -g56 -I0 -ssbtp575 -a(V002 -p576 -g1 -(g29 -g3 -Ntp577 -Rp578 -(dp579 -g8 -V002 -p580 -sg23 -VVP_ISA_F001_S009_I002 -p581 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p582 -sg37 -VISA\u000aChapter 2.4 -p583 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve, and zero.\u000aAll bits of rd are toggled -p584 -sg41 -Visacov.rv32i_sra_cg.cp_rd_value\u000aisacov.rv32i_sra_cg.cp_rd_toggle -p585 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp586 -sg15 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -g56 -I0 -ssbtp590 -asg86 -(lp591 -sg53 -(lp592 -sg13 -(dp593 -sbtp594 -asVrfu_list_0 -p595 -(lp596 -sg86 -(lp597 -sVvptool_gitrev -p598 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p599 -sVio_fmt_gitrev -p600 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p601 -sVconfig_gitrev -p602 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p603 -sVymlcfg_gitrev -p604 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p605 -sbtp606 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml new file mode 100644 index 000000000..67a3f707d --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -0,0 +1,665 @@ +!Feature +next_elt_id: 10 +name: RV32I Register-Register Instructions +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_ADD: !Subfeature + name: 000_ADD + tag: VP_IP001_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S000_I000 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1\nisacov.rv32i_add_cg.cp_rs2\nisacov.rv32i_add_cg.cp_rd\n\ + isacov.rv32i_add_cg.cp_rd_rs1_hazard\nisacov.rv32i_add_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S000_I001 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1_value\nisacov.rv32i_add_cg.cp_rs2_value\n\ + isacov.rv32i_add_cg.cross_rs1_rs2_value\nisacov.rv32i_add_cg.cp_rs1_toggle\n\ + isacov.rv32i_add_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S000_I002 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rd_value\nisacov.rv32i_add_cg.cp_rd_toggle" + comments: '' +- 001_SUB: !Subfeature + name: 001_SUB + tag: VP_IP001_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S001_I000 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1\nisacov.rv32i_sub_cg.cp_rs2\nisacov.rv32i_sub_cg.cp_rd\n\ + isacov.rv32i_sub_cg.cp_rd_rs1_hazard\nisacov.rv32i_sub_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S001_I001 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1_value\nisacov.rv32i_sub_cg.cp_rs2_value\n\ + isacov.rv32i_sub_cg.cross_rs1_rs2_value\nisacov.rv32i_sub_cg.cp_rs1_toggle\n\ + isacov.rv32i_sub_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S001_I002 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rd_value\nisacov.rv32i_sub_cg.cp_rd_toggle" + comments: '' +- 002_AND: !Subfeature + name: 002_AND + tag: VP_IP001_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S002_I000 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard\n\ + isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S002_I001 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1_value\nisacov.rv32i_and_cg.cp_rs2_value\n\ + isacov.rv32i_and_cg.cross_rs1_rs2_value\nisacov.rv32i_and_cg.cp_rs1_toggle\n\ + isacov.rv32i_and_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S002_I002 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rd_value\nisacov.rv32i_and_cg.cp_rd_toggle" + comments: '' +- 003_OR: !Subfeature + name: 003_OR + tag: VP_IP001_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S003_I000 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1\nisacov.rv32i_or_cg.cp_rs2\nisacov.rv32i_or_cg.cp_rd\n\ + isacov.rv32i_or_cg.cp_rd_rs1_hazard\nisacov.rv32i_or_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S003_I001 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1_value\nisacov.rv32i_or_cg.cp_rs2_value\n\ + isacov.rv32i_or_cg.cross_rs1_rs2_value\nisacov.rv32i_or_cg.cp_rs1_toggle\n\ + isacov.rv32i_or_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S003_I002 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rd_value\nisacov.rv32i_or_cg.cp_rd_toggle" + comments: '' +- 004_XOR: !Subfeature + name: 004_XOR + tag: VP_IP001_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S004_I000 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1\nisacov.rv32i_xor_cg.cp_rs2\nisacov.rv32i_xor_cg.cp_rd\n\ + isacov.rv32i_xor_cg.rd_rs1_hazard\nisacov.rv32i_xor_cg.rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S004_I001 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1_value\nisacov.rv32i_xor_cg.cp_rs2_value\n\ + isacov.rv32i_xor_cg.cross_rs1_rs2_value\nisacov.rv32i_xor_cg.cp_rs1_toggle\n\ + isacov.rv32i_xor_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S004_I002 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rd_value\nisacov.rv32i_xor_cg.cp_rd_toggle" + comments: '' +- 005_SLT: !Subfeature + name: 005_SLT + tag: VP_IP001_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S005_I000 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1\nisacov.rv32i_slt_cg.cp_rs2\nisacov.rv32i_slt_cg.cp_rd\n\ + isacov.rv32i_slt_cg.cp_rd_rs1_hazard\nisacov.rv32i_slt_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S005_I001 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1_value\nisacov.rv32i_slt_cg.cp_rs2_value\n\ + isacov.rv32i_slt_cg.cross_rs1_rs2_value\nisacov.rv32i_slt_cg.cp_rs1_toggle\n\ + isacov.rv32i_slt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S005_I002 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slt_cg.cp_rd_value + comments: '' +- 006_SLTU: !Subfeature + name: 006_SLTU + tag: VP_IP001_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S006_I000 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1\nisacov.rv32i_sltu_cg.cp_rs2\n\ + isacov.rv32i_sltu_cg.cp_rd\nisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\nisacov.rv32i_sltu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S006_I001 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1_value\nisacov.rv32i_sltu_cg.cp_rs2_value\n\ + isacov.rv32i_sltu_cg.cross_rs1_rs2_value\nisacov.rv32i_sltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S006_I002 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltu_cg.cp_rd_value + comments: '' +- 007_SLL: !Subfeature + name: 007_SLL + tag: VP_IP001_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S007_I000 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1\nisacov.rv32i_sll_cg.cp_rs2\nisacov.rv32i_sll_cg.cp_rd\n\ + isacov.rv32i_sll_cg.cp_rd_rs1_hazard\nisacov.rv32i_sll_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S007_I001 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1_value\nisacov.rv32i_sll_cg.cp_rs2_value\n\ + isacov.rv32i_sll_cg.cross_rs1_rs2_value\nisacov.rv32i_sll_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S007_I002 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle\n\ + isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle" + comments: '' +- 008_SRL: !Subfeature + name: 008_SRL + tag: VP_IP001_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S008_I000 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1\nisacov.rv32i_srl_cg.cp_rs2\nisacov.rv32i_srl_cg.cp_rd\n\ + isacov.rv32i_srl_cg.cp_rd_rs1_hazard\nisacov.rv32i_srl_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S008_I001 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1_value\nisacov.rv32i_srl_cg.cp_rs2_value\n\ + isacov.rv32i_srl_cg.cross_rs1_rs2_value\nisacov.rv32i_srl_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S008_I002 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rd_value\nisacov.rv32i_srl_cg.cp_rd_toggle" + comments: '' +- 009_SRA: !Subfeature + name: 009_SRA + tag: VP_IP001_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S009_I000 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1\nisacov.rv32i_sra_cg.cp_rs2\nisacov.rv32i_sra_cg.cp_rd\n\ + isacov.rv32i_sra_cg.cp_rd_rs1_hazard\nisacov.rv32i_sra_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S009_I001 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve, and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 +ve, -ve and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1_value\nisacov.rv32i_sra_cg.cp_rs2_value\n\ + isacov.rv32i_sra_cg.cross_rs1_rs2_value\nisacov.rv32i_sra_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S009_I002 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve, and zero.\nAll bits\ + \ of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rd_value\nisacov.rv32i_sra_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck deleted file mode 100644 index e2b333919..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck +++ /dev/null @@ -1,1478 +0,0 @@ -(VRV32I Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I2 -sVwid_order -p12 -I2 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_JAL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP002_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F002_S000_I000 -p34 -sVdescription -p35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p36 -sVpurpose -p37 -VISA\u000aChapter 2.5 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -Visacov.rv32i_jal_cg.cp_rd -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F002_S000_I001 -p63 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p64 -sg37 -VISA\u000aChapter 2.5 -p65 -sg39 -VInput operands:\u000a\u000aimmj value is +ve, -ve, and zero\u000aAll bits of immj are toggled -p66 -sg41 -Visacov.rv32i_jal_cg.cp_immj_value\u000aisacov.rv32i_jal_cg.cp_immj_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F002_S000_I002 -p78 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p79 -sg37 -VISA\u000aChapter 2.5 -p80 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_jal_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_JALR -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP002_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F002_S001_I000 -p105 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.5 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_jalr_cg.cp_rs1\u000aisacov.rv32i_jalr_cg.cp_rd\u000aisacov.rv32i_jalr_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F002_S001_I001 -p120 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.5 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve, and zero\u000aAll bits of immi are toggled\u000aAll bits of rs1 are toggled -p123 -sg41 -Visacov.rv32i_jalr_cg.cp_immi_value\u000aisacov.rv32i_jalr_cg.cp_immi_toggle\u000aisacov.rv32i_jalr_cg.cp_rs1_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F002_S001_I002 -p135 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.5 -p137 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_jalr_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_BEQ -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP002_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F002_S002_I000 -p161 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.5 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p164 -sg41 -Visacov.rv32i_beq_cg.cp_rs1\u000aisacov.rv32i_beq_cg.cp_rs2 -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F002_S002_I001 -p176 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.5 -p178 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32i_beq_cg.cp_immb_value\u000aisacov.rv32i_beq_cg.cp_rs1_toggle\u000aisacov.rv32i_beq_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F002_S002_I002 -p191 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.5 -p193 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p194 -sg41 -Visacov.rv32i_beq_cg.cp_branch_taken -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_BNE -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP002_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F002_S003_I000 -p217 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p218 -sg37 -VISA\u000aChapter 2.5 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p220 -sg41 -Visacov.rv32i_bne_cg.cp_rs1\u000aisacov.rv32i_bne_cg.cp_rs2 -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F002_S003_I001 -p232 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p233 -sg37 -VISA\u000aChapter 2.5 -p234 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32i_bne_cg.cp_immb_value\u000aisacov.rv32i_bne_cg.cp_rs1_toggle\u000aisacov.rv32i_bne_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F002_S003_I002 -p247 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p248 -sg37 -VISA\u000aChapter 2.5 -p249 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p250 -sg41 -Visacov.rv32i_bne_cg.cp_branch_taken -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_BLT -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP002_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F002_S004_I000 -p273 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p274 -sg37 -VISA\u000aChapter 2.5 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p276 -sg41 -Visacov.rv32i_blt_cg.cp_rs1\u000aisacov.rv32i_blt_cg.cp_rs2 -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F002_S004_I001 -p288 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p289 -sg37 -VISA\u000aChapter 2.5 -p290 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p291 -sg41 -Visacov.rv32i_blt_cg.cp_immb_value\u000aisacov.rv32i_blt_cg.cp_rs1_toggle\u000aisacov.rv32i_blt_cg.cp_rs2_toggle -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F002_S004_I002 -p303 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p304 -sg37 -VISA\u000aChapter 2.5 -p305 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p306 -sg41 -Visacov.rv32i_blt_cg.cp_branch_taken -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_BGE -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I6 -sg8 -g317 -sg23 -VVP_IP002_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F002_S005_I000 -p329 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p330 -sg37 -VISA\u000aChapter 2.5 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_bge_cg.cp_rs1\u000aisacov.rv32i_bge_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -g339 -sg23 -VVP_ISA_F002_S005_I001 -p343 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p344 -sg37 -VISA\u000aChapter 2.5 -p345 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p346 -sg41 -Visacov.rv32i_bge_cg.cp_immb_value\u000aisacov.rv32i_bge_cg.cp_rs1_toggle\u000aisacov.rv32i_bge_cg.cp_rs2_toggle -p347 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp348 -sg15 -(lp349 -sg53 -(lp350 -sg13 -(dp351 -g56 -I0 -ssbtp352 -a(V002 -p353 -g1 -(g29 -g3 -Ntp354 -Rp355 -(dp356 -g8 -g353 -sg23 -VVP_ISA_F002_S005_I002 -p357 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p358 -sg37 -VISA\u000aChapter 2.5 -p359 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p360 -sg41 -Visacov.rv32i_bge_cg.cp_branch_taken -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg88 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_BLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP002_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F002_S006_I000 -p383 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p384 -sg37 -VISA\u000aChapter 2.5 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p386 -sg41 -Visacov.rv32i_bltu_cg.cp_rs1\u000aisacov.rv32i_bltu_cg.cp_rs2 -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F002_S006_I001 -p398 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p399 -sg37 -VISA\u000aChapter 2.5 -p400 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_bltu_cg.cp_immb_value\u000aisacov.rv32i_bltu_cg.cp_rs1_toggle\u000aisacov.rv32i_bltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F002_S006_I002 -p413 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p414 -sg37 -VISA\u000aChapter 2.5 -p415 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p416 -sg41 -Visacov.rv32i_bltu_cg.cp_branch_taken -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg88 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_BGEU -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP002_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F002_S007_I000 -p439 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p440 -sg37 -VISA\u000aChapter 2.5 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p442 -sg41 -Visacov.rv32i_bgeu_cg.cp_rs1\u000aisacov.rv32i_bgeu_cg.cp_rs2 -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F002_S007_I001 -p454 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p455 -sg37 -VISA\u000aChapter 2.5 -p456 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p457 -sg41 -Visacov.rv32i_bgeu_cg.cp_immb_value\u000aisacov.rv32i_bgeu_cg.cp_rs1_toggle\u000aisacov.rv32i_bgeu_cg.cp_rs2_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F002_S007_I002 -p469 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p470 -sg37 -VISA\u000aChapter 2.5 -p471 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p472 -sg41 -Visacov.rv32i_bgeu_cg.cp_branch_taken -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg88 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -asVrfu_list_0 -p483 -(lp484 -sg88 -(lp485 -sVvptool_gitrev -p486 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p487 -sVio_fmt_gitrev -p488 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p489 -sVconfig_gitrev -p490 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p491 -sVymlcfg_gitrev -p492 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p493 -sbtp494 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml new file mode 100644 index 000000000..f08639528 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -0,0 +1,498 @@ +!Feature +next_elt_id: 8 +name: RV32I Control Transfer Instructions +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_JAL: !Subfeature + name: 000_JAL + tag: VP_IP002_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S000_I000 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S000_I001 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmj value is +ve, -ve, and zero\nAll bits\ + \ of immj are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jal_cg.cp_immj_value\nisacov.rv32i_jal_cg.cp_immj_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S000_I002 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd_toggle + comments: '' +- 001_JALR: !Subfeature + name: 001_JALR + tag: VP_IP002_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S001_I000 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_rs1\nisacov.rv32i_jalr_cg.cp_rd\nisacov.rv32i_jalr_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S001_I001 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve, and zero\nAll bits\ + \ of immi are toggled\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_immi_value\nisacov.rv32i_jalr_cg.cp_immi_toggle\n\ + isacov.rv32i_jalr_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S001_I002 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jalr_cg.cp_rd_toggle + comments: '' +- 002_BEQ: !Subfeature + name: 002_BEQ + tag: VP_IP002_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S002_I000 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_rs1\nisacov.rv32i_beq_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S002_I001 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_immb_value\nisacov.rv32i_beq_cg.cp_rs1_toggle\n\ + isacov.rv32i_beq_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S002_I002 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_beq_cg.cp_branch_taken + comments: '' +- 003_BNE: !Subfeature + name: 003_BNE + tag: VP_IP002_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S003_I000 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_rs1\nisacov.rv32i_bne_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S003_I001 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_immb_value\nisacov.rv32i_bne_cg.cp_rs1_toggle\n\ + isacov.rv32i_bne_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S003_I002 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bne_cg.cp_branch_taken + comments: '' +- 004_BLT: !Subfeature + name: 004_BLT + tag: VP_IP002_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S004_I000 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_rs1\nisacov.rv32i_blt_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S004_I001 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_immb_value\nisacov.rv32i_blt_cg.cp_rs1_toggle\n\ + isacov.rv32i_blt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S004_I002 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_blt_cg.cp_branch_taken + comments: '' +- 005_BGE: !Subfeature + name: 005_BGE + tag: VP_IP002_P005 + next_elt_id: 6 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S005_I000 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_rs1\nisacov.rv32i_bge_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S005_I001 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_immb_value\nisacov.rv32i_bge_cg.cp_rs1_toggle\n\ + isacov.rv32i_bge_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S005_I002 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bge_cg.cp_branch_taken + comments: '' +- 006_BLTU: !Subfeature + name: 006_BLTU + tag: VP_IP002_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S006_I000 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_rs1\nisacov.rv32i_bltu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S006_I001 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_immb_value\nisacov.rv32i_bltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S006_I002 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bltu_cg.cp_branch_taken + comments: '' +- 007_BGEU: !Subfeature + name: 007_BGEU + tag: VP_IP002_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S007_I000 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_rs1\nisacov.rv32i_bgeu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S007_I001 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_immb_value\nisacov.rv32i_bgeu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bgeu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S007_I002 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bgeu_cg.cp_branch_taken + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck deleted file mode 100644 index bcd79324f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck +++ /dev/null @@ -1,1333 +0,0 @@ -(VRV32I Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP003_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F003_S000_I000 -p34 -sVdescription -p35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VISA\u000aChapter 2.6 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_lb_cg.cp_rs1\u000aisacov.rv32i_lb_cg.cp_rd\u000aisacov.rv32i_lb_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F003_S000_I001 -p63 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p64 -sg37 -VISA\u000aChapter 2.6 -p65 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_lb_cg.cp_immi_value\u000aisacov.rv32i_lb_cg.cp_rs1_toggle\u000aisacov.rv32i_lb_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F003_S000_I002 -p78 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p79 -sg37 -VISA\u000aChapter 2.6 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_lb_cg.cp_rd_value\u000aisacov.rv32i_lb_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_LH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP003_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F003_S001_I000 -p105 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.6 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_lh_cg.cp_rs1\u000aisacov.rv32i_lh_cg.cp_rd\u000aisacov.rv32i_lh_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F003_S001_I001 -p120 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.6 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p123 -sg41 -Visacov.rv32i_lh_cg.cp_immi_value\u000aisacov.rv32i_lh_cg.cp_rs1_toggle\u000aisacov.rv32i_lh_cg.cp_immi_toggle\u000aisacov.rv32i_lh_cg.cp_aligned -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F003_S001_I002 -p135 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.6 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_lh_cg.cp_rd_value\u000aisacov.rv32i_lh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_LW -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP003_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F003_S002_I000 -p161 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.6 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p164 -sg41 -Visacov.rv32i_lw_cg.cp_rs1\u000aisacov.rv32i_lw_cg.cp_rd\u000aisacov.rv32i_lw_cg.cp_rd_rs1_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F003_S002_I001 -p176 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.6 -p178 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p179 -sg41 -Visacov.rv32i_lw_cg.cp_immi_value\u000aisacov.rv32i_lw_cg.cp_rs1_toggle\u000aisacov.rv32i_lw_cg.cp_immi_toggle\u000aisacov.rv32i_lw_cg.cp_aligned -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F003_S002_I002 -p191 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.6 -p193 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32i_lw_cg.cp_rd_value\u000aisacov.rv32i_lw_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_LBU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP003_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F003_S003_I000 -p217 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p218 -sg37 -VISA\u000aChapter 2.6 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p220 -sg41 -Visacov.rv32i_lbu_cg.cp_rs1\u000aisacov.rv32i_lbu_cg.cp_rd\u000aisacov.rv32i_lbu_cg.cp_rd_rs1_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F003_S003_I001 -p232 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p233 -sg37 -VISA\u000aChapter 2.6 -p234 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p235 -sg41 -Visacov.rv32i_lbu_cg.cp_immi_value\u000aisacov.rv32i_lbu_cg.cp_rs1_toggle\u000aisacov.rv32i_lbu_cg.cp_immi_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F003_S003_I002 -p247 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p248 -sg37 -VISA\u000aChapter 2.6 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[7:0] are toggled -p250 -sg41 -Visacov.rv32i_lbu_cg.cp_rd_value\u000aisacov.rv32i_lbu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_LHU -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP003_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F003_S004_I000 -p273 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p274 -sg37 -VISA\u000aChapter 2.6 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p276 -sg41 -Visacov.rv32i_lhu_cg.cp_rs1\u000aisacov.rv32i_lhu_cg.cp_rd\u000aisacov.rv32i_lhu_cg.cp_rd_rs1_hazard -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F003_S004_I001 -p288 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p289 -sg37 -VISA\u000aChapter 2.6 -p290 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p291 -sg41 -Visacov.rv32i_lhu_cg.cp_immi_value\u000aisacov.rv32i_lhu_cg.cp_rs1_toggle\u000aisacov.rv32i_lhu_cg.cp_immi_toggle\u000aisacov.rv32i_lhu_cg.cp_aligned -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F003_S004_I002 -p303 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p304 -sg37 -VISA\u000aChapter 2.6 -p305 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[15:0] are toggled -p306 -sg41 -Visacov.rv32i_lhu_cg.cp_rd_value\u000aisacov.rv32i_lhu_cg.cp_rd_toggle -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_SB -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I3 -sg8 -g317 -sg23 -VVP_IP003_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F003_S005_I000 -p329 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p330 -sg37 -VISA\u000aChapter 2.6 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_sb_cg.cp_rs1\u000aisacov.rv32i_sb_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -V001 -p343 -sg23 -VVP_ISA_F003_S005_I001 -p344 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p345 -sg37 -VISA\u000aChapter 2.6 -p346 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled -p347 -sg41 -Visacov.rv32i_sb_cg.cp_imms_value\u000aisacov.rv32i_sb_cg.cp_rs1_toggle\u000aisacov.rv32i_sb_cg.cp_rs2_toggle\u000aisacov.rv32i_sb_cg.cp_imms_toggle -p348 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp349 -sg15 -(lp350 -sg53 -(lp351 -sg13 -(dp352 -g56 -I0 -ssbtp353 -asg88 -(lp354 -sg53 -(lp355 -sg13 -(dp356 -sbtp357 -a(V006_SH -p358 -g1 -(g18 -g3 -Ntp359 -Rp360 -(dp361 -g22 -I2 -sg8 -g358 -sg23 -VVP_IP003_P006 -p362 -sg25 -(dp363 -sg12 -I6 -sg15 -(lp364 -(V000 -p365 -g1 -(g29 -g3 -Ntp366 -Rp367 -(dp368 -g8 -V000 -p369 -sg23 -VVP_ISA_F003_S006_I000 -p370 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p371 -sg37 -VISA\u000aChapter 2.6 -p372 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p373 -sg41 -Visacov.rv32i_sh_cg.cp_rs1\u000aisacov.rv32i_sh_cg.cp_rs2 -p374 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp375 -sg15 -(lp376 -sg53 -(lp377 -sg13 -(dp378 -g56 -I0 -ssbtp379 -a(V001 -p380 -g1 -(g29 -g3 -Ntp381 -Rp382 -(dp383 -g8 -V001 -p384 -sg23 -VVP_ISA_F003_S006_I001 -p385 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p386 -sg37 -VISA\u000aChapter 2.6 -p387 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p388 -sg41 -Visacov.rv32i_sh_cg.cp_imms_value\u000aisacov.rv32i_sh_cg.cp_rs1_toggle\u000aisacov.rv32i_sh_cg.cp_rs2_toggle\u000aisacov.rv32i_sh_cg.cp_imms_toggle\u000aisacov.rv32i_sh_cg.cp_aligned -p389 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp390 -sg15 -(lp391 -sg53 -(lp392 -sg13 -(dp393 -g56 -I0 -ssbtp394 -asg88 -(lp395 -sg53 -(lp396 -sg13 -(dp397 -sbtp398 -a(V007_SW -p399 -g1 -(g18 -g3 -Ntp400 -Rp401 -(dp402 -g22 -I2 -sg8 -g399 -sg23 -VVP_IP003_P007 -p403 -sg25 -(dp404 -sg12 -I7 -sg15 -(lp405 -(V000 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V000 -p410 -sg23 -VVP_ISA_F003_S007_I000 -p411 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p412 -sg37 -VISA\u000aChapter 2.6 -p413 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p414 -sg41 -Visacov.rv32i_sw_cg.cp_rs1\u000aisacov.rv32i_sw_cg.cp_rs2 -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -a(V001 -p421 -g1 -(g29 -g3 -Ntp422 -Rp423 -(dp424 -g8 -V001 -p425 -sg23 -VVP_ISA_F003_S007_I001 -p426 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p427 -sg37 -VISA\u000aChapter 2.6 -p428 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p429 -sg41 -Visacov.rv32i_sw_cg.cp_imms_value\u000aisacov.rv32i_sw_cg.cp_rs1_toggle\u000aisacov.rv32i_sw_cg.cp_rs2_toggle\u000aisacov.rv32i_sw_cg.cp_imms_toggle\u000aisacov.rv32i_sw_cg.cp_aligned -p430 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp431 -sg15 -(lp432 -sg53 -(lp433 -sg13 -(dp434 -g56 -I0 -ssbtp435 -asg88 -(lp436 -sg53 -(lp437 -sg13 -(dp438 -sbtp439 -asVrfu_list_0 -p440 -(lp441 -sg88 -(lp442 -sVvptool_gitrev -p443 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p444 -sVio_fmt_gitrev -p445 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p446 -sVconfig_gitrev -p447 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p448 -sVymlcfg_gitrev -p449 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p450 -sbtp451 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml new file mode 100644 index 000000000..7980343f7 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -0,0 +1,454 @@ +!Feature +next_elt_id: 8 +name: RV32I Load and Store Instructions +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_LB: !Subfeature + name: 000_LB + tag: VP_IP003_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S000_I000 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rs1\nisacov.rv32i_lb_cg.cp_rd\nisacov.rv32i_lb_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S000_I001 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_immi_value\nisacov.rv32i_lb_cg.cp_rs1_toggle\n\ + isacov.rv32i_lb_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S000_I002 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rd_value\nisacov.rv32i_lb_cg.cp_rd_toggle" + comments: '' +- 001_LH: !Subfeature + name: 001_LH + tag: VP_IP003_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S001_I000 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rs1\nisacov.rv32i_lh_cg.cp_rd\nisacov.rv32i_lh_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S001_I001 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_immi_value\nisacov.rv32i_lh_cg.cp_rs1_toggle\n\ + isacov.rv32i_lh_cg.cp_immi_toggle\nisacov.rv32i_lh_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S001_I002 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rd_value\nisacov.rv32i_lh_cg.cp_rd_toggle" + comments: '' +- 002_LW: !Subfeature + name: 002_LW + tag: VP_IP003_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S002_I000 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rs1\nisacov.rv32i_lw_cg.cp_rd\nisacov.rv32i_lw_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S002_I001 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_immi_value\nisacov.rv32i_lw_cg.cp_rs1_toggle\n\ + isacov.rv32i_lw_cg.cp_immi_toggle\nisacov.rv32i_lw_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S002_I002 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rd_value\nisacov.rv32i_lw_cg.cp_rd_toggle" + comments: '' +- 003_LBU: !Subfeature + name: 003_LBU + tag: VP_IP003_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S003_I000 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rs1\nisacov.rv32i_lbu_cg.cp_rd\nisacov.rv32i_lbu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S003_I001 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_immi_value\nisacov.rv32i_lbu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lbu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S003_I002 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[7:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rd_value\nisacov.rv32i_lbu_cg.cp_rd_toggle" + comments: '' +- 004_LHU: !Subfeature + name: 004_LHU + tag: VP_IP003_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S004_I000 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rs1\nisacov.rv32i_lhu_cg.cp_rd\nisacov.rv32i_lhu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S004_I001 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_immi_value\nisacov.rv32i_lhu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lhu_cg.cp_immi_toggle\nisacov.rv32i_lhu_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S004_I002 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[15:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rd_value\nisacov.rv32i_lhu_cg.cp_rd_toggle" + comments: '' +- 005_SB: !Subfeature + name: 005_SB + tag: VP_IP003_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S005_I000 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_rs1\nisacov.rv32i_sb_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S005_I001 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_imms_value\nisacov.rv32i_sb_cg.cp_rs1_toggle\n\ + isacov.rv32i_sb_cg.cp_rs2_toggle\nisacov.rv32i_sb_cg.cp_imms_toggle" + comments: '' +- 006_SH: !Subfeature + name: 006_SH + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S006_I000 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_rs1\nisacov.rv32i_sh_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S006_I001 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_imms_value\nisacov.rv32i_sh_cg.cp_rs1_toggle\n\ + isacov.rv32i_sh_cg.cp_rs2_toggle\nisacov.rv32i_sh_cg.cp_imms_toggle\nisacov.rv32i_sh_cg.cp_aligned" + comments: '' +- 007_SW: !Subfeature + name: 007_SW + tag: VP_IP003_P007 + next_elt_id: 2 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S007_I000 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_rs1\nisacov.rv32i_sw_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S007_I001 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_imms_value\nisacov.rv32i_sw_cg.cp_rs1_toggle\n\ + isacov.rv32i_sw_cg.cp_rs2_toggle\nisacov.rv32i_sw_cg.cp_imms_toggle\nisacov.rv32i_sw_cg.cp_aligned" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck deleted file mode 100644 index bd77b2b90..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32I Memory Ordering Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F004_S000_I000 -p34 -sVdescription -p35 -VFence operation executed\u000aImplementation is microarchitecture specific -p36 -sVpurpose -p37 -VISA\u000aChapter 2.7 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_fence.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml new file mode 100644 index 000000000..332583c94 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -0,0 +1,33 @@ +!Feature +next_elt_id: 1 +name: RV32I Memory Ordering Instructions +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_FENCE: !Subfeature + name: 000_FENCE + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F004_S000_I000 + description: "Fence operation executed\nImplementation is microarchitecture\ + \ specific" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_fence.cp_fixed + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck deleted file mode 100644 index f17fd3ee4..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck +++ /dev/null @@ -1,284 +0,0 @@ -(VRV32I Environment Call and Breakpoints -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ECALL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F005_S000_I000 -p34 -sVdescription -p35 -VSoftware exception vector entered -p36 -sVpurpose -p37 -VISA\u000aChapter 2.8 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_ecall.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F005_S000_I001 -p63 -sg35 -VReturn control to a debugger -p64 -sg37 -VISA\u000aChapter 2.8 -p65 -sg39 -VInstruction executed -p66 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -asVrfu_list_1 -p73 -(lp74 -sg53 -(lp75 -sg13 -(dp76 -sbtp77 -a(V001_EBREAK -p78 -g1 -(g18 -g3 -Ntp79 -Rp80 -(dp81 -g22 -I1 -sg8 -g78 -sg23 -VVP_IP005_P001 -p82 -sg25 -(dp83 -sg12 -I1 -sg15 -(lp84 -(V000 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V000 -p89 -sg23 -VVP_ISA_F005_S001_I000 -p90 -sg35 -VReturn control to a debugger -p91 -sg37 -VISA\u000aChapter 2.8 -p92 -sg39 -VInstruction executed -p93 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p94 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp95 -sg15 -(lp96 -sg53 -(lp97 -sg13 -(dp98 -Vlock_status -p99 -I0 -ssbtp100 -asg73 -(lp101 -sg53 -(lp102 -sg13 -(dp103 -sbtp104 -asVrfu_list_0 -p105 -(lp106 -sg73 -(lp107 -sVvptool_gitrev -p108 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p109 -sVio_fmt_gitrev -p110 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p111 -sVconfig_gitrev -p112 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p113 -sVymlcfg_gitrev -p114 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p115 -sbtp116 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml new file mode 100644 index 000000000..a2cfdcaa3 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -0,0 +1,70 @@ +!Feature +next_elt_id: 2 +name: RV32I Environment Call and Breakpoints +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_ECALL: !Subfeature + name: 000_ECALL + tag: VP_IP005_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F005_S000_I000 + description: Software exception vector entered + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ecall.cp_fixed + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F005_S000_I001 + description: Return control to a debugger + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +- 001_EBREAK: !Subfeature + name: 001_EBREAK + tag: VP_IP005_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F005_S001_I000 + description: Return control to a debugger + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck deleted file mode 100644 index 540f7f495..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck +++ /dev/null @@ -1,780 +0,0 @@ -(VRV32M Multiplication Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I7 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_MUL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP000_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F000_S000_I000 -p34 -sVdescription -p35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.1 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_mul_cg.cp_rs1\u000aisacov.rv32m_mul_cg.cp_rs2\u000aisacov.rv32m_mul_cg.cp_rd\u000aisacov.rv32m_mul_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mul_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F000_S000_I001 -p63 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_mul_cg.cp_rs1_value\u000aisacov.rv32m_mul_cg.cp_rs2_value\u000aisacov.rv32m_mul_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mul_cg.cp_rs1_toggle \u000aisacov.rv32m_mul_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F000_S000_I002 -p78 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p80 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_mul_cg.cp_rd_value\u000aisacov.rv32m_mul_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_MULH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP000_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F000_S001_I000 -p105 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p106 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p108 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1\u000aisacov.rv32m_mulh_cg.cp_rs2\u000aisacov.rv32m_mulh_cg.cp_rd\u000aisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulh_cg.cp_rd_rs2_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F000_S001_I001 -p120 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p122 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p123 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1_value\u000aisacov.rv32m_mulh_cg.cp_rs2_value\u000aisacov.rv32m_mulh_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulh_cg.cp_rs1_toggle \u000aisacov.rv32m_mulh_cg.cp_rs2_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F000_S001_I002 -p135 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32m_mulh_cg.cp_rd_value\u000aisacov.rv32m_mulh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_MULHU -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP000_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F000_S002_I000 -p161 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p162 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p164 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1\u000aisacov.rv32m_mulhu_cg.cp_rs2\u000aisacov.rv32m_mulhu_cg.cp_rd\u000aisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F000_S002_I001 -p176 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p177 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p178 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1_value\u000aisacov.rv32m_mulhu_cg.cp_rs2_value\u000aisacov.rv32m_mulhu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhu_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F000_S002_I002 -p191 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p193 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32m_mulhu_cg.cp_rd_value\u000aisacov.rv32m_mulhu_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_MULHSU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP000_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F000_S003_I000 -p217 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p218 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p220 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1\u000aisacov.rv32m_mulhsu_cg.cp_rs2\u000aisacov.rv32m_mulhsu_cg.cp_rd\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F000_S003_I001 -p232 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p233 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p234 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1_value\u000aisacov.rv32m_mulhsu_cg.cp_rs2_value\u000aisacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhsu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhsu_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F000_S003_I002 -p247 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p248 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p250 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rd_value\u000aisacov.rv32m_mulhsu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -asVrfu_list_0 -p261 -(lp262 -sg88 -(lp263 -sVvptool_gitrev -p264 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p265 -sVio_fmt_gitrev -p266 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p267 -sVconfig_gitrev -p268 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p269 -sVymlcfg_gitrev -p270 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p271 -sbtp272 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml new file mode 100644 index 000000000..d6f0e2de4 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -0,0 +1,275 @@ +!Feature +next_elt_id: 7 +name: RV32M Multiplication Operations +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_MUL: !Subfeature + name: 000_MUL + tag: VP_IP000_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S000_I000 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1\nisacov.rv32m_mul_cg.cp_rs2\nisacov.rv32m_mul_cg.cp_rd\n\ + isacov.rv32m_mul_cg.cp_rd_rs1_hazard\nisacov.rv32m_mul_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S000_I001 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1_value\nisacov.rv32m_mul_cg.cp_rs2_value\n\ + isacov.rv32m_mul_cg.cross_rs1_rs2_value\nisacov.rv32m_mul_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mul_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S000_I002 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rd_value\nisacov.rv32m_mul_cg.cp_rd_toggle" + comments: '' +- 001_MULH: !Subfeature + name: 001_MULH + tag: VP_IP000_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S001_I000 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1\nisacov.rv32m_mulh_cg.cp_rs2\n\ + isacov.rv32m_mulh_cg.cp_rd\nisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulh_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S001_I001 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1_value\nisacov.rv32m_mulh_cg.cp_rs2_value\n\ + isacov.rv32m_mulh_cg.cross_rs1_rs2_value\nisacov.rv32m_mulh_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulh_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S001_I002 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rd_value\nisacov.rv32m_mulh_cg.cp_rd_toggle" + comments: '' +- 002_MULHU: !Subfeature + name: 002_MULHU + tag: VP_IP000_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S002_I000 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1\nisacov.rv32m_mulhu_cg.cp_rs2\n\ + isacov.rv32m_mulhu_cg.cp_rd\nisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S002_I001 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1_value\nisacov.rv32m_mulhu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S002_I002 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rd_value\nisacov.rv32m_mulhu_cg.cp_rd_toggle" + comments: '' +- 003_MULHSU: !Subfeature + name: 003_MULHSU + tag: VP_IP000_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S003_I000 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1\nisacov.rv32m_mulhsu_cg.cp_rs2\n\ + isacov.rv32m_mulhsu_cg.cp_rd\nisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\n\ + isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S003_I001 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1_value\nisacov.rv32m_mulhsu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhsu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhsu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S003_I002 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rd_value\nisacov.rv32m_mulhsu_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck deleted file mode 100644 index 057f15b89..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck +++ /dev/null @@ -1,976 +0,0 @@ -(VRV32M Division Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_DIV -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_div_cg.cp_rs1\u000aisacov.rv32m_div_cg.cp_rs2\u000aisacov.rv32m_div_cg.cp_rd\u000aisacov.rv32m_div_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_div_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F007_S000_I001 -p63 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F007_S000_I002 -p78 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -a(V003 -p88 -g1 -(g29 -g3 -Ntp89 -Rp90 -(dp91 -g8 -V003 -p92 -sg23 -VVP_ISA_F007_S000_I003 -p93 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p94 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p95 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = -2^31).\u000aExercise division by zero (returns -1 ; all bits set) -p96 -sg41 -Visacov.rv32m_div_results_cg.cp_div_special_results\u000aisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow -p97 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp98 -sg15 -(lp99 -sg53 -(lp100 -sg13 -(dp101 -g56 -I0 -ssbtp102 -asVrfu_list_1 -p103 -(lp104 -sg53 -(lp105 -sg13 -(dp106 -sbtp107 -a(V001_REM -p108 -g1 -(g18 -g3 -Ntp109 -Rp110 -(dp111 -g22 -I4 -sg8 -g108 -sg23 -VVP_IP007_P001 -p112 -sg25 -(dp113 -sg12 -I1 -sg15 -(lp114 -(V000 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V000 -p119 -sg23 -VVP_ISA_F007_S001_I000 -p120 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p122 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p123 -sg41 -Visacov.rv32m_rem_cg.cp_rs1\u000aisacov.rv32m_rem_cg.cp_rs2\u000aisacov.rv32m_rem_cg.cp_rd\u000aisacov.rv32m_rem_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_rem_cg.cp_rd_rs2_hazard -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V001 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V001 -p134 -sg23 -VVP_ISA_F007_S001_I001 -p135 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p137 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p138 -sg41 -Visacov.rv32m_rem_cg.cp_rs1_value\u000aisacov.rv32m_rem_cg.cp_rs2_value\u000aisacov.rv32m_rem_cg.cross_rs1_rs2_value\u000aisacov.rv32m_rem_cg.cp_rs1_toggle \u000aisacov.rv32m_rem_cg.cp_rs2_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -a(V002 -p145 -g1 -(g29 -g3 -Ntp146 -Rp147 -(dp148 -g8 -V002 -p149 -sg23 -VVP_ISA_F007_S001_I002 -p150 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p151 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p152 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p153 -sg41 -Visacov.rv32m_rem_cg.cp_rd_value\u000aisacov.rv32m_rem_cg.cp_rd_toggle -p154 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp155 -sg15 -(lp156 -sg53 -(lp157 -sg13 -(dp158 -g56 -I0 -ssbtp159 -a(V003 -p160 -g1 -(g29 -g3 -Ntp161 -Rp162 -(dp163 -g8 -V003 -p164 -sg23 -VVP_ISA_F007_S001_I003 -p165 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p166 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p167 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = 0).\u000aExercise division by zero (returns rs1) -p168 -sg41 -Visacov.rv32m_rem_results_cg.cp_div_zero\u000aisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow -p169 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp170 -sg15 -(lp171 -sg53 -(lp172 -sg13 -(dp173 -g56 -I0 -ssbtp174 -asg103 -(lp175 -sg53 -(lp176 -sg13 -(dp177 -sbtp178 -a(V002_DIVU -p179 -g1 -(g18 -g3 -Ntp180 -Rp181 -(dp182 -g22 -I4 -sg8 -g179 -sg23 -VVP_IP007_P002 -p183 -sg25 -(dp184 -sg12 -I2 -sg15 -(lp185 -(V000 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V000 -p190 -sg23 -VVP_ISA_F007_S002_I000 -p191 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p193 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p194 -sg41 -Visacov.rv32m_divu_cg.cp_rs1\u000aisacov.rv32m_divu_cg.cp_rs2\u000aisacov.rv32m_divu_cg.cp_rd\u000aisacov.rv32m_divu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_divu_cg.cp_rd_rs2_hazard -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -a(V001 -p201 -g1 -(g29 -g3 -Ntp202 -Rp203 -(dp204 -g8 -V001 -p205 -sg23 -VVP_ISA_F007_S002_I001 -p206 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p207 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p208 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p209 -sg41 -Visacov.rv32m_divu_cg.cp_rs1_value\u000aisacov.rv32m_divu_cg.cp_rs2_value\u000aisacov.rv32m_divu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_divu_cg.cp_rs1_toggle \u000aisacov.rv32m_divu_cg.cp_rs2_toggle -p210 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp211 -sg15 -(lp212 -sg53 -(lp213 -sg13 -(dp214 -g56 -I0 -ssbtp215 -a(V002 -p216 -g1 -(g29 -g3 -Ntp217 -Rp218 -(dp219 -g8 -V002 -p220 -sg23 -VVP_ISA_F007_S002_I002 -p221 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p222 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p223 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p224 -sg41 -Visacov.rv32m_divu_cg.cp_rd_value\u000aisacov.rv32m_divu_cg.cp_rd_toggle -p225 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp226 -sg15 -(lp227 -sg53 -(lp228 -sg13 -(dp229 -g56 -I0 -ssbtp230 -a(V003 -p231 -g1 -(g29 -g3 -Ntp232 -Rp233 -(dp234 -g8 -V003 -p235 -sg23 -VVP_ISA_F007_S002_I003 -p236 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p237 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p238 -sg39 -VExercise division by zero (returns 2^32-1 ; all bits set) -p239 -sg41 -Visacov.rv32m_divu_results_cg.cp_div_zero -p240 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp241 -sg15 -(lp242 -sg53 -(lp243 -sg13 -(dp244 -g56 -I0 -ssbtp245 -asg103 -(lp246 -sg53 -(lp247 -sg13 -(dp248 -sbtp249 -a(V003_REMU -p250 -g1 -(g18 -g3 -Ntp251 -Rp252 -(dp253 -g22 -I4 -sg8 -g250 -sg23 -VVP_IP007_P003 -p254 -sg25 -(dp255 -sg12 -I3 -sg15 -(lp256 -(V000 -p257 -g1 -(g29 -g3 -Ntp258 -Rp259 -(dp260 -g8 -V000 -p261 -sg23 -VVP_ISA_F007_S003_I000 -p262 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p263 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p264 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p265 -sg41 -Visacov.rv32m_remu_cg.cp_rs1\u000aisacov.rv32m_remu_cg.cp_rs2\u000aisacov.rv32m_remu_cg.cp_rd\u000aisacov.rv32m_remu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_remu_cg.cp_rd_rs2_hazard -p266 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp267 -sg15 -(lp268 -sg53 -(lp269 -sg13 -(dp270 -g56 -I0 -ssbtp271 -a(V001 -p272 -g1 -(g29 -g3 -Ntp273 -Rp274 -(dp275 -g8 -V001 -p276 -sg23 -VVP_ISA_F007_S003_I001 -p277 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p278 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p279 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p280 -sg41 -Visacov.rv32m_remu_cg.cp_rs1_value\u000aisacov.rv32m_remu_cg.cp_rs2_value\u000aisacov.rv32m_remu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_remu_cg.cp_rs1_toggle \u000aisacov.rv32m_remu_cg.cp_rs2_toggle -p281 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp282 -sg15 -(lp283 -sg53 -(lp284 -sg13 -(dp285 -g56 -I0 -ssbtp286 -a(V002 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V002 -p291 -sg23 -VVP_ISA_F007_S003_I002 -p292 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p293 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p294 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p295 -sg41 -Visacov.rv32m_remu_cg.cp_rd_value\u000aisacov.rv32m_remu_cg.cp_rd_toggle -p296 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp297 -sg15 -(lp298 -sg53 -(lp299 -sg13 -(dp300 -g56 -I0 -ssbtp301 -a(V003 -p302 -g1 -(g29 -g3 -Ntp303 -Rp304 -(dp305 -g8 -V003 -p306 -sg23 -VVP_ISA_F007_S003_I003 -p307 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p308 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p309 -sg39 -VExercise division by zero (returns rs1) -p310 -sg41 -Visacov.rv32m_remu_results_cg.cp_div_zero -p311 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp312 -sg15 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -g56 -I0 -ssbtp316 -asg103 -(lp317 -sg53 -(lp318 -sg13 -(dp319 -sbtp320 -asVrfu_list_0 -p321 -(lp322 -sg103 -(lp323 -sVvptool_gitrev -p324 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p325 -sVio_fmt_gitrev -p326 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p327 -sVconfig_gitrev -p328 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p329 -sVymlcfg_gitrev -p330 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p331 -sbtp332 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml new file mode 100644 index 000000000..f507c377c --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -0,0 +1,350 @@ +!Feature +next_elt_id: 4 +name: RV32M Division Operations +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_DIV: !Subfeature + name: 000_DIV + tag: VP_IP007_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S000_I000 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\ + isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S000_I001 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S000_I002 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S000_I003 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 001_REM: !Subfeature + name: 001_REM + tag: VP_IP007_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S001_I000 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\ + isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S001_I001 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\ + isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_rem_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S001_I002 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S001_I003 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = 0).\nExercise division by zero (returns rs1)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 002_DIVU: !Subfeature + name: 002_DIVU + tag: VP_IP007_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S002_I000 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\ + isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S002_I001 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\ + isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_divu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S002_I002 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S002_I003 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero + comments: '' +- 003_REMU: !Subfeature + name: 003_REMU + tag: VP_IP007_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S003_I000 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\ + isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S003_I001 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\ + isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_remu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S003_I002 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S003_I003 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Exercise division by zero (returns rs1) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck deleted file mode 100644 index 2844a13db..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck +++ /dev/null @@ -1,520 +0,0 @@ -(VRV32A Load-Reserved/Store-Conditional Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LR.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F008_S000_I002 -p76 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p78 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F008_S000_I003 -p90 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exceptio -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_SC.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP008_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F008_S001_I000 -p116 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p118 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F008_S001_I001 -p130 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F008_S001_I002 -p144 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p146 -sg39 -VOutput result:\u000a\u000ard is either zero or non-zero to indicate success or failure, respectively -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F008_S001_I003 -p158 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -asVrfu_list_0 -p171 -(lp172 -sg99 -(lp173 -sVvptool_gitrev -p174 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p175 -sVio_fmt_gitrev -p176 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p177 -sVconfig_gitrev -p178 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p179 -sVymlcfg_gitrev -p180 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p181 -sbtp182 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml new file mode 100644 index 000000000..11e6f403b --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 2 +name: RV32A Load-Reserved/Store-Conditional Instructions +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_LR.W: !Subfeature + name: 000_LR.W + tag: VP_IP008_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F008_S000_I000 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F008_S000_I001 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F008_S000_I002 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F008_S000_I003 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exceptio" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_SC.W: !Subfeature + name: 001_SC.W + tag: VP_IP008_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F008_S001_I000 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used\nAll possible register combinations where rs2\ + \ == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F008_S001_I001 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F008_S001_I002 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd is either zero or non-zero to indicate\ + \ success or failure, respectively" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F008_S001_I003 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck deleted file mode 100644 index 09577a56f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck +++ /dev/null @@ -1,2059 +0,0 @@ -(VRV32A Atomic Memory Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I9 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_AMOSWAP.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p78 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F009_S000_I003 -p90 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_AMOADD.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP009_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F009_S001_I000 -p116 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p118 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F009_S001_I001 -p130 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F009_S001_I002 -p144 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p146 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F009_S001_I003 -p158 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -a(V002_AMOAND.W -p171 -g1 -(g18 -g3 -Ntp172 -Rp173 -(dp174 -g22 -I4 -sg8 -g171 -sg23 -VVP_IP009_P002 -p175 -sg25 -(dp176 -sg12 -I2 -sg15 -(lp177 -(V000 -p178 -g1 -(g29 -g3 -Ntp179 -Rp180 -(dp181 -g8 -V000 -p182 -sg23 -VVP_ISA_F009_S002_I000 -p183 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p184 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p185 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p186 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp187 -sg15 -(lp188 -sg52 -(lp189 -sg13 -(dp190 -g55 -I0 -ssbtp191 -a(V001 -p192 -g1 -(g29 -g3 -Ntp193 -Rp194 -(dp195 -g8 -V001 -p196 -sg23 -VVP_ISA_F009_S002_I001 -p197 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p198 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p199 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p200 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp201 -sg15 -(lp202 -sg52 -(lp203 -sg13 -(dp204 -g55 -I0 -ssbtp205 -a(V002 -p206 -g1 -(g29 -g3 -Ntp207 -Rp208 -(dp209 -g8 -V002 -p210 -sg23 -VVP_ISA_F009_S002_I002 -p211 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p212 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p213 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p214 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp215 -sg15 -(lp216 -sg52 -(lp217 -sg13 -(dp218 -g55 -I0 -ssbtp219 -a(V003 -p220 -g1 -(g29 -g3 -Ntp221 -Rp222 -(dp223 -g8 -V003 -p224 -sg23 -VVP_ISA_F009_S002_I003 -p225 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p226 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p227 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p228 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp229 -sg15 -(lp230 -sg52 -(lp231 -sg13 -(dp232 -g55 -I0 -ssbtp233 -asg99 -(lp234 -sg52 -(lp235 -sg13 -(dp236 -sbtp237 -a(V003_AMOOR.W -p238 -g1 -(g18 -g3 -Ntp239 -Rp240 -(dp241 -g22 -I4 -sg8 -g238 -sg23 -VVP_IP009_P003 -p242 -sg25 -(dp243 -sg12 -I3 -sg15 -(lp244 -(V000 -p245 -g1 -(g29 -g3 -Ntp246 -Rp247 -(dp248 -g8 -V000 -p249 -sg23 -VVP_ISA_F009_S003_I000 -p250 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p251 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p252 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p253 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp254 -sg15 -(lp255 -sg52 -(lp256 -sg13 -(dp257 -g55 -I0 -ssbtp258 -a(V001 -p259 -g1 -(g29 -g3 -Ntp260 -Rp261 -(dp262 -g8 -V001 -p263 -sg23 -VVP_ISA_F009_S003_I001 -p264 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p265 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p266 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p267 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp268 -sg15 -(lp269 -sg52 -(lp270 -sg13 -(dp271 -g55 -I0 -ssbtp272 -a(V002 -p273 -g1 -(g29 -g3 -Ntp274 -Rp275 -(dp276 -g8 -V002 -p277 -sg23 -VVP_ISA_F009_S003_I002 -p278 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p279 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p280 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p281 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp282 -sg15 -(lp283 -sg52 -(lp284 -sg13 -(dp285 -g55 -I0 -ssbtp286 -a(V003 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V003 -p291 -sg23 -VVP_ISA_F009_S003_I003 -p292 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p293 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p294 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p295 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp296 -sg15 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -g55 -I0 -ssbtp300 -asg99 -(lp301 -sg52 -(lp302 -sg13 -(dp303 -sbtp304 -a(V004_AMOXOR.W -p305 -g1 -(g18 -g3 -Ntp306 -Rp307 -(dp308 -g22 -I4 -sg8 -g305 -sg23 -VVP_IP009_P004 -p309 -sg25 -(dp310 -sg12 -I4 -sg15 -(lp311 -(V000 -p312 -g1 -(g29 -g3 -Ntp313 -Rp314 -(dp315 -g8 -V000 -p316 -sg23 -VVP_ISA_F009_S004_I000 -p317 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p318 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p319 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p320 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp321 -sg15 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -g55 -I0 -ssbtp325 -a(V001 -p326 -g1 -(g29 -g3 -Ntp327 -Rp328 -(dp329 -g8 -V001 -p330 -sg23 -VVP_ISA_F009_S004_I001 -p331 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p332 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p333 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p334 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp335 -sg15 -(lp336 -sg52 -(lp337 -sg13 -(dp338 -g55 -I0 -ssbtp339 -a(V002 -p340 -g1 -(g29 -g3 -Ntp341 -Rp342 -(dp343 -g8 -V002 -p344 -sg23 -VVP_ISA_F009_S004_I002 -p345 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p346 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p347 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p348 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp349 -sg15 -(lp350 -sg52 -(lp351 -sg13 -(dp352 -g55 -I0 -ssbtp353 -a(V003 -p354 -g1 -(g29 -g3 -Ntp355 -Rp356 -(dp357 -g8 -V003 -p358 -sg23 -VVP_ISA_F009_S004_I003 -p359 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p360 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p361 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p362 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp363 -sg15 -(lp364 -sg52 -(lp365 -sg13 -(dp366 -g55 -I0 -ssbtp367 -asg99 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -sbtp371 -a(V005_AMOMAX.W -p372 -g1 -(g18 -g3 -Ntp373 -Rp374 -(dp375 -g22 -I4 -sg8 -g372 -sg23 -VVP_IP009_P005 -p376 -sg25 -(dp377 -sg12 -I5 -sg15 -(lp378 -(V000 -p379 -g1 -(g29 -g3 -Ntp380 -Rp381 -(dp382 -g8 -V000 -p383 -sg23 -VVP_ISA_F009_S005_I000 -p384 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p385 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p386 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p387 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp388 -sg15 -(lp389 -sg52 -(lp390 -sg13 -(dp391 -g55 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F009_S005_I001 -p398 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p399 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p400 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p401 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp402 -sg15 -(lp403 -sg52 -(lp404 -sg13 -(dp405 -g55 -I0 -ssbtp406 -a(V002 -p407 -g1 -(g29 -g3 -Ntp408 -Rp409 -(dp410 -g8 -g407 -sg23 -VVP_ISA_F009_S005_I002 -p411 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p412 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p413 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p414 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp415 -sg15 -(lp416 -sg52 -(lp417 -sg13 -(dp418 -g55 -I0 -ssbtp419 -a(V003 -p420 -g1 -(g29 -g3 -Ntp421 -Rp422 -(dp423 -g8 -V003 -p424 -sg23 -VVP_ISA_F009_S005_I003 -p425 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p426 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p427 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p428 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp429 -sg15 -(lp430 -sg52 -(lp431 -sg13 -(dp432 -g55 -I0 -ssbtp433 -asg99 -(lp434 -sg52 -(lp435 -sg13 -(dp436 -sbtp437 -a(V006_AMOMAXU.W -p438 -g1 -(g18 -g3 -Ntp439 -Rp440 -(dp441 -g22 -I4 -sg8 -g438 -sg23 -VVP_IP009_P006 -p442 -sg25 -(dp443 -sg12 -I6 -sg15 -(lp444 -(V000 -p445 -g1 -(g29 -g3 -Ntp446 -Rp447 -(dp448 -g8 -V000 -p449 -sg23 -VVP_ISA_F009_S006_I000 -p450 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p451 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p452 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p453 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp454 -sg15 -(lp455 -sg52 -(lp456 -sg13 -(dp457 -g55 -I0 -ssbtp458 -a(V001 -p459 -g1 -(g29 -g3 -Ntp460 -Rp461 -(dp462 -g8 -V001 -p463 -sg23 -VVP_ISA_F009_S006_I001 -p464 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p465 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p466 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p467 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp468 -sg15 -(lp469 -sg52 -(lp470 -sg13 -(dp471 -g55 -I0 -ssbtp472 -a(V002 -p473 -g1 -(g29 -g3 -Ntp474 -Rp475 -(dp476 -g8 -V002 -p477 -sg23 -VVP_ISA_F009_S006_I002 -p478 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p479 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p480 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p481 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp482 -sg15 -(lp483 -sg52 -(lp484 -sg13 -(dp485 -g55 -I0 -ssbtp486 -a(V003 -p487 -g1 -(g29 -g3 -Ntp488 -Rp489 -(dp490 -g8 -V003 -p491 -sg23 -VVP_ISA_F009_S006_I003 -p492 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p493 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p494 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p495 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp496 -sg15 -(lp497 -sg52 -(lp498 -sg13 -(dp499 -g55 -I0 -ssbtp500 -asg99 -(lp501 -sg52 -(lp502 -sg13 -(dp503 -sbtp504 -a(V007_AMOMIN.W -p505 -g1 -(g18 -g3 -Ntp506 -Rp507 -(dp508 -g22 -I4 -sg8 -g505 -sg23 -VVP_IP009_P007 -p509 -sg25 -(dp510 -sg12 -I7 -sg15 -(lp511 -(V000 -p512 -g1 -(g29 -g3 -Ntp513 -Rp514 -(dp515 -g8 -V000 -p516 -sg23 -VVP_ISA_F009_S007_I000 -p517 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p518 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p519 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p520 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp521 -sg15 -(lp522 -sg52 -(lp523 -sg13 -(dp524 -g55 -I0 -ssbtp525 -a(V001 -p526 -g1 -(g29 -g3 -Ntp527 -Rp528 -(dp529 -g8 -V001 -p530 -sg23 -VVP_ISA_F009_S007_I001 -p531 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p532 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p533 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p534 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp535 -sg15 -(lp536 -sg52 -(lp537 -sg13 -(dp538 -g55 -I0 -ssbtp539 -a(V002 -p540 -g1 -(g29 -g3 -Ntp541 -Rp542 -(dp543 -g8 -V002 -p544 -sg23 -VVP_ISA_F009_S007_I002 -p545 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p546 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p547 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p548 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp549 -sg15 -(lp550 -sg52 -(lp551 -sg13 -(dp552 -g55 -I0 -ssbtp553 -a(V003 -p554 -g1 -(g29 -g3 -Ntp555 -Rp556 -(dp557 -g8 -V003 -p558 -sg23 -VVP_ISA_F009_S007_I003 -p559 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p560 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p561 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p562 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp563 -sg15 -(lp564 -sg52 -(lp565 -sg13 -(dp566 -g55 -I0 -ssbtp567 -asg99 -(lp568 -sg52 -(lp569 -sg13 -(dp570 -sbtp571 -a(V008_AMOMINU.W -p572 -g1 -(g18 -g3 -Ntp573 -Rp574 -(dp575 -g22 -I4 -sg8 -g572 -sg23 -VVP_IP009_P008 -p576 -sg25 -(dp577 -sg12 -I8 -sg15 -(lp578 -(V000 -p579 -g1 -(g29 -g3 -Ntp580 -Rp581 -(dp582 -g8 -V000 -p583 -sg23 -VVP_ISA_F009_S008_I000 -p584 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p585 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p586 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p587 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp588 -sg15 -(lp589 -sg52 -(lp590 -sg13 -(dp591 -g55 -I0 -ssbtp592 -a(V001 -p593 -g1 -(g29 -g3 -Ntp594 -Rp595 -(dp596 -g8 -V001 -p597 -sg23 -VVP_ISA_F009_S008_I001 -p598 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p599 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p600 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p601 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp602 -sg15 -(lp603 -sg52 -(lp604 -sg13 -(dp605 -g55 -I0 -ssbtp606 -a(V002 -p607 -g1 -(g29 -g3 -Ntp608 -Rp609 -(dp610 -g8 -V002 -p611 -sg23 -VVP_ISA_F009_S008_I002 -p612 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p613 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p614 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p615 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp616 -sg15 -(lp617 -sg52 -(lp618 -sg13 -(dp619 -g55 -I0 -ssbtp620 -a(V003 -p621 -g1 -(g29 -g3 -Ntp622 -Rp623 -(dp624 -g8 -V003 -p625 -sg23 -VVP_ISA_F009_S008_I003 -p626 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p627 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p628 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p629 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp630 -sg15 -(lp631 -sg52 -(lp632 -sg13 -(dp633 -g55 -I0 -ssbtp634 -asg99 -(lp635 -sg52 -(lp636 -sg13 -(dp637 -sbtp638 -asVrfu_list_0 -p639 -(lp640 -sg99 -(lp641 -sVvptool_gitrev -p642 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p643 -sVio_fmt_gitrev -p644 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p645 -sVconfig_gitrev -p646 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p647 -sVymlcfg_gitrev -p648 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p649 -sbtp650 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml new file mode 100644 index 000000000..9799fa6df --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -0,0 +1,788 @@ +!Feature +next_elt_id: 9 +name: RV32A Atomic Memory Operations +id: 9 +display_order: 9 +subfeatures: !!omap +- 000_AMOSWAP.W: !Subfeature + name: 000_AMOSWAP.W + tag: VP_IP009_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S000_I000 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S000_I001 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S000_I002 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S000_I003 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_AMOADD.W: !Subfeature + name: 001_AMOADD.W + tag: VP_IP009_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S001_I000 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S001_I001 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S001_I002 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S001_I003 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_AMOAND.W: !Subfeature + name: 002_AMOAND.W + tag: VP_IP009_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S002_I000 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S002_I001 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S002_I002 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S002_I003 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_AMOOR.W: !Subfeature + name: 003_AMOOR.W + tag: VP_IP009_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S003_I000 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S003_I001 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S003_I002 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S003_I003 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_AMOXOR.W: !Subfeature + name: 004_AMOXOR.W + tag: VP_IP009_P004 + next_elt_id: 4 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S004_I000 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S004_I001 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S004_I002 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S004_I003 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_AMOMAX.W: !Subfeature + name: 005_AMOMAX.W + tag: VP_IP009_P005 + next_elt_id: 4 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S005_I000 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S005_I001 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S005_I002 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S005_I003 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AMOMAXU.W: !Subfeature + name: 006_AMOMAXU.W + tag: VP_IP009_P006 + next_elt_id: 4 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S006_I000 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S006_I001 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S006_I002 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S006_I003 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AMOMIN.W: !Subfeature + name: 007_AMOMIN.W + tag: VP_IP009_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S007_I000 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S007_I001 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S007_I002 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S007_I003 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_AMOMINU.W: !Subfeature + name: 008_AMOMINU.W + tag: VP_IP009_P008 + next_elt_id: 4 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S008_I000 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S008_I001 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S008_I002 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S008_I003 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck deleted file mode 100644 index 997752667..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck +++ /dev/null @@ -1,2592 +0,0 @@ -(VRV32C Integer Computational Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I16 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.5 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll bits of imm[5:0] are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p64 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_C.LUI -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP008_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F008_S001_I000 -p88 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p90 -sg39 -VInput operands:\u000a\u000aAll bits of imm[17:12] are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F008_S001_I001 -p102 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p104 -sg39 -VOutput result:\u000a\u000aAll bits of rd[31:12] are toggled -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_C.ADDI -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I3 -sg8 -g115 -sg23 -VVP_IP008_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F008_S002_I000 -p127 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F008_S002_I001 -p141 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p143 -sg39 -VInput operands:\u000a\u000aAll inputs bits of rd before instruction execution are toggled\u000aAll bits of nzimm are toggled -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V002 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V002 -p154 -sg23 -VVP_ISA_F008_S002_I002 -p155 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p157 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -asg71 -(lp164 -sg52 -(lp165 -sg13 -(dp166 -sbtp167 -a(V003_C.ADDI16SP -p168 -g1 -(g18 -g3 -Ntp169 -Rp170 -(dp171 -g22 -I3 -sg8 -g168 -sg23 -VVP_IP008_P003 -p172 -sg25 -(dp173 -sg12 -I3 -sg15 -(lp174 -(V000 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V000 -p179 -sg23 -VVP_ISA_F008_S003_I000 -p180 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p182 -sg39 -VInput operands:\u000a\u000a+ve and -ve values of nzimm are used\u000aAll bits of nzimm[9:4] are toggled\u000aAll bits of x2 before instruction execution are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -a(V001 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V001 -p193 -sg23 -VVP_ISA_F008_S003_I001 -p194 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p196 -sg39 -VOutput result:\u000a\u000aAll bits of x2 are toggled -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -asg71 -(lp203 -sg52 -(lp204 -sg13 -(dp205 -sbtp206 -a(V004_C.ADDI4SPN -p207 -g1 -(g18 -g3 -Ntp208 -Rp209 -(dp210 -g22 -I3 -sg8 -g207 -sg23 -VVP_IP008_P004 -p211 -sg25 -(dp212 -sg12 -I4 -sg15 -(lp213 -(V000 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V000 -p218 -sg23 -VVP_ISA_F008_S004_I000 -p219 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p221 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V001 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V001 -p232 -sg23 -VVP_ISA_F008_S004_I001 -p233 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p235 -sg39 -VInput operands:\u000a\u000aAll bits of nzuimm[9:2] are toggled\u000aAll bits of x2 before instruction execution are toggled -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F008_S004_I002 -p247 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p248 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p249 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p250 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp251 -sg15 -(lp252 -sg52 -(lp253 -sg13 -(dp254 -g55 -I0 -ssbtp255 -asg71 -(lp256 -sg52 -(lp257 -sg13 -(dp258 -sbtp259 -a(V005_C.SLLI -p260 -g1 -(g18 -g3 -Ntp261 -Rp262 -(dp263 -g22 -I3 -sg8 -g260 -sg23 -VVP_IP008_P005 -p264 -sg25 -(dp265 -sg12 -I5 -sg15 -(lp266 -(V000 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V000 -p271 -sg23 -VVP_ISA_F008_S005_I000 -p272 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p274 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F008_S005_I001 -p286 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p288 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -a(V002 -p295 -g1 -(g29 -g3 -Ntp296 -Rp297 -(dp298 -g8 -V002 -p299 -sg23 -VVP_ISA_F008_S005_I002 -p300 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p301 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p302 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p303 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp304 -sg15 -(lp305 -sg52 -(lp306 -sg13 -(dp307 -g55 -I0 -ssbtp308 -asg71 -(lp309 -sg52 -(lp310 -sg13 -(dp311 -sbtp312 -a(V006_C.SRLI -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP008_P006 -p317 -sg25 -(dp318 -sg12 -I6 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F008_S006_I000 -p325 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p326 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p328 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp329 -sg15 -(lp330 -sg52 -(lp331 -sg13 -(dp332 -g55 -I0 -ssbtp333 -a(V001 -p334 -g1 -(g29 -g3 -Ntp335 -Rp336 -(dp337 -g8 -V001 -p338 -sg23 -VVP_ISA_F008_S006_I001 -p339 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p340 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p341 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p342 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp343 -sg15 -(lp344 -sg52 -(lp345 -sg13 -(dp346 -g55 -I0 -ssbtp347 -a(V002 -p348 -g1 -(g29 -g3 -Ntp349 -Rp350 -(dp351 -g8 -V002 -p352 -sg23 -VVP_ISA_F008_S006_I002 -p353 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p354 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p355 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p356 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp357 -sg15 -(lp358 -sg52 -(lp359 -sg13 -(dp360 -g55 -I0 -ssbtp361 -asg71 -(lp362 -sg52 -(lp363 -sg13 -(dp364 -sbtp365 -a(V007_C.SRAI -p366 -g1 -(g18 -g3 -Ntp367 -Rp368 -(dp369 -g22 -I3 -sg8 -g366 -sg23 -VVP_IP008_P007 -p370 -sg25 -(dp371 -sg12 -I7 -sg15 -(lp372 -(V000 -p373 -g1 -(g29 -g3 -Ntp374 -Rp375 -(dp376 -g8 -V000 -p377 -sg23 -VVP_ISA_F008_S007_I000 -p378 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p379 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p380 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p381 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp382 -sg15 -(lp383 -sg52 -(lp384 -sg13 -(dp385 -g55 -I0 -ssbtp386 -a(V001 -p387 -g1 -(g29 -g3 -Ntp388 -Rp389 -(dp390 -g8 -V001 -p391 -sg23 -VVP_ISA_F008_S007_I001 -p392 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p393 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p394 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of rd` are used\u000aAll bits of rd` before instruction execution are toggled -p395 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp396 -sg15 -(lp397 -sg52 -(lp398 -sg13 -(dp399 -g55 -I0 -ssbtp400 -a(V002 -p401 -g1 -(g29 -g3 -Ntp402 -Rp403 -(dp404 -g8 -V002 -p405 -sg23 -VVP_ISA_F008_S007_I002 -p406 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p407 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p408 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p409 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp410 -sg15 -(lp411 -sg52 -(lp412 -sg13 -(dp413 -g55 -I0 -ssbtp414 -asg71 -(lp415 -sg52 -(lp416 -sg13 -(dp417 -sbtp418 -a(V008_C.ANDI -p419 -g1 -(g18 -g3 -Ntp420 -Rp421 -(dp422 -g22 -I3 -sg8 -g419 -sg23 -VVP_IP008_P008 -p423 -sg25 -(dp424 -sg12 -I8 -sg15 -(lp425 -(V000 -p426 -g1 -(g29 -g3 -Ntp427 -Rp428 -(dp429 -g8 -V000 -p430 -sg23 -VVP_ISA_F008_S008_I000 -p431 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p432 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p433 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p434 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp435 -sg15 -(lp436 -sg52 -(lp437 -sg13 -(dp438 -g55 -I0 -ssbtp439 -a(V001 -p440 -g1 -(g29 -g3 -Ntp441 -Rp442 -(dp443 -g8 -V001 -p444 -sg23 -VVP_ISA_F008_S008_I001 -p445 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p446 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p447 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of imm are used\u000aAll bits of rd` before instruction execution are toggled -p448 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp449 -sg15 -(lp450 -sg52 -(lp451 -sg13 -(dp452 -g55 -I0 -ssbtp453 -a(V002 -p454 -g1 -(g29 -g3 -Ntp455 -Rp456 -(dp457 -g8 -V002 -p458 -sg23 -VVP_ISA_F008_S008_I002 -p459 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p460 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p461 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p462 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp463 -sg15 -(lp464 -sg52 -(lp465 -sg13 -(dp466 -g55 -I0 -ssbtp467 -asg71 -(lp468 -sg52 -(lp469 -sg13 -(dp470 -sbtp471 -a(V009_C.MV -p472 -g1 -(g18 -g3 -Ntp473 -Rp474 -(dp475 -g22 -I3 -sg8 -g472 -sg23 -VVP_IP008_P009 -p476 -sg25 -(dp477 -sg12 -I9 -sg15 -(lp478 -(V000 -p479 -g1 -(g29 -g3 -Ntp480 -Rp481 -(dp482 -g8 -V000 -p483 -sg23 -VVP_ISA_F008_S009_I000 -p484 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p485 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p486 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs2 == rd are used -p487 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp488 -sg15 -(lp489 -sg52 -(lp490 -sg13 -(dp491 -g55 -I0 -ssbtp492 -a(V001 -p493 -g1 -(g29 -g3 -Ntp494 -Rp495 -(dp496 -g8 -V001 -p497 -sg23 -VVP_ISA_F008_S009_I001 -p498 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p499 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p500 -sg39 -VInput operands:\u000a\u000aAll bits of rs2 are toggled -p501 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp502 -sg15 -(lp503 -sg52 -(lp504 -sg13 -(dp505 -g55 -I0 -ssbtp506 -a(V002 -p507 -g1 -(g29 -g3 -Ntp508 -Rp509 -(dp510 -g8 -V002 -p511 -sg23 -VVP_ISA_F008_S009_I002 -p512 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p513 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p514 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p515 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp516 -sg15 -(lp517 -sg52 -(lp518 -sg13 -(dp519 -g55 -I0 -ssbtp520 -asg71 -(lp521 -sg52 -(lp522 -sg13 -(dp523 -sbtp524 -a(V010_C.ADD -p525 -g1 -(g18 -g3 -Ntp526 -Rp527 -(dp528 -g22 -I3 -sg8 -g525 -sg23 -VVP_IP008_P010 -p529 -sg25 -(dp530 -sg12 -I10 -sg15 -(lp531 -(V000 -p532 -g1 -(g29 -g3 -Ntp533 -Rp534 -(dp535 -g8 -V000 -p536 -sg23 -VVP_ISA_F008_S010_I000 -p537 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p538 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p539 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p540 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp541 -sg15 -(lp542 -sg52 -(lp543 -sg13 -(dp544 -g55 -I0 -ssbtp545 -a(V001 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V001 -p550 -sg23 -VVP_ISA_F008_S010_I001 -p551 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p552 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p553 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2 are used\u000a+ve,-ve, and zero values of rdrs1 are used\u000aAll bits of rs2 are toggled\u000aAll bits of rd before instruction execution are toggled -p554 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp555 -sg15 -(lp556 -sg52 -(lp557 -sg13 -(dp558 -g55 -I0 -ssbtp559 -a(V002 -p560 -g1 -(g29 -g3 -Ntp561 -Rp562 -(dp563 -g8 -V002 -p564 -sg23 -VVP_ISA_F008_S010_I002 -p565 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p566 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p567 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled\u000a+ve,-ve and zero values of rd are used -p568 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp569 -sg15 -(lp570 -sg52 -(lp571 -sg13 -(dp572 -g55 -I0 -ssbtp573 -asg71 -(lp574 -sg52 -(lp575 -sg13 -(dp576 -sbtp577 -a(V011_C.AND -p578 -g1 -(g18 -g3 -Ntp579 -Rp580 -(dp581 -g22 -I3 -sg8 -g578 -sg23 -VVP_IP008_P011 -p582 -sg25 -(dp583 -sg12 -I11 -sg15 -(lp584 -(V000 -p585 -g1 -(g29 -g3 -Ntp586 -Rp587 -(dp588 -g8 -V000 -p589 -sg23 -VVP_ISA_F008_S011_I000 -p590 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p591 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p592 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p593 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp594 -sg15 -(lp595 -sg52 -(lp596 -sg13 -(dp597 -g55 -I0 -ssbtp598 -a(V001 -p599 -g1 -(g29 -g3 -Ntp600 -Rp601 -(dp602 -g8 -V001 -p603 -sg23 -VVP_ISA_F008_S011_I001 -p604 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p605 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p606 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p607 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp608 -sg15 -(lp609 -sg52 -(lp610 -sg13 -(dp611 -g55 -I0 -ssbtp612 -a(V002 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V002 -p617 -sg23 -VVP_ISA_F008_S011_I002 -p618 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p619 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p620 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p621 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp622 -sg15 -(lp623 -sg52 -(lp624 -sg13 -(dp625 -g55 -I0 -ssbtp626 -asg71 -(lp627 -sg52 -(lp628 -sg13 -(dp629 -sbtp630 -a(V012_C.OR -p631 -g1 -(g18 -g3 -Ntp632 -Rp633 -(dp634 -g22 -I3 -sg8 -g631 -sg23 -VVP_IP008_P012 -p635 -sg25 -(dp636 -sg12 -I12 -sg15 -(lp637 -(V000 -p638 -g1 -(g29 -g3 -Ntp639 -Rp640 -(dp641 -g8 -V000 -p642 -sg23 -VVP_ISA_F008_S012_I000 -p643 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p644 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p645 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p646 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp647 -sg15 -(lp648 -sg52 -(lp649 -sg13 -(dp650 -g55 -I0 -ssbtp651 -a(V001 -p652 -g1 -(g29 -g3 -Ntp653 -Rp654 -(dp655 -g8 -V001 -p656 -sg23 -VVP_ISA_F008_S012_I001 -p657 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p658 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p659 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p660 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp661 -sg15 -(lp662 -sg52 -(lp663 -sg13 -(dp664 -g55 -I0 -ssbtp665 -a(V002 -p666 -g1 -(g29 -g3 -Ntp667 -Rp668 -(dp669 -g8 -V002 -p670 -sg23 -VVP_ISA_F008_S012_I002 -p671 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p672 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p673 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p674 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp675 -sg15 -(lp676 -sg52 -(lp677 -sg13 -(dp678 -g55 -I0 -ssbtp679 -asg71 -(lp680 -sg52 -(lp681 -sg13 -(dp682 -sbtp683 -a(V013_C.XOR -p684 -g1 -(g18 -g3 -Ntp685 -Rp686 -(dp687 -g22 -I3 -sg8 -g684 -sg23 -VVP_IP008_P013 -p688 -sg25 -(dp689 -sg12 -I13 -sg15 -(lp690 -(V000 -p691 -g1 -(g29 -g3 -Ntp692 -Rp693 -(dp694 -g8 -V000 -p695 -sg23 -VVP_ISA_F008_S013_I000 -p696 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p697 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p698 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p699 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp700 -sg15 -(lp701 -sg52 -(lp702 -sg13 -(dp703 -g55 -I0 -ssbtp704 -a(V001 -p705 -g1 -(g29 -g3 -Ntp706 -Rp707 -(dp708 -g8 -V001 -p709 -sg23 -VVP_ISA_F008_S013_I001 -p710 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p711 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p712 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p713 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp714 -sg15 -(lp715 -sg52 -(lp716 -sg13 -(dp717 -g55 -I0 -ssbtp718 -a(V002 -p719 -g1 -(g29 -g3 -Ntp720 -Rp721 -(dp722 -g8 -V002 -p723 -sg23 -VVP_ISA_F008_S013_I002 -p724 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p725 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p726 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p727 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp728 -sg15 -(lp729 -sg52 -(lp730 -sg13 -(dp731 -g55 -I0 -ssbtp732 -asg71 -(lp733 -sg52 -(lp734 -sg13 -(dp735 -sbtp736 -a(V014_C.SUB -p737 -g1 -(g18 -g3 -Ntp738 -Rp739 -(dp740 -g22 -I3 -sg8 -g737 -sg23 -VVP_IP008_P014 -p741 -sg25 -(dp742 -sg12 -I14 -sg15 -(lp743 -(V000 -p744 -g1 -(g29 -g3 -Ntp745 -Rp746 -(dp747 -g8 -V000 -p748 -sg23 -VVP_ISA_F008_S014_I000 -p749 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p750 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p751 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p752 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp753 -sg15 -(lp754 -sg52 -(lp755 -sg13 -(dp756 -g55 -I0 -ssbtp757 -a(V001 -p758 -g1 -(g29 -g3 -Ntp759 -Rp760 -(dp761 -g8 -V001 -p762 -sg23 -VVP_ISA_F008_S014_I001 -p763 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p764 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p765 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2` are used\u000a+ve, -ve, and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p766 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp767 -sg15 -(lp768 -sg52 -(lp769 -sg13 -(dp770 -g55 -I0 -ssbtp771 -a(V002 -p772 -g1 -(g29 -g3 -Ntp773 -Rp774 -(dp775 -g8 -V002 -p776 -sg23 -VVP_ISA_F008_S014_I002 -p777 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p778 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p779 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p780 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp781 -sg15 -(lp782 -sg52 -(lp783 -sg13 -(dp784 -g55 -I0 -ssbtp785 -asg71 -(lp786 -sg52 -(lp787 -sg13 -(dp788 -sbtp789 -a(V015_C.EBREAK -p790 -g1 -(g18 -g3 -Ntp791 -Rp792 -(dp793 -g22 -I1 -sg8 -g790 -sg23 -VVP_IP008_P015 -p794 -sg25 -(dp795 -sg12 -I15 -sg15 -(lp796 -(V000 -p797 -g1 -(g29 -g3 -Ntp798 -Rp799 -(dp800 -g8 -V000 -p801 -sg23 -VVP_ISA_F008_S015_I000 -p802 -sg35 -Vc.ebreak\u000aRaiseException(Breakpoint)\u000aExpands to ebreak. -p803 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p804 -sg39 -VInstruction executed -p805 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp806 -sg15 -(lp807 -sg52 -(lp808 -sg13 -(dp809 -g55 -I0 -ssbtp810 -asg71 -(lp811 -sg52 -(lp812 -sg13 -(dp813 -sbtp814 -asVrfu_list_0 -p815 -(lp816 -sg71 -(lp817 -sVvptool_gitrev -p818 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p819 -sVio_fmt_gitrev -p820 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p821 -sVconfig_gitrev -p822 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p823 -sVymlcfg_gitrev -p824 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p825 -sbtp826 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml new file mode 100644 index 000000000..4289289cf --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -0,0 +1,868 @@ +!Feature +next_elt_id: 16 +name: RV32C Integer Computational Instructions +id: 10 +display_order: 10 +subfeatures: !!omap +- 000_C.LI: !Subfeature + name: 000_C.LI + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S000_I000 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of imm[5:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S000_I001 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.LUI: !Subfeature + name: 001_C.LUI + tag: VP_IP008_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S001_I000 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of imm[17:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S001_I001 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd[31:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.ADDI: !Subfeature + name: 002_C.ADDI + tag: VP_IP008_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S002_I000 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S002_I001 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll inputs bits of rd before instruction\ + \ execution are toggled\nAll bits of nzimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S002_I002 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.ADDI16SP: !Subfeature + name: 003_C.ADDI16SP + tag: VP_IP008_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S003_I000 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve and -ve values of nzimm are used\nAll\ + \ bits of nzimm[9:4] are toggled\nAll bits of x2 before instruction execution\ + \ are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S003_I001 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.ADDI4SPN: !Subfeature + name: 004_C.ADDI4SPN + tag: VP_IP008_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S004_I000 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S004_I001 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of nzuimm[9:2] are toggled\nAll\ + \ bits of x2 before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S004_I002 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.SLLI: !Subfeature + name: 005_C.SLLI + tag: VP_IP008_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S005_I000 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S005_I001 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S005_I002 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_C.SRLI: !Subfeature + name: 006_C.SRLI + tag: VP_IP008_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S006_I000 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S006_I001 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S006_I002 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_C.SRAI: !Subfeature + name: 007_C.SRAI + tag: VP_IP008_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S007_I000 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S007_I001 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of rd` are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S007_I002 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_C.ANDI: !Subfeature + name: 008_C.ANDI + tag: VP_IP008_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S008_I000 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S008_I001 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of imm are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S008_I002 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_C.MV: !Subfeature + name: 009_C.MV + tag: VP_IP008_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S009_I000 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used.\n\ + All possible register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S009_I001 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S009_I002 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 010_C.ADD: !Subfeature + name: 010_C.ADD + tag: VP_IP008_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S010_I000 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S010_I001 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2 are used\n\ + +ve,-ve, and zero values of rdrs1 are used\nAll bits of rs2 are toggled\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S010_I002 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled\n+ve,-ve and zero\ + \ values of rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 011_C.AND: !Subfeature + name: 011_C.AND + tag: VP_IP008_P011 + next_elt_id: 3 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S011_I000 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S011_I001 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S011_I002 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 012_C.OR: !Subfeature + name: 012_C.OR + tag: VP_IP008_P012 + next_elt_id: 3 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S012_I000 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S012_I001 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S012_I002 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 013_C.XOR: !Subfeature + name: 013_C.XOR + tag: VP_IP008_P013 + next_elt_id: 3 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S013_I000 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S013_I001 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S013_I002 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 014_C.SUB: !Subfeature + name: 014_C.SUB + tag: VP_IP008_P014 + next_elt_id: 3 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S014_I000 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S014_I001 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2` are used\n\ + +ve, -ve, and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S014_I002 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 015_C.EBREAK: !Subfeature + name: 015_C.EBREAK + tag: VP_IP008_P015 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S015_I000 + description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck deleted file mode 100644 index e8ad3e411..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck +++ /dev/null @@ -1,920 +0,0 @@ -(VRV32C Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I11 -sVwid_order -p12 -I11 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.J -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP010_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F010_S000_I000 -p34 -sVdescription -p35 -Vc.j imm[11:1]\u000apc += sext(imm)\u000apc is calculated using signed arithmetic\u000aExpands to jal x0, imm[11:1]. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_C.JAL -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I2 -sg8 -g62 -sg23 -VVP_IP010_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_ISA_F010_S001_I000 -p74 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p75 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p76 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p77 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -a(V001 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V001 -p87 -sg23 -VVP_ISA_F010_S001_I001 -p88 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p90 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -asg57 -(lp97 -sg52 -(lp98 -sg13 -(dp99 -sbtp100 -a(V002_C.JR -p101 -g1 -(g18 -g3 -Ntp102 -Rp103 -(dp104 -g22 -I2 -sg8 -g101 -sg23 -VVP_IP010_P002 -p105 -sg25 -(dp106 -sg12 -I2 -sg15 -(lp107 -(V000 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V000 -p112 -sg23 -VVP_ISA_F010_S002_I000 -p113 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p114 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p115 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p116 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -a(V001 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V001 -p126 -sg23 -VVP_ISA_F010_S002_I001 -p127 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p129 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -asg57 -(lp136 -sg52 -(lp137 -sg13 -(dp138 -sbtp139 -a(V003_C.JALR -p140 -g1 -(g18 -g3 -Ntp141 -Rp142 -(dp143 -g22 -I3 -sg8 -g140 -sg23 -VVP_IP010_P003 -p144 -sg25 -(dp145 -sg12 -I3 -sg15 -(lp146 -(V000 -p147 -g1 -(g29 -g3 -Ntp148 -Rp149 -(dp150 -g8 -V000 -p151 -sg23 -VVP_ISA_F010_S003_I000 -p152 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p153 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p154 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p155 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp156 -sg15 -(lp157 -sg52 -(lp158 -sg13 -(dp159 -g55 -I0 -ssbtp160 -a(V001 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V001 -p165 -sg23 -VVP_ISA_F010_S003_I001 -p166 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p167 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p168 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V002 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V002 -p179 -sg23 -VVP_ISA_F010_S003_I002 -p180 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p182 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg57 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_C.BEQZ -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I3 -sg8 -g193 -sg23 -VVP_IP010_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F010_S004_I000 -p205 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p206 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F010_S004_I001 -p219 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p221 -sg39 -VInput operands:\u000a\u000aAll bits of rs1` are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V002 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V002 -p232 -sg23 -VVP_ISA_F010_S004_I002 -p233 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p235 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -asg57 -(lp242 -sg52 -(lp243 -sg13 -(dp244 -sbtp245 -a(V005_C.BNEZ -p246 -g1 -(g18 -g3 -Ntp247 -Rp248 -(dp249 -g22 -I3 -sg8 -g246 -sg23 -VVP_IP010_P005 -p250 -sg25 -(dp251 -sg12 -I5 -sg15 -(lp252 -(V000 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V000 -p257 -sg23 -VVP_ISA_F010_S005_I000 -p258 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p259 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p260 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -a(V001 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V001 -p271 -sg23 -VVP_ISA_F010_S005_I001 -p272 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p274 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V002 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V002 -p285 -sg23 -VVP_ISA_F010_S005_I002 -p286 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p288 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -asg57 -(lp295 -sg52 -(lp296 -sg13 -(dp297 -sbtp298 -asVrfu_list_0 -p299 -(lp300 -sg57 -(lp301 -sVvptool_gitrev -p302 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p303 -sVio_fmt_gitrev -p304 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p305 -sVconfig_gitrev -p306 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p307 -sVymlcfg_gitrev -p308 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p309 -sbtp310 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml new file mode 100644 index 000000000..2e9439798 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -0,0 +1,286 @@ +!Feature +next_elt_id: 6 +name: RV32C Control Transfer Instructions +id: 11 +display_order: 11 +subfeatures: !!omap +- 000_C.J: !Subfeature + name: 000_C.J + tag: VP_IP010_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S000_I000 + description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ + \ arithmetic\nExpands to jal x0, imm[11:1]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.JAL: !Subfeature + name: 001_C.JAL + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S001_I000 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S001_I001 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.JR: !Subfeature + name: 002_C.JR + tag: VP_IP010_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S002_I000 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S002_I001 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.JALR: !Subfeature + name: 003_C.JALR + tag: VP_IP010_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S003_I000 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S003_I001 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S003_I002 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.BEQZ: !Subfeature + name: 004_C.BEQZ + tag: VP_IP010_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S004_I000 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S004_I001 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S004_I002 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.BNEZ: !Subfeature + name: 005_C.BNEZ + tag: VP_IP010_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S005_I000 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S005_I001 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S005_I002 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck deleted file mode 100644 index 73c3f301f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck +++ /dev/null @@ -1,672 +0,0 @@ -(VRV32C Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I12 -sVwid_order -p12 -I12 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LWSP -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.3 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p64 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p77 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p78 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V001_C.SWSP -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I2 -sg8 -g90 -sg23 -VVP_IP009_P001 -p94 -sg25 -(dp95 -sg12 -I1 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_ISA_F009_S001_I000 -p102 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p104 -sg39 -VRegister operands:\u000a\u000aAll possible rs2 registers are used. -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V001 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V001 -p115 -sg23 -VVP_ISA_F009_S001_I001 -p116 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p117 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p118 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg85 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -a(V002_C.LW -p129 -g1 -(g18 -g3 -Ntp130 -Rp131 -(dp132 -g22 -I3 -sg8 -g129 -sg23 -VVP_IP009_P002 -p133 -sg25 -(dp134 -sg12 -I2 -sg15 -(lp135 -(V000 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V000 -p140 -sg23 -VVP_ISA_F009_S002_I000 -p141 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p143 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V001 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V001 -p154 -sg23 -VVP_ISA_F009_S002_I001 -p155 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p157 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -a(V002 -p164 -g1 -(g29 -g3 -Ntp165 -Rp166 -(dp167 -g8 -V002 -p168 -sg23 -VVP_ISA_F009_S002_I002 -p169 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p170 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p171 -sg39 -VOutput result:\u000a\u000ard` value is non-zero and zero\u000aAll bits of rd are toggled -p172 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp173 -sg15 -(lp174 -sg52 -(lp175 -sg13 -(dp176 -g55 -I0 -ssbtp177 -asg85 -(lp178 -sg52 -(lp179 -sg13 -(dp180 -sbtp181 -a(V003_C.SW -p182 -g1 -(g18 -g3 -Ntp183 -Rp184 -(dp185 -g22 -I2 -sg8 -g182 -sg23 -VVP_IP009_P003 -p186 -sg25 -(dp187 -sg12 -I3 -sg15 -(lp188 -(V000 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V000 -p193 -sg23 -VVP_ISA_F009_S003_I000 -p194 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p196 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -a(V001 -p203 -g1 -(g29 -g3 -Ntp204 -Rp205 -(dp206 -g8 -V001 -p207 -sg23 -VVP_ISA_F009_S003_I001 -p208 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p209 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p210 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled\u000aAll bits of rs2` are toggled -p211 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp212 -sg15 -(lp213 -sg52 -(lp214 -sg13 -(dp215 -g55 -I0 -ssbtp216 -asg85 -(lp217 -sg52 -(lp218 -sg13 -(dp219 -sbtp220 -asVrfu_list_0 -p221 -(lp222 -sg85 -(lp223 -sVvptool_gitrev -p224 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p225 -sVio_fmt_gitrev -p226 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p227 -sVconfig_gitrev -p228 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p229 -sVymlcfg_gitrev -p230 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p231 -sbtp232 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml new file mode 100644 index 000000000..c32098fd3 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -0,0 +1,218 @@ +!Feature +next_elt_id: 4 +name: RV32C Load and Store Instructions +id: 12 +display_order: 12 +subfeatures: !!omap +- 000_C.LWSP: !Subfeature + name: 000_C.LWSP + tag: VP_IP009_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S000_I000 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S000_I001 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F012_S000_I002 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.SWSP: !Subfeature + name: 001_C.SWSP + tag: VP_IP009_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S001_I000 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S001_I001 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.LW: !Subfeature + name: 002_C.LW + tag: VP_IP009_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S002_I000 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S002_I001 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F012_S002_I002 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd` value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.SW: !Subfeature + name: 003_C.SW + tag: VP_IP009_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S003_I000 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S003_I001 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled\nAll bits of rs2` are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck deleted file mode 100644 index acac41764..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck +++ /dev/null @@ -1,824 +0,0 @@ -(VRV32Zicsr Control and Status Register (CSR) Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I13 -sVwid_order -p12 -I13 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_CSRRW -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p36 -sVpurpose -p37 -VISA Chapter 9 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F007_S000_I001 -p62 -sg35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p63 -sg37 -VISA Chapter 9 -p64 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_CSRRS -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP007_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F007_S001_I000 -p88 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p89 -sg37 -VISA Chapter 9 -p90 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F007_S001_I001 -p102 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p103 -sg37 -VISA Chapter 9 -p104 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_CSRRC -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I2 -sg8 -g115 -sg23 -VVP_IP007_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F007_S002_I000 -p127 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p128 -sg37 -VISA Chapter 9 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F007_S002_I001 -p141 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p142 -sg37 -VISA Chapter 9 -p143 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -asg71 -(lp150 -sg52 -(lp151 -sg13 -(dp152 -sbtp153 -a(V003_CSRRWI -p154 -g1 -(g18 -g3 -Ntp155 -Rp156 -(dp157 -g22 -I2 -sg8 -g154 -sg23 -VVP_IP007_P003 -p158 -sg25 -(dp159 -sg12 -I3 -sg15 -(lp160 -(V000 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V000 -p165 -sg23 -VVP_ISA_F007_S003_I000 -p166 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p167 -sg37 -VISA Chapter 9 -p168 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V001 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V001 -p179 -sg23 -VVP_ISA_F007_S003_I001 -p180 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p181 -sg37 -VISA Chapter 9 -p182 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg71 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_CSRRSI -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I2 -sg8 -g193 -sg23 -VVP_IP007_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F007_S004_I000 -p205 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p206 -sg37 -VISA Chapter 9 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F007_S004_I001 -p219 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p220 -sg37 -VISA Chapter 9 -p221 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -asg71 -(lp228 -sg52 -(lp229 -sg13 -(dp230 -sbtp231 -a(V005_CSRRCI -p232 -g1 -(g18 -g3 -Ntp233 -Rp234 -(dp235 -g22 -I2 -sg8 -g232 -sg23 -VVP_IP007_P005 -p236 -sg25 -(dp237 -sg12 -I5 -sg15 -(lp238 -(V000 -p239 -g1 -(g29 -g3 -Ntp240 -Rp241 -(dp242 -g8 -V000 -p243 -sg23 -VVP_ISA_F007_S005_I000 -p244 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p245 -sg37 -VISA Chapter 9 -p246 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p247 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp248 -sg15 -(lp249 -sg52 -(lp250 -sg13 -(dp251 -g55 -I0 -ssbtp252 -a(V001 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V001 -p257 -sg23 -VVP_ISA_F007_S005_I001 -p258 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p259 -sg37 -VISA Chapter 9 -p260 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -asg71 -(lp267 -sg52 -(lp268 -sg13 -(dp269 -sbtp270 -asVrfu_list_0 -p271 -(lp272 -sg71 -(lp273 -sVvptool_gitrev -p274 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p275 -sVio_fmt_gitrev -p276 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p277 -sVconfig_gitrev -p278 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p279 -sVymlcfg_gitrev -p280 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p281 -sbtp282 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml new file mode 100644 index 000000000..d79d48918 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -0,0 +1,263 @@ +!Feature +next_elt_id: 6 +name: RV32Zicsr Control and Status Register (CSR) Instructions +id: 13 +display_order: 13 +subfeatures: !!omap +- 000_CSRRW: !Subfeature + name: 000_CSRRW + tag: VP_IP007_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S000_I000 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S000_I001 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_CSRRS: !Subfeature + name: 001_CSRRS + tag: VP_IP007_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S001_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S001_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_CSRRC: !Subfeature + name: 002_CSRRC + tag: VP_IP007_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S002_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S002_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSRRWI: !Subfeature + name: 003_CSRRWI + tag: VP_IP007_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S003_I000 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S003_I001 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_CSRRSI: !Subfeature + name: 004_CSRRSI + tag: VP_IP007_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S004_I000 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S004_I001 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_CSRRCI: !Subfeature + name: 005_CSRRCI + tag: VP_IP007_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S005_I000 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S005_I001 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck deleted file mode 100644 index d3b9272ec..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32Zifencei Instruction-Fetch Fence -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I14 -sVwid_order -p12 -I14 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE.I -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F006_S000_I000 -p34 -sVdescription -p35 -VFence.I instruction executed\u000aImplementation is core-specific -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 3 -p38 -sVverif_goals -p39 -VFence.I instruction is executed -p40 -sVcoverage_loc -p41 -Visacov.rv32zifencei_fence_i_cg -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml new file mode 100644 index 000000000..12f3f8662 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -0,0 +1,32 @@ +!Feature +next_elt_id: 1 +name: RV32Zifencei Instruction-Fetch Fence +id: 14 +display_order: 14 +subfeatures: !!omap +- 000_FENCE.I: !Subfeature + name: 000_FENCE.I + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F014_S000_I000 + description: "Fence.I instruction executed\nImplementation is core-specific" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Fence.I instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32zifencei_fence_i_cg + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP015.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP015.yml new file mode 100644 index 000000000..d07158928 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP015.yml @@ -0,0 +1,154 @@ +!Feature +next_elt_id: 4 +name: Instruction execution sequences +id: 15 +display_order: 15 +subfeatures: !!omap +- 000_Instruction Execution: !Subfeature + name: 000_Instruction Execution + tag: VP_ISA_RV32_F015_S000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S000_I000 + description: All suported instructions for the core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S000_I001 + description: All suported instructions for the core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: All back-to-back supported instruction sequences are executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_Instruction Group Execution: !Subfeature + name: 001_Instruction Group Execution + tag: VP_ISA_RV32_F015_S001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S001_I000 + description: All defined instruction groups for a core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: For the core under test, all instruction groups are executed + in the core + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S001_I001 + description: All defined instruction groups are executed in sequence + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Depending on the length of the pipeline in the processor, sequence + chains of 2,3,or 4 instruction groups are checked for execution + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_GPR Hazard: !Subfeature + name: 002_GPR Hazard + tag: VP_ISA_RV32_F015_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S002_I000 + description: An instruction reads from register that was written to in the + previous instruction + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: All instruction groups are tested across GPR hazards + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSR Hazard: !Subfeature + name: 003_CSR Hazard + tag: VP_ISA_RV32_F015_S003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S003_I000 + description: CSR writes from the program are executed in conjunction with + all instruction groups + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "CSR write instruction attempts to write to a supported CSR\n\ + This does not include csr set or clear instructions where rs1 is x0 (bypassing\ + \ the write)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S003_I001 + description: CSR writes from the program are executed in conjunction with + all instruction groups + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Each instruction group is executed after each supported CSR is + written with a Zicsri write instructio + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index 8cc952c8a..5c581f0d5 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -17,11 +17,11 @@ export PLATFORM_TOP_DIR="$ROOTDIR" # Set the printable name for the project that will be used # in the human-readable documentation. -export PROJECT_NAME="ISA" +export PROJECT_NAME="ISA RISC-V 32b" # Set the alphanumerical identifier of the project that # will be used to construct file names etc. -export PROJECT_IDENT="ISA" +export PROJECT_IDENT="ISA_RV32" # Set the destination directory of Markdown files for this project. # Since it will be used by VPTOOL, it shall NOT be a relative path. @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/csr_access/VP_IP000.yml b/cva6/docs/VerifPlans/csr_access/VP_IP000.yml new file mode 100644 index 000000000..47fd5143d --- /dev/null +++ b/cva6/docs/VerifPlans/csr_access/VP_IP000.yml @@ -0,0 +1,71 @@ +!Feature +next_elt_id: 1 +name: machineScratch(MSCRATCH) +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_MSCRATCH: !Subfeature + name: 000_MSCRATCH + tag: VP_csr-test-ident_F000_S000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_csr-test-ident_F000_S000_I000 + description: "To verify the Power-on Reset value for MSCRATCH CSR.\n \nAddress\ + \ Offset : 0x340\nWidth (bits) : 32\nAccess Type : RW\nReset Value : 0x00000000\n\ + priviliged mode : Machine" + reqt_doc: riscv-privileged-20211203 + ref_mode: section + ref_page: '' + ref_section: 3.1.13 + ref_viewer: firefox + verif_goals: Read MSCRATCH CSR to check default POR value that should be equal + to 0x00000000. + pfc: 3 + test_type: 1 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_csr-test-ident_F000_S000_I001 + description: Verifying R/W access of a MSCRATCH CSR by writing random valid + data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values + to check correctness. + reqt_doc: riscv-privileged-20211203 + ref_mode: section + ref_page: '' + ref_section: 3.1.13 + ref_viewer: firefox + verif_goals: The read values of MSCRATCH CSR should matches with written random + data values. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_csr-test-ident_F000_S000_I002 + description: Verifying MSCRATCH CSR in other privilige modes(supervisor, user) + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: It is expected that accessing Machine Mode CSRs in lower privilige + modes will raise an exception. + pfc: 3 + test_type: 1 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/csr_access/cva6_csr.rst b/cva6/docs/VerifPlans/csr_access/cva6_csr.rst new file mode 100644 index 000000000..0d7e8ce29 --- /dev/null +++ b/cva6/docs/VerifPlans/csr_access/cva6_csr.rst @@ -0,0 +1,2653 @@ +REGISTERS CSR CV32A6 +=================== + +Floating-Point Accrued Exceptions Register +-------------------------- +AddressOffset: 'h1 +-------------------------- +Description: +-------------------------- +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 4 + - NV + - Invalid operation + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 3 + - DZ + - Divide by zero + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 2 + - OF + - Overflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 1 + - UF + - Underflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 0 + - NX + - Inexact + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + +Floating-Point Dynamic Rounding Mode Register +-------------------------- +AddressOffset: 'h2 +-------------------------- +Description: +-------------------------- +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 2:0 + - FRM + - Floating-point rounding mode + - read-write + - The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses\. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least\-significant three bits of integer register \*rd\*, with zero in all other bits\. FSRM swaps the value in frm by copying the original value into integer register \*rd\*, and then writing a new value obtained from the three least\-significant bits of integer register \*rs1\* into ``frm``\. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``\. ``Enumerated Values``( "RNE" :0)( "RTZ" :1)( "RDN" :2)( "RUP" :3)( "RMM" :4)( "INVALID_5" :5)( "INVALID_6" :6)( "DYN" :7)'\n' + +Floating-Point Control and Status Register Register +-------------------------- +AddressOffset: 'h3 +-------------------------- +Description: +-------------------------- +The floating-point control and status register, ``fcsr``, is a RISC-V control and status register (CSR). It is a read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags. + +The ``fcsr`` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads ``fcsr`` by copying it into integer register *rd*. FSCSR swaps the value in ``fcsr`` by copying the original value into integer register *rd*, and then writing a new value obtained from integer register *rs1* into ``fcsr``. + +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 7:5 + - FRM + - Floating-point rounding mode + - read-write + - Floating\-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``\. Rounding modes are encoded as shown in the enumerated value\. A value of 111 in the instruction’s \*rm\* field selects the dynamic rounding mode held in ``frm``\. If ``frm`` is set to an invalid value \(101–111\), any subsequent attempt to execute a floating\-point operation with a dynamic rounding mode will raise an illegal instruction exception\. Some instructions, including widening conversions, have the \*rm\* field but are nevertheless unaffected by the rounding mode; software should set their \*rm\* field to RNE \(000\)\. ``Enumerated Values``( "RNE" :0)( "RTZ" :1)( "RDN" :2)( "RUP" :3)( "RMM" :4)( "INVALID_5" :5)( "INVALID_6" :6)( "DYN" :7)'\n' + * - 4 + - NV + - Invalid operation + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 3 + - DZ + - Divide by zero + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 2 + - OF + - Overflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 1 + - UF + - Underflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 0 + - NX + - Inexact + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + +Supervisor Status Register +-------------------------- +AddressOffset: 'h100 +-------------------------- +Description: +-------------------------- +The ``sstatus`` register keeps track of the processor’s current operating state. + +The ``sstatus`` register is a subset of the ``mstatus`` register. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - SD + - State dirty + - read-only + - The SD bit is a read\-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory\. If FS, XS, and VS are all read\-only zero, then SD is also always zero\. + * - 19 + - MXR + - Make executable readable + - read-write + - The MXR bit modifies the privilege with which loads access virtual memory\. When MXR=0, only loads from pages marked readable will succeed\. When MXR=1, loads from pages marked either readable or executable \(R=1 or X=1\) will succeed\. MXR has no effect when page\-based virtual memory is not in effect\. + * - 18 + - SUM + - Supervisor user memory + - read-write + - The SUM \(permit Supervisor User Memory access\) bit modifies the privilege with which S\-mode loads and stores access virtual memory\. When SUM=0, S\-mode memory accesses to pages that are accessible by U\-mode will fault\. When SUM=1, these accesses are permitted\. SUM has no effect when page\-based virtual memory is not in effect\. Note that, while SUM is ordinarily ignored when not executing in S\-mode, it \*is\* in effect when MPRV=1 and MPP=S\. SUM is read\-only 0 if S\-mode is not supported or if ``satp``\.MODE is read\-only 0\. + * - 16:15 + - XS + - Extension state + - read-only + - The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 14:13 + - FS + - Floating-point unit state + - read-write + - The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 8 + - SPP + - Supervisor mode prior privilege + - read-write + - SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode\. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise\. When an SRET instruction is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0\. + * - 5 + - SPIE + - Supervisor mode prior interrupt enable + - read-write + - The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0\. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1\. + * - 4 + - UPIE + - + - read-write + - When a URET instruction is executed, UIE is set to UPIE, and UPIE is set to 1\. + * - 1 + - SIE + - Supervisor mode interrupt enable + - read-write + - The SIE bit enables or disables all interrupts in supervisor mode\. When SIE is clear, interrupts are not taken while in supervisor mode\. When the hart is running in user\-mode, the value in SIE is ignored, and supervisor\-level interrupts are enabled\. The supervisor can disable individual interrupt sources using the ``sie`` CSR\. + * - 0 + - UIE + - + - read-write + - The UIE bit enables or disables user\-mode interrupts\. + +Supervisor Interrupt Enable Register +-------------------------- +AddressOffset: 'h104 +-------------------------- +Description: +-------------------------- +The ``sie`` is the register containing supervisor interrupt enable bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 9 + - SEIE + - Supervisor-level external interrupt enable + - read-write + - SEIE is the interrupt\-enable bit for supervisor\-level external interrupts\. + * - 8 + - UEIE + - + - read-write + - User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\. + * - 5 + - STIE + - Supervisor-level timer interrupt enable + - read-write + - STIE is the interrupt\-enable bit for supervisor\-level timer interrupts\. + * - 4 + - UTIE + - + - read-write + - User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\. + * - 1 + - SSIE + - Supervisor-level software interrupt enable + - read-write + - SSIE is the interrupt\-enable bit for supervisor\-level software interrupts\. + * - 0 + - USIE + - + - read-write + - User\-level software interrupts are disabled when the USIE bit in the sie register is clear + +Supervisor Trap Vector Base Address Register +-------------------------- +AddressOffset: 'h105 +-------------------------- +Description: +-------------------------- +The ``stvec`` register holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:2 + - BASE + - + - read-write + - The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4\-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field\. + * - 1:0 + - MODE + - + - read-write + - When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\. ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n' + +Supervisor Counter Enable Register +-------------------------- +AddressOffset: 'h106 +-------------------------- +Description: +-------------------------- +The counter-enable register ``scounteren`` controls the availability of the hardware performance monitoring counters to U-mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:3 + - HPMn + - Hpmcountern + - read-write + - When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 2 + - IR + - Instret + - read-write + - When IR is clear, attempts to read the ``instret`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 1 + - TM + - Time + - read-write + - When TM is clear, attempts to read the ``time`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 0 + - CY + - Cycle + - read-write + - When CY is clear, attempts to read the ``cycle`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + +Supervisor Scratch Register +-------------------------- +AddressOffset: 'h140 +-------------------------- +Description: +-------------------------- +The ``sscratch`` register is dedicated for use by the supervisor. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - SSCRATCH + - Supervisor scratch + - read-write + - The ``sscratch`` register is dedicated for use by the supervisor\. + +Supervisor Exception Program Counter Register +-------------------------- +AddressOffset: 'h141 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - SEPC + - Supervisor exception program counter + - read-write + - When a trap is taken into S\-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception\. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software\. + +Supervisor Cause Register +-------------------------- +AddressOffset: 'h142 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``scause`` is written with a code indicating the event that caused the trap. Otherwise, ``scause`` is never written by the implementation, though it may be explicitly written by software. +Supervisor cause register (``scause``) values after trap are shown in the following table. + +.. list-table:: + :widths: 20 20 20 + :header-rows: 1 + + * - **Interrupt** + - **Exception Code** + - **Description** + * - 1 + - 0 + - *Reserved* + * - 1 + - 1 + - Supervisor software interrupt + * - 1 + - 2-4 + - *Reserved* + * - 1 + - 5 + - Supervisor timer interrupt + * - 1 + - 6-8 + - *Reserved* + * - 1 + - 9 + - Supervisor external interrupt + * - 1 + - 10-15 + - *Reserved* + * - 1 + - >=16 + - *Designated for platform use* + * - 0 + - 0 + - Instruction address misaligned + * - 0 + - 1 + - Instruction access fault + * - 0 + - 2 + - Illegal instruction + * - 0 + - 3 + - Breakpoint + * - 0 + - 4 + - Load address misaligned + * - 0 + - 5 + - Load access fault + * - 0 + - 6 + - Store/AMO address misaligned + * - 0 + - 7 + - Store/AMO access fault + * - 0 + - 8 + - Environment call from U-mode + * - 0 + - 9 + - Environment call from S-mode + * - 0 + - 10-11 + - *Reserved* + * - 0 + - 12 + - Instruction page fault + * - 0 + - 13 + - Load page fault + * - 0 + - 14 + - *Reserved* + * - 0 + - 15 + - Store/AMO page fault + * - 0 + - 16-23 + - *Reserved* + * - 0 + - 24-31 + - *Designated for custom use* + * - 0 + - 32-47 + - *Reserved* + * - 0 + - 48-63 + - *Designated for custom use* + * - 0 + - >=64 + - *Reserved* + + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - Interrupt + - + - read-write + - The Interrupt bit in the ``scause`` register is set if the trap was caused by an interrupt\. + * - 30:0 + - Exception_Code + - Exception code + - read-write + - The Exception Code field contains a code identifying the last exception or interrupt\. + +Supervisor Trap Value Register +-------------------------- +AddressOffset: 'h143 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``stval`` is written with exception-specific information to assist software in handling the trap. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - STVAL + - Supervisor trap value + - read-write + - When a trap is taken into S\-mode, ``stval`` is written with exception\-specific information to assist software in handling the trap\. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software\. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero\. + +Supervisor Interrupt Pending Register +-------------------------- +AddressOffset: 'h144 +-------------------------- +Description: +-------------------------- +The ``sip`` register contains information on pending interrupts. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 9 + - SEIP + - Supervisor-level external interrupt pending + - read-only + - SEIP is the interrupt\-pending bit for supervisor\-level external interrupts\. + * - 8 + - UEIP + - + - read-write + - UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\. + * - 5 + - STIP + - Supervisor-level timer interrupt pending + - read-only + - SEIP is the interrupt\-pending bit for supervisor\-level timer interrupts\. + * - 4 + - UTIP + - + - read-write + - A user\-level timer interrupt is pending if the UTIP bit in the sip register is set + * - 1 + - SSIP + - Supervisor-level software interrupt pending + - read-only + - SSIP is the interrupt\-pending bit for supervisor\-level software interrupts\. + * - 0 + - USIP + - + - read-write + - A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit + +Supervisor Address Translation and Protection Register +-------------------------- +AddressOffset: 'h180 +-------------------------- +Description: +-------------------------- +The ``satp`` register controls supervisor-mode address translation and protection. + +The ``satp`` register is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of ``satp`` when ``satp`` is active. + +.. note:: + Writing ``satp`` does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction after, or in some cases before, writing ``satp``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:31 + - MODE + - Mode + - read-write + - This bitfield selects the current address\-translation scheme\. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme\. To select MODE=Bare, software must write zero to the remaining fields of ``satp`` \(bits 30–0\)\. Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an ``unspecified`` effect on the value that the remaining fields assume and an ``unspecified`` effect on address translation and protection behavior\. ``Enumerated Values``( "Bare" :0)( "Sv32" :1)'\n' + * - 30:22 + - ASID + - Address space identifier + - read-write + - This bitfield facilitates address\-translation fences on a per\-address\-space basis\. + * - 21:0 + - PPN + - Physical page number + - read-write + - This bitfield holds the root page table, i\.e\., its supervisor physical address divided by 4 KiB\. + +Machine Status Register +-------------------------- +AddressOffset: 'h300 +-------------------------- +Description: +-------------------------- +The ``mstatus`` register keeps track of and controls the hart’s current operating state. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - SD + - State dirty + - read-only + - The SD bit is a read\-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory\. If FS, XS, and VS are all read\-only zero, then SD is also always zero\. + * - 22 + - TSR + - Trap sret + - read-write + - The TSR bit supports intercepting the supervisor exception return instruction, SRET\. When TSR=1, attempts to execute SRET while executing in S\-mode will raise an illegal instruction exception\. When TSR=0, this operation is permitted in S\-mode\. + * - 21 + - TW + - Timeout wait + - read-write + - The TW bit supports intercepting the WFI instruction\. When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason\. When TW=1, then if WFI is executed in any less\-privileged mode, and it does not complete within an implementation\-specific, bounded time limit, the WFI instruction causes an illegal instruction exception\. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less\-privileged modes when TW=1\. + * - 20 + - TVM + - Trap virtual memory + - read-write + - The TVM bit supports intercepting supervisor virtual\-memory management operations\. When TVM=1, attempts to read or write the ``satp`` CSR or execute an SFENCE\.VMA or SINVAL\.VMA instruction while executing in S\-mode will raise an illegal instruction exception\. When TVM=0, these operations are permitted in S\-mode\. + * - 19 + - MXR + - Make executable readable + - read-write + - The MXR bit modifies the privilege with which loads access virtual memory\. When MXR=0, only loads from pages marked readable will succeed\. When MXR=1, loads from pages marked either readable or executable \(R=1 or X=1\) will succeed\. MXR has no effect when page\-based virtual memory is not in effect\. + * - 18 + - SUM + - Supervisor user memory + - read-write + - The SUM \(permit Supervisor User Memory access\) bit modifies the privilege with which S\-mode loads and stores access virtual memory\. When SUM=0, S\-mode memory accesses to pages that are accessible by U\-mode will fault\. When SUM=1, these accesses are permitted\. SUM has no effect when page\-based virtual memory is not in effect\. Note that, while SUM is ordinarily ignored when not executing in S\-mode, it is in effect when MPRV=1 and MPP=S\. + * - 17 + - MPRV + - Modify privilege + - read-write + - The MPRV \(Modify PRiVilege\) bit modifies the effective privilege mode, i\.e\., the privilege level at which loads and stores execute\. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the current privilege mode\. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP\. Instruction address\-translation and protection are unaffected by the setting of MPRV\. + * - 16:15 + - XS + - Extension state + - read-only + - The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 14:13 + - FS + - Floating-point unit state + - read-write + - The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 12:11 + - MPP + - Machine mode prior privilege + - read-write + - Holds the previous privilege mode for machine mode\. + * - 8 + - SPP + - Supervisor mode prior privilege + - read-write + - Holds the previous privilege mode for supervisor mode\. + * - 7 + - MPIE + - Machine mode prior interrupt enable + - read-write + - Indicates whether machine interrupts were enabled prior to trapping into machine mode\. + * - 5 + - SPIE + - Supervisor mode prior interrupt enable + - read-write + - Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. + * - 4 + - UPIE + - + - read-write + - indicates whether user\-level interrupts were enabled prior to taking a user\-level trap + * - 3 + - MIE + - Machine mode interrupt enable + - read-write + - Global interrupt\-enable bit for Machine mode\. + * - 1 + - SIE + - Supervisor mode interrupt enable + - read-write + - Global interrupt\-enable bit for Supervisor mode\. + * - 0 + - UIE + - + - read-write + - Global interrupt\-enable bits + +Machine ISA Register +-------------------------- +AddressOffset: 'h301 +-------------------------- +Description: +-------------------------- +The misa CSR is reporting the ISA supported by the hart. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:30 + - MXL + - Machine xlen + - read-write + - The MXL field encodes the native base integer ISA width\. ``Enumerated Values``( "XLEN_32" :1)( "XLEN_64" :2)( "XLEN_128" :3)'\n' + * - 25:0 + - Extensions + - Extensions + - read-write + - The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet\. ``Enumerated Values``( "A" :1)( "B" :2)( "C" :4)( "D" :8)( "E" :16)( "F" :32)( "G" :64)( "H" :128)( "I" :256)( "J" :512)( "K" :1024)( "L" :2048)( "M" :4096)( "N" :8192)( "O" :16384)( "P" :32768)( "Q" :65536)( "R" :131072)( "S" :262144)( "T" :524288)( "U" :1048576)( "V" :2097152)( "W" :4194304)( "X" :8388608)( "Y" :16777216)( "Z" :33554432)'\n' + +Machine Exception Delegation Register +-------------------------- +AddressOffset: 'h302 +-------------------------- +Description: +-------------------------- +Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - Synchronous_Exceptions + - Synchronous exceptions + - read-write + - Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level\. + +Machine Interrupt Delegation Register +-------------------------- +AddressOffset: 'h303 +-------------------------- +Description: +-------------------------- +Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - Interrupts + - Interrupts + - read-write + - Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level\. + +Machine Interrupt Enable Register +-------------------------- +AddressOffset: 'h304 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt enable bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 11 + - MEIE + - M-mode external interrupt enable + - read-write + - Enables machine mode external interrupts\. + * - 9 + - SEIE + - S-mode external interrupt enable + - read-write + - Enables supervisor mode external interrupts\. + * - 8 + - UEIE + - + - read-write + - enables U\-mode external interrupts + * - 7 + - MTIE + - M-mode timer interrupt enable + - read-write + - Enables machine mode timer interrupts\. + * - 5 + - STIE + - S-mode timer interrupt enable + - read-write + - Enables supervisor mode timer interrupts\. + * - 4 + - UTIE + - + - read-write + - timer interrupt\-enable bit for U\-mode + * - 3 + - MSIE + - M-mode software interrupt enable + - read-write + - Enables machine mode software interrupts\. + * - 1 + - SSIE + - S-mode software interrupt enable + - read-write + - Enables supervisor mode software interrupts\. + * - 0 + - USIE + - + - read-write + - enable U\-mode software interrrupts + +Machine Trap Vector Register +-------------------------- +AddressOffset: 'h305 +-------------------------- +Description: +-------------------------- +This register holds trap vector configuration, consisting of a vector base address and a vector mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:2 + - BASE + - + - read-write + - Holds the vector base address\. The value in the BASE field must always be aligned on a 4\-byte boundary\. + * - 1:0 + - MODE + - + - read-write + - Imposes additional alignment constraints on the value in the BASE field\. ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n' + +Machine Counter Enable Register +-------------------------- +AddressOffset: 'h306 +-------------------------- +Description: +-------------------------- +This register controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:3 + - HPMn + - Hpmcountern + - read-write + - When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 2 + - IR + - Instret + - read-write + - When IR is clear, attempts to read the ``instret`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 1 + - TM + - Time + - read-write + - When TM is clear, attempts to read the ``time`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 0 + - CY + - Cycle + - read-write + - When CY is clear, attempts to read the ``cycle`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + +Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h323 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 4:0 + - mhpmevent + - + - read-write + - This register controls which event causes the corresponding counter to increment\. + +Machine Scratch Register +-------------------------- +AddressOffset: 'h340 +-------------------------- +Description: +-------------------------- +This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mscratch + - Machine scratch + - read-write + - This register is used to hold a value dedicated to Machine mode\. Attempts to access without Machine mode level raise illegal instruction exception\. + +Machine Exception Program Counter Register +-------------------------- +AddressOffset: 'h341 +-------------------------- +Description: +-------------------------- +This register must be able to hold all valid virtual addresses. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mepc + - Machine exception program counter + - read-write + - This register must be able to hold all valid virtual addresses\. + +Machine Cause Register +-------------------------- +AddressOffset: 'h342 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. +Machine cause register (``mcause``) values after trap are shown in the following table. + +.. list-table:: + :widths: 20 20 20 + :header-rows: 1 + + * - **Interrupt** + - **Exception Code** + - **Description** + * - 1 + - 0 + - *Reserved* + * - 1 + - 1 + - Supervisor software interrupt + * - 1 + - 2-4 + - *Reserved* + * - 1 + - 5 + - Supervisor timer interrupt + * - 1 + - 6-8 + - *Reserved* + * - 1 + - 9 + - Supervisor external interrupt + * - 1 + - 10-15 + - *Reserved* + * - 1 + - >=16 + - *Designated for platform use* + * - 0 + - 0 + - Instruction address misaligned + * - 0 + - 1 + - Instruction access fault + * - 0 + - 2 + - Illegal instruction + * - 0 + - 3 + - Breakpoint + * - 0 + - 4 + - Load address misaligned + * - 0 + - 5 + - Load access fault + * - 0 + - 6 + - Store/AMO address misaligned + * - 0 + - 7 + - Store/AMO access fault + * - 0 + - 8 + - Environment call from U-mode + * - 0 + - 9 + - Environment call from S-mode + * - 0 + - 10-11 + - *Reserved* + * - 0 + - 12 + - Instruction page fault + * - 0 + - 13 + - Load page fault + * - 0 + - 14 + - *Reserved* + * - 0 + - 15 + - Store/AMO page fault + * - 0 + - 16-23 + - *Reserved* + * - 0 + - 24-31 + - *Designated for custom use* + * - 0 + - 32-47 + - *Reserved* + * - 0 + - 48-63 + - *Designated for custom use* + * - 0 + - >=64 + - *Reserved* + + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - Interrupt + - Interrupt + - read-write + - This bit is set if the trap was caused by an interrupt\. + * - 30:0 + - exception_code + - Exception code + - read-write + - This field contains a code identifying the last exception or interrupt\. + +Machine Trap Value Register +-------------------------- +AddressOffset: 'h343 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mtval + - Machine trap value + - read-write + - When a trap is taken into M\-mode, mtval is either set to zero or written with exception\-specific information to assist software in handling the trap\. + +Machine Interrupt Pending Register +-------------------------- +AddressOffset: 'h344 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt pending bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 11 + - MEIP + - M-mode external interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level external interrupts\. + * - 9 + - SEIP + - S-mode external interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level external interrupts\. + * - 8 + - UEIP + - + - read-write + - enables external interrupts + * - 7 + - MTIP + - M-mode timer interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level timer interrupts\. + * - 5 + - STIP + - S-mode timer interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level timer interrupts\. + * - 4 + - UTIP + - + - read-write + - Correspond to timer interrupt\-pending bits for user interrupt + * - 3 + - MSIP + - M-mode software interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level software interrupts\. + * - 1 + - SSIP + - S-mode software interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level software interrupts\. + * - 0 + - USIP + - + - read-write + - A hart to directly write its own USIP bits when running in the appropriate mode + +Physical Memory Protection Config 0 Register +-------------------------- +AddressOffset: 'h3A0 +-------------------------- +Description: +-------------------------- +Holds configuration 0-3. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp3cfg + - Physical memory protection 3 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp2cfg + - Physical memory protection 2 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp1cfg + - Physical memory protection 1 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp0cfg + - Physical memory protection 0 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 1 Register +-------------------------- +AddressOffset: 'h3A1 +-------------------------- +Description: +-------------------------- +Holds configuration 4-7. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp7cfg + - Physical memory protection 7 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp6cfg + - Physical memory protection 6 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp5cfg + - Physical memory protection 5 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp4cfg + - Physical memory protection 4 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 2 Register +-------------------------- +AddressOffset: 'h3A2 +-------------------------- +Description: +-------------------------- +Holds configuration 8-11. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp11cfg + - Physical memory protection 11 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp10cfg + - Physical memory protection 10 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp9cfg + - Physical memory protection 9 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp8cfg + - Physical memory protection 8 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 3 Register +-------------------------- +AddressOffset: 'h3A3 +-------------------------- +Description: +-------------------------- +Holds configuration 12-15. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp15cfg + - Physical memory protection 15 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp14cfg + - Physical memory protection 14 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp13cfg + - Physical memory protection 13 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp12cfg + - Physical memory protection 12 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3B0 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - read-write + - Address register for Physical Memory Protection\. + +Instuction Cache Register +-------------------------- +AddressOffset: 'h700 +-------------------------- +Description: +-------------------------- +Custom Register to enable/disable for Icache [bit 0] + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 0 + - icache + - Instruction cache + - read-write + - Custom Register to enable/disable for Icache \[bit 0\] + +Data Cache Register +-------------------------- +AddressOffset: 'h701 +-------------------------- +Description: +-------------------------- +Custom Register to enable/disable for Dcache [bit 0] + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 0 + - dcache + - Data cache + - read-write + - Custom Register to enable/disable for Dcache \[bit 0\] + +Trigger Select Register +-------------------------- +AddressOffset: 'h7A0 +-------------------------- +Description: +-------------------------- +This register determines which trigger is accessible through the other trigger registers. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - index + - Index + - read-write + - This register determines which trigger is accessible through the other trigger registers\. + +Trigger Data 1 Register +-------------------------- +AddressOffset: 'h7A1 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:28 + - type + - Type + - read-write + - Type of trigger\. ``Enumerated Values``( "no_trigger" :0)( "legacy_address_match_trigger" :1)( "address_data_match_trigger" :2)( "instruction_count_trigger" :3)( "interrupt_trigger" :4)( "exception_trigger" :5)( "Reserved_6" :6)( "Reserved_7" :7)( "Reserved_8" :8)( "Reserved_9" :9)( "Reserved_10" :10)( "Reserved_11" :11)( "Reserved_12" :12)( "Reserved_13" :13)( "Reserved_14" :14)( "trigger_exists" :15)'\n' + * - 27:27 + - dmode + - Debug mode + - read-write + - This bit is only writable from Debug Mode\. ``Enumerated Values``( "D_and_M_mode" :0)( "M_mode_only" :1)'\n' + * - 26:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Data 2 Register +-------------------------- +AddressOffset: 'h7A2 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Data 3 Register +-------------------------- +AddressOffset: 'h7A3 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Info Register +-------------------------- +AddressOffset: 'h7A4 +-------------------------- +Description: +-------------------------- +Shows trigger information. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 15:0 + - info + - Info + - read-only + - Shows trigger information\. + +Debug Control and Status Register +-------------------------- +AddressOffset: 'h7B0 +-------------------------- +Description: +-------------------------- +Debug ontrol and status register. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:28 + - xdebugver + - Debug version + - read-only + - Shows the version of the debug support\. ``Enumerated Values``( "no_ext_debug" :0)( "ext_debug_spec" :4)( "ext_debug_no_spec" :15)'\n' + * - 15:15 + - ebreakm + - Environment breakpoint m-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in machine mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 13:13 + - ebreaks + - Environment breakpoint s-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in supervisor mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 12:12 + - ebreaku + - Environment breakpoint u-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in user mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 11:11 + - stepie + - Stepping interrupt enable + - read-write + - Enables/disables interrupts for single stepping\. The debugger must not change the value of this bit while the hart is running\. ``Enumerated Values``( "disabled" :0)( "enabled" :1)'\n' + * - 10:10 + - stopcount + - Stop counters + - read-write + - Starts/stops incrementing counters in debug mode\. ``Enumerated Values``( "increment_counters" :0)( "dont_increment_counters" :1)'\n' + * - 9:9 + - stoptime + - Stop timers + - read-write + - Starts/stops incrementing timers in debug mode\. ``Enumerated Values``( "increment_timers" :0)( "dont_increment_timers" :1)'\n' + * - 8:6 + - cause + - Cause + - read-write + - Explains why Debug Mode was entered\. When there are multiple reasons to enter Debug Mode in a single cycle, hardware sets ``cause`` to the cause with the highest priority\. ``Enumerated Values``( "ebreak_instruction" :1)( "trigger_module" :2)( "debugger_request" :3)( "single_step" :4)( "reset_halt" :5)'\n' + * - 4:4 + - mprven + - Modify privilege enable + - read-write + - Enables/disables the modify privilege setting in debug mode\. ``Enumerated Values``( "disable_mprv" :0)( "enable_mprv" :1)'\n' + * - 3 + - nmip + - Non-maskable interrupt pending + - read-only + - When set, there is a Non\-Maskable\-Interrupt \(NMI\) pending for the hart\. + * - 2 + - step + - Step + - read-write + - When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode\. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set\. The debugger must not change the value of this bit while the hart is running\. + * - 1:0 + - prv + - Privilege level + - read-write + - Contains the privilege level the hart was operating in when Debug Mode was entered\. A debugger can change this value to change the hart’s privilege level when exiting Debug Mode\. ``Enumerated Values``( "User" :0)( "Supervisor" :1)( "Machine" :3)'\n' + +Debug PC Register +-------------------------- +AddressOffset: 'h7B1 +-------------------------- +Description: +-------------------------- +Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed. + +When resuming, the hart’s PC is updated to the virtual address stored in ``dpc``. A debugger may write ``dpc`` to change where the hart resumes. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - dpc + - + - read-write + - Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed\. When resuming, the hart’s PC is updated to the virtual address stored in ``dpc``\. A debugger may write ``dpc`` to change where the hart resumes\. + +Debug Scratch Register Register +-------------------------- +AddressOffset: 'h7B2 +-------------------------- +Description: +-------------------------- +Optional scratch register. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - dscratch + - + - read-write + - Optional scratch register\. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it\. + + Register +-------------------------- +AddressOffset: 'h800 +-------------------------- +Description: +-------------------------- +Floating Point Custom CSR + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 6:0 + - ftran + - + - read-write + - Floating Point Custom CSR + +M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB00 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of clock cycles executed by the processor core on which the hart is running\. + +Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB02 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of instructions the hart has retired\. + +L1 Inst Cache Miss Register +-------------------------- +AddressOffset: 'hB03 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +L1 Data Cache Miss Register +-------------------------- +AddressOffset: 'hB04 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +ITLB Miss Register +-------------------------- +AddressOffset: 'hB05 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +DTLB Miss Register +-------------------------- +AddressOffset: 'hB06 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Loads Register +-------------------------- +AddressOffset: 'hB07 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Stores Register +-------------------------- +AddressOffset: 'hB08 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Taken Exceptions Register +-------------------------- +AddressOffset: 'hB09 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Exception Return Register +-------------------------- +AddressOffset: 'hB0A +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Software Change of PC Register +-------------------------- +AddressOffset: 'hB0B +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Procedure Call Register +-------------------------- +AddressOffset: 'hB0C +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Procedure Return Register +-------------------------- +AddressOffset: 'hB0D +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Branch mis-predicted Register +-------------------------- +AddressOffset: 'hB0E +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Scoreboard Full Register +-------------------------- +AddressOffset: 'hB0F +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Instruction Fetch Queue Empty Register +-------------------------- +AddressOffset: 'hB10 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Upper 32-bits of M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB80 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of clock cycles executed by the processor core on which the hart is running\. + +Upper 32-bits of Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB82 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of instructions the hart has retired\. + +Upper 32-bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hB83 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Cycle counter Register +-------------------------- +AddressOffset: 'hC00 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Cycle counter for RDCYCLE instruction\. + +Timer Register +-------------------------- +AddressOffset: 'hC01 +-------------------------- +Description: +-------------------------- +Timer for RDTIME instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Timer for RDTIME instruction\. + +Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC02 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Instructions\-retired counter for RDINSTRET instruction + +L1 Inst Cache Miss Register +-------------------------- +AddressOffset: 'hC03 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +L1 Data Cache Miss Register +-------------------------- +AddressOffset: 'hC04 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +ITLB Miss Register +-------------------------- +AddressOffset: 'hC05 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +DTLB Miss Register +-------------------------- +AddressOffset: 'hC06 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Loads Register +-------------------------- +AddressOffset: 'hC07 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Stores Register +-------------------------- +AddressOffset: 'hC08 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Taken Exceptions Register +-------------------------- +AddressOffset: 'hC09 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Exception Return Register +-------------------------- +AddressOffset: 'hC0A +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Software Change of PC Register +-------------------------- +AddressOffset: 'hC0B +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Procedure Call Register +-------------------------- +AddressOffset: 'hC0C +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Procedure Return Register +-------------------------- +AddressOffset: 'hC0D +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Branch mis-predicted Register +-------------------------- +AddressOffset: 'hC0E +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Scoreboard Full Register +-------------------------- +AddressOffset: 'hC0F +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Instruction Fetch Queue Empty Register +-------------------------- +AddressOffset: 'hC10 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Upper 32-bits of Cycle counter Register +-------------------------- +AddressOffset: 'hC80 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Cycle counter for RDCYCLE instruction\. + +Upper 32-bit of Timer Register +-------------------------- +AddressOffset: 'hC81 +-------------------------- +Description: +-------------------------- +Timer for RDTIME instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Timer for RDTIME instruction\. + +Upper 32-bits of Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC82 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Instructions\-retired counter for RDINSTRET instruction + +Machine Vendor ID Register +-------------------------- +AddressOffset: 'hF11 +-------------------------- +Description: +-------------------------- +This register provids the JEDEC manufacturer ID of the provider of the core. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:7 + - bank + - Bank + - read-only + - Contain encoding for number of one\-byte continuation codes discarding the parity bit\. + * - 6:0 + - offset + - Offset + - read-only + - Contain encording for the final byte discarding the parity bit\. + +Machine Architecture ID Register +-------------------------- +AddressOffset: 'hF12 +-------------------------- +Description: +-------------------------- +This register encodes the base microarchitecture of the hart. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - architecture_id + - Architecture id + - read-only + - This register encodes the base microarchitecture of the hart\. + +Machine Implementation ID Register +-------------------------- +AddressOffset: 'hF13 +-------------------------- +Description: +-------------------------- +Provides a unique encoding of the version of the processor implementation. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - implementation + - Implementation + - read-only + - Provides a unique encoding of the version of the processor implementation\. + +Machine Hardware Thread ID Register +-------------------------- +AddressOffset: 'hF14 +-------------------------- +Description: +-------------------------- +This register contains the integer ID of the hardware thread running the code. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - hart_id + - Hart id + - read-only + - This register contains the integer ID of the hardware thread running the code\. diff --git a/cva6/docs/VerifPlans/csr_access/runme.sh b/cva6/docs/VerifPlans/csr_access/runme.sh new file mode 100644 index 000000000..fbf348b40 --- /dev/null +++ b/cva6/docs/VerifPlans/csr_access/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="CSR ACCESS VERIFICATION" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="csr-access" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/install-prerequisites.sh b/cva6/docs/VerifPlans/install-prerequisites.sh index 65a4d5642..b8f169bb7 100644 --- a/cva6/docs/VerifPlans/install-prerequisites.sh +++ b/cva6/docs/VerifPlans/install-prerequisites.sh @@ -9,19 +9,29 @@ ############################################################################# # Make sure all necessary components are installed/available. # -# Install Python dependencies. -for REQT in `cat requirements.txt` ; do - python3 -m pip install $REQT -done +# Install Python dependencies. We can extract the full path of the script only +# when invoked using '$SHELL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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- Metrics Report Generate on 2020/11/03 08:34:26 -
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Context Info:
- loaded run directory
  /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default

model files
  domain : hdl
    /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default/icc_59a3d6de_075288d4.ucm

ucds files
  domain : hdl
    /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default/icc_59a3d6de_075288d4.ucd

loaded refinements
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.auto.vRefine
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.manual.vRefine
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.hierarchy.vRefine

ccf files
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/covfile.tcl
    # ----------------------------------------------------------------------------------
    # General coverage configuration options
    # ----------------------------------------------------------------------------------
    
    # Setting Constant Object Marking and enabling log for it
    set_com -log
    
    # Disable scoring of implicit else and default case blocks
    set_implicit_block_scoring -off
    
    # Remove empty instances from coverage hierarchy
    deselect_coverage -remove_empty_instances
    
    # Enable resilience from code changes
    set_refinement_resilience
    
    # Improve expression coverage performance
    set_optimize -vlog_prune_on
    
    # Set glitch strobes
    set_glitch_strobe 1ps
    
    # ----------------------------------------------------------------------------------
    # Expression coverage configuration
    # ----------------------------------------------------------------------------------
    
    # Setting expression scoring for all operators (not only boolean (|| &&) and VHDL (AND OR NOR NAND)
    set_expr_scoring -all
    
    # ----------------------------------------------------------------------------------
    # Toggle coverage configuration
    # ----------------------------------------------------------------------------------
    
    # Toggle coverage smart refinement (refinement for toggle with traverse hierarchy)
    set_toggle_smart_refinement

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(#13335) -// Support: Firefox 18+ -//"use strict"; -var - // The deferred used on DOM ready - readyList, - - // A central reference to the root jQuery(document) - rootjQuery, - - // Support: IE<10 - // For `typeof xmlNode.method` instead of `xmlNode.method !== undefined` - core_strundefined = typeof undefined, - - // Use the correct document accordingly with window argument (sandbox) - location = window.location, - document = window.document, - docElem = document.documentElement, - - // Map over jQuery in case of overwrite - _jQuery = window.jQuery, - - // Map over the $ in case of overwrite - _$ = window.$, - - // [[Class]] -> type pairs - class2type = {}, - - // List of deleted data cache ids, so we can reuse them - core_deletedIds = [], - - core_version = "1.10.2", - - // Save a reference to some core methods - core_concat = core_deletedIds.concat, - core_push = core_deletedIds.push, - core_slice = core_deletedIds.slice, - core_indexOf = core_deletedIds.indexOf, - core_toString = class2type.toString, - core_hasOwn = class2type.hasOwnProperty, - core_trim = core_version.trim, - - // Define a local copy of jQuery - jQuery = function( selector, context ) { - // The jQuery object is actually just the init constructor 'enhanced' - return new jQuery.fn.init( selector, context, rootjQuery ); - }, - - // Used for matching numbers - core_pnum = /[+-]?(?:\d*\.|)\d+(?:[eE][+-]?\d+|)/.source, - - // Used for splitting on whitespace - core_rnotwhite = /\S+/g, - - // Make sure we trim BOM and NBSP (here's looking at you, Safari 5.0 and IE) - rtrim = /^[\s\uFEFF\xA0]+|[\s\uFEFF\xA0]+$/g, - - // A simple way to check for HTML strings - // Prioritize #id over to avoid XSS via location.hash (#9521) - // Strict HTML recognition (#11290: must start with <) - rquickExpr = /^(?:\s*(<[\w\W]+>)[^>]*|#([\w-]*))$/, - - // Match a standalone tag - rsingleTag = /^<(\w+)\s*\/?>(?:<\/\1>|)$/, - - // JSON RegExp - rvalidchars = /^[\],:{}\s]*$/, - rvalidbraces = /(?:^|:|,)(?:\s*\[)+/g, - rvalidescape = /\\(?:["\\\/bfnrt]|u[\da-fA-F]{4})/g, - rvalidtokens = /"[^"\\\r\n]*"|true|false|null|-?(?:\d+\.|)\d+(?:[eE][+-]?\d+|)/g, - - // Matches dashed string for camelizing - rmsPrefix = /^-ms-/, - rdashAlpha = /-([\da-z])/gi, - - // Used by jQuery.camelCase as callback to replace() - fcamelCase = function( all, letter ) { - return letter.toUpperCase(); - }, - - // The ready event handler - completed = function( event ) { - - // readyState === "complete" is good enough for us to call the dom ready in oldIE - if ( document.addEventListener || event.type === "load" || document.readyState === "complete" ) { - detach(); - jQuery.ready(); - } - }, - // Clean-up method for dom ready events - detach = function() { - if ( document.addEventListener ) { - document.removeEventListener( "DOMContentLoaded", completed, false ); - window.removeEventListener( "load", completed, false ); - - } else { - document.detachEvent( "onreadystatechange", completed ); - window.detachEvent( "onload", completed ); - } - }; - -jQuery.fn = jQuery.prototype = { - // The current version of jQuery being used - jquery: core_version, - - constructor: jQuery, - init: function( selector, context, rootjQuery ) { - var match, elem; - - // HANDLE: $(""), $(null), $(undefined), $(false) - if ( !selector ) { - return this; - } - - // Handle HTML strings - if ( typeof selector === "string" ) { - if ( selector.charAt(0) === "<" && selector.charAt( selector.length - 1 ) === ">" && selector.length >= 3 ) { - // Assume that strings that start and end with <> are HTML and skip the regex check - match = [ null, selector, null ]; - - } else { - match = rquickExpr.exec( selector ); - } - - // Match html or make sure no context is specified for #id - if ( match && (match[1] || !context) ) { - - // HANDLE: $(html) -> $(array) - if ( match[1] ) { - context = context instanceof jQuery ? context[0] : context; - - // scripts is true for back-compat - jQuery.merge( this, jQuery.parseHTML( - match[1], - context && context.nodeType ? context.ownerDocument || context : document, - true - ) ); - - // HANDLE: $(html, props) - if ( rsingleTag.test( match[1] ) && jQuery.isPlainObject( context ) ) { - for ( match in context ) { - // Properties of context are called as methods if possible - if ( jQuery.isFunction( this[ match ] ) ) { - this[ match ]( context[ match ] ); - - // ...and otherwise set as attributes - } else { - this.attr( match, context[ match ] ); - } - } - } - - return this; - - // HANDLE: $(#id) - } else { - elem = document.getElementById( match[2] ); - - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - if ( elem && elem.parentNode ) { - // Handle the case where IE and Opera return items - // by name instead of ID - if ( elem.id !== match[2] ) { - return rootjQuery.find( selector ); - } - - // Otherwise, we inject the element directly into the jQuery object - this.length = 1; - this[0] = elem; - } - - this.context = document; - this.selector = selector; - return this; - } - - // HANDLE: $(expr, $(...)) - } else if ( !context || context.jquery ) { - return ( context || rootjQuery ).find( selector ); - - // HANDLE: $(expr, context) - // (which is just equivalent to: $(context).find(expr) - } else { - return this.constructor( context ).find( selector ); - } - - // HANDLE: $(DOMElement) - } else if ( selector.nodeType ) { - this.context = this[0] = selector; - this.length = 1; - return this; - - // HANDLE: $(function) - // Shortcut for document ready - } else if ( jQuery.isFunction( selector ) ) { - return rootjQuery.ready( selector ); - } - - if ( selector.selector !== undefined ) { - this.selector = selector.selector; - this.context = selector.context; - } - - return jQuery.makeArray( selector, this ); - }, - - // Start with an empty selector - selector: "", - - // The default length of a jQuery object is 0 - length: 0, - - toArray: function() { - return core_slice.call( this ); - }, - - // Get the Nth element in the matched element set OR - // Get the whole matched element set as a clean array - get: function( num ) { - return num == null ? - - // Return a 'clean' array - this.toArray() : - - // Return just the object - ( num < 0 ? this[ this.length + num ] : this[ num ] ); - }, - - // Take an array of elements and push it onto the stack - // (returning the new matched element set) - pushStack: function( elems ) { - - // Build a new jQuery matched element set - var ret = jQuery.merge( this.constructor(), elems ); - - // Add the old object onto the stack (as a reference) - ret.prevObject = this; - ret.context = this.context; - - // Return the newly-formed element set - return ret; - }, - - // Execute a callback for every element in the matched set. - // (You can seed the arguments with an array of args, but this is - // only used internally.) - each: function( callback, args ) { - return jQuery.each( this, callback, args ); - }, - - ready: function( fn ) { - // Add the callback - jQuery.ready.promise().done( fn ); - - return this; - }, - - slice: function() { - return this.pushStack( core_slice.apply( this, arguments ) ); - }, - - first: function() { - return this.eq( 0 ); - }, - - last: function() { - return this.eq( -1 ); - }, - - eq: function( i ) { - var len = this.length, - j = +i + ( i < 0 ? len : 0 ); - return this.pushStack( j >= 0 && j < len ? [ this[j] ] : [] ); - }, - - map: function( callback ) { - return this.pushStack( jQuery.map(this, function( elem, i ) { - return callback.call( elem, i, elem ); - })); - }, - - end: function() { - return this.prevObject || this.constructor(null); - }, - - // For internal use only. - // Behaves like an Array's method, not like a jQuery method. - push: core_push, - sort: [].sort, - splice: [].splice -}; - -// Give the init function the jQuery prototype for later instantiation -jQuery.fn.init.prototype = jQuery.fn; - -jQuery.extend = jQuery.fn.extend = function() { - var src, copyIsArray, copy, name, options, clone, - target = arguments[0] || {}, - i = 1, - length = arguments.length, - deep = false; - - // Handle a deep copy situation - if ( typeof target === "boolean" ) { - deep = target; - target = arguments[1] || {}; - // skip the boolean and the target - i = 2; - } - - // Handle case when target is a string or something (possible in deep copy) - if ( typeof target !== "object" && !jQuery.isFunction(target) ) { - target = {}; - } - - // extend jQuery itself if only one argument is passed - if ( length === i ) { - target = this; - --i; - } - - for ( ; i < length; i++ ) { - // Only deal with non-null/undefined values - if ( (options = arguments[ i ]) != null ) { - // Extend the base object - for ( name in options ) { - src = target[ name ]; - copy = options[ name ]; - - // Prevent never-ending loop - if ( target === copy ) { - continue; - } - - // Recurse if we're merging plain objects or arrays - if ( deep && copy && ( jQuery.isPlainObject(copy) || (copyIsArray = jQuery.isArray(copy)) ) ) { - if ( copyIsArray ) { - copyIsArray = false; - clone = src && jQuery.isArray(src) ? src : []; - - } else { - clone = src && jQuery.isPlainObject(src) ? src : {}; - } - - // Never move original objects, clone them - target[ name ] = jQuery.extend( deep, clone, copy ); - - // Don't bring in undefined values - } else if ( copy !== undefined ) { - target[ name ] = copy; - } - } - } - } - - // Return the modified object - return target; -}; - -jQuery.extend({ - // Unique for each copy of jQuery on the page - // Non-digits removed to match rinlinejQuery - expando: "jQuery" + ( core_version + Math.random() ).replace( /\D/g, "" ), - - noConflict: function( deep ) { - if ( window.$ === jQuery ) { - window.$ = _$; - } - - if ( deep && window.jQuery === jQuery ) { - window.jQuery = _jQuery; - } - - return jQuery; - }, - - // Is the DOM ready to be used? Set to true once it occurs. - isReady: false, - - // A counter to track how many items to wait for before - // the ready event fires. See #6781 - readyWait: 1, - - // Hold (or release) the ready event - holdReady: function( hold ) { - if ( hold ) { - jQuery.readyWait++; - } else { - jQuery.ready( true ); - } - }, - - // Handle when the DOM is ready - ready: function( wait ) { - - // Abort if there are pending holds or we're already ready - if ( wait === true ? --jQuery.readyWait : jQuery.isReady ) { - return; - } - - // Make sure body exists, at least, in case IE gets a little overzealous (ticket #5443). - if ( !document.body ) { - return setTimeout( jQuery.ready ); - } - - // Remember that the DOM is ready - jQuery.isReady = true; - - // If a normal DOM Ready event fired, decrement, and wait if need be - if ( wait !== true && --jQuery.readyWait > 0 ) { - return; - } - - // If there are functions bound, to execute - readyList.resolveWith( document, [ jQuery ] ); - - // Trigger any bound ready events - if ( jQuery.fn.trigger ) { - jQuery( document ).trigger("ready").off("ready"); - } - }, - - // See test/unit/core.js for details concerning isFunction. - // Since version 1.3, DOM methods and functions like alert - // aren't supported. They return false on IE (#2968). - isFunction: function( obj ) { - return jQuery.type(obj) === "function"; - }, - - isArray: Array.isArray || function( obj ) { - return jQuery.type(obj) === "array"; - }, - - isWindow: function( obj ) { - /* jshint eqeqeq: false */ - return obj != null && obj == obj.window; - }, - - isNumeric: function( obj ) { - return !isNaN( parseFloat(obj) ) && isFinite( obj ); - }, - - type: function( obj ) { - if ( obj == null ) { - return String( obj ); - } - return typeof obj === "object" || typeof obj === "function" ? - class2type[ core_toString.call(obj) ] || "object" : - typeof obj; - }, - - isPlainObject: function( obj ) { - var key; - - // Must be an Object. - // Because of IE, we also have to check the presence of the constructor property. - // Make sure that DOM nodes and window objects don't pass through, as well - if ( !obj || jQuery.type(obj) !== "object" || obj.nodeType || jQuery.isWindow( obj ) ) { - return false; - } - - try { - // Not own constructor property must be Object - if ( obj.constructor && - !core_hasOwn.call(obj, "constructor") && - !core_hasOwn.call(obj.constructor.prototype, "isPrototypeOf") ) { - return false; - } - } catch ( e ) { - // IE8,9 Will throw exceptions on certain host objects #9897 - return false; - } - - // Support: IE<9 - // Handle iteration over inherited properties before own properties. - if ( jQuery.support.ownLast ) { - for ( key in obj ) { - return core_hasOwn.call( obj, key ); - } - } - - // Own properties are enumerated firstly, so to speed up, - // if last one is own, then all properties are own. - for ( key in obj ) {} - - return key === undefined || core_hasOwn.call( obj, key ); - }, - - isEmptyObject: function( obj ) { - var name; - for ( name in obj ) { - return false; - } - return true; - }, - - error: function( msg ) { - throw new Error( msg ); - }, - - // data: string of html - // context (optional): If specified, the fragment will be created in this context, defaults to document - // keepScripts (optional): If true, will include scripts passed in the html string - parseHTML: function( data, context, keepScripts ) { - if ( !data || typeof data !== "string" ) { - return null; - } - if ( typeof context === "boolean" ) { - keepScripts = context; - context = false; - } - context = context || document; - - var parsed = rsingleTag.exec( data ), - scripts = !keepScripts && []; - - // Single tag - if ( parsed ) { - return [ context.createElement( parsed[1] ) ]; - } - - parsed = jQuery.buildFragment( [ data ], context, scripts ); - if ( scripts ) { - jQuery( scripts ).remove(); - } - return jQuery.merge( [], parsed.childNodes ); - }, - - parseJSON: function( data ) { - // Attempt to parse using the native JSON parser first - if ( window.JSON && window.JSON.parse ) { - return window.JSON.parse( data ); - } - - if ( data === null ) { - return data; - } - - if ( typeof data === "string" ) { - - // Make sure leading/trailing whitespace is removed (IE can't handle it) - data = jQuery.trim( data ); - - if ( data ) { - // Make sure the incoming data is actual JSON - // Logic borrowed from http://json.org/json2.js - if ( rvalidchars.test( data.replace( rvalidescape, "@" ) - .replace( rvalidtokens, "]" ) - .replace( rvalidbraces, "")) ) { - - return ( new Function( "return " + data ) )(); - } - } - } - - jQuery.error( "Invalid JSON: " + data ); - }, - - // Cross-browser xml parsing - parseXML: function( data ) { - var xml, tmp; - if ( !data || typeof data !== "string" ) { - return null; - } - try { - if ( window.DOMParser ) { // Standard - tmp = new DOMParser(); - xml = tmp.parseFromString( data , "text/xml" ); - } else { // IE - xml = new ActiveXObject( "Microsoft.XMLDOM" ); - xml.async = "false"; - xml.loadXML( data ); - } - } catch( e ) { - xml = undefined; - } - if ( !xml || !xml.documentElement || xml.getElementsByTagName( "parsererror" ).length ) { - jQuery.error( "Invalid XML: " + data ); - } - return xml; - }, - - noop: function() {}, - - // Evaluates a script in a global context - // Workarounds based on findings by Jim Driscoll - // http://weblogs.java.net/blog/driscoll/archive/2009/09/08/eval-javascript-global-context - globalEval: function( data ) { - if ( data && jQuery.trim( data ) ) { - // We use execScript on Internet Explorer - // We use an anonymous function so that context is window - // rather than jQuery in Firefox - ( window.execScript || function( data ) { - window[ "eval" ].call( window, data ); - } )( data ); - } - }, - - // Convert dashed to camelCase; used by the css and data modules - // Microsoft forgot to hump their vendor prefix (#9572) - camelCase: function( string ) { - return string.replace( rmsPrefix, "ms-" ).replace( rdashAlpha, fcamelCase ); - }, - - nodeName: function( elem, name ) { - return elem.nodeName && elem.nodeName.toLowerCase() === name.toLowerCase(); - }, - - // args is for internal usage only - each: function( obj, callback, args ) { - var value, - i = 0, - length = obj.length, - isArray = isArraylike( obj ); - - if ( args ) { - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback.apply( obj[ i ], args ); - - if ( value === false ) { - break; - } - } - } else { - for ( i in obj ) { - value = callback.apply( obj[ i ], args ); - - if ( value === false ) { - break; - } - } - } - - // A special, fast, case for the most common use of each - } else { - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback.call( obj[ i ], i, obj[ i ] ); - - if ( value === false ) { - break; - } - } - } else { - for ( i in obj ) { - value = callback.call( obj[ i ], i, obj[ i ] ); - - if ( value === false ) { - break; - } - } - } - } - - return obj; - }, - - // Use native String.trim function wherever possible - trim: core_trim && !core_trim.call("\uFEFF\xA0") ? - function( text ) { - return text == null ? - "" : - core_trim.call( text ); - } : - - // Otherwise use our own trimming functionality - function( text ) { - return text == null ? - "" : - ( text + "" ).replace( rtrim, "" ); - }, - - // results is for internal usage only - makeArray: function( arr, results ) { - var ret = results || []; - - if ( arr != null ) { - if ( isArraylike( Object(arr) ) ) { - jQuery.merge( ret, - typeof arr === "string" ? - [ arr ] : arr - ); - } else { - core_push.call( ret, arr ); - } - } - - return ret; - }, - - inArray: function( elem, arr, i ) { - var len; - - if ( arr ) { - if ( core_indexOf ) { - return core_indexOf.call( arr, elem, i ); - } - - len = arr.length; - i = i ? i < 0 ? Math.max( 0, len + i ) : i : 0; - - for ( ; i < len; i++ ) { - // Skip accessing in sparse arrays - if ( i in arr && arr[ i ] === elem ) { - return i; - } - } - } - - return -1; - }, - - merge: function( first, second ) { - var l = second.length, - i = first.length, - j = 0; - - if ( typeof l === "number" ) { - for ( ; j < l; j++ ) { - first[ i++ ] = second[ j ]; - } - } else { - while ( second[j] !== undefined ) { - first[ i++ ] = second[ j++ ]; - } - } - - first.length = i; - - return first; - }, - - grep: function( elems, callback, inv ) { - var retVal, - ret = [], - i = 0, - length = elems.length; - inv = !!inv; - - // Go through the array, only saving the items - // that pass the validator function - for ( ; i < length; i++ ) { - retVal = !!callback( elems[ i ], i ); - if ( inv !== retVal ) { - ret.push( elems[ i ] ); - } - } - - return ret; - }, - - // arg is for internal usage only - map: function( elems, callback, arg ) { - var value, - i = 0, - length = elems.length, - isArray = isArraylike( elems ), - ret = []; - - // Go through the array, translating each of the items to their - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback( elems[ i ], i, arg ); - - if ( value != null ) { - ret[ ret.length ] = value; - } - } - - // Go through every key on the object, - } else { - for ( i in elems ) { - value = callback( elems[ i ], i, arg ); - - if ( value != null ) { - ret[ ret.length ] = value; - } - } - } - - // Flatten any nested arrays - return core_concat.apply( [], ret ); - }, - - // A global GUID counter for objects - guid: 1, - - // Bind a function to a context, optionally partially applying any - // arguments. - proxy: function( fn, context ) { - var args, proxy, tmp; - - if ( typeof context === "string" ) { - tmp = fn[ context ]; - context = fn; - fn = tmp; - } - - // Quick check to determine if target is callable, in the spec - // this throws a TypeError, but we will just return undefined. - if ( !jQuery.isFunction( fn ) ) { - return undefined; - } - - // Simulated bind - args = core_slice.call( arguments, 2 ); - proxy = function() { - return fn.apply( context || this, args.concat( core_slice.call( arguments ) ) ); - }; - - // Set the guid of unique handler to the same of original handler, so it can be removed - proxy.guid = fn.guid = fn.guid || jQuery.guid++; - - return proxy; - }, - - // Multifunctional method to get and set values of a collection - // The value/s can optionally be executed if it's a function - access: function( elems, fn, key, value, chainable, emptyGet, raw ) { - var i = 0, - length = elems.length, - bulk = key == null; - - // Sets many values - if ( jQuery.type( key ) === "object" ) { - chainable = true; - for ( i in key ) { - jQuery.access( elems, fn, i, key[i], true, emptyGet, raw ); - } - - // Sets one value - } else if ( value !== undefined ) { - chainable = true; - - if ( !jQuery.isFunction( value ) ) { - raw = true; - } - - if ( bulk ) { - // Bulk operations run against the entire set - if ( raw ) { - fn.call( elems, value ); - fn = null; - - // ...except when executing function values - } else { - bulk = fn; - fn = function( elem, key, value ) { - return bulk.call( jQuery( elem ), value ); - }; - } - } - - if ( fn ) { - for ( ; i < length; i++ ) { - fn( elems[i], key, raw ? value : value.call( elems[i], i, fn( elems[i], key ) ) ); - } - } - } - - return chainable ? - elems : - - // Gets - bulk ? - fn.call( elems ) : - length ? fn( elems[0], key ) : emptyGet; - }, - - now: function() { - return ( new Date() ).getTime(); - }, - - // A method for quickly swapping in/out CSS properties to get correct calculations. - // Note: this method belongs to the css module but it's needed here for the support module. - // If support gets modularized, this method should be moved back to the css module. - swap: function( elem, options, callback, args ) { - var ret, name, - old = {}; - - // Remember the old values, and insert the new ones - for ( name in options ) { - old[ name ] = elem.style[ name ]; - elem.style[ name ] = options[ name ]; - } - - ret = callback.apply( elem, args || [] ); - - // Revert the old values - for ( name in options ) { - elem.style[ name ] = old[ name ]; - } - - return ret; - } -}); - -jQuery.ready.promise = function( obj ) { - if ( !readyList ) { - - readyList = jQuery.Deferred(); - - // Catch cases where $(document).ready() is called after the browser event has already occurred. - // we once tried to use readyState "interactive" here, but it caused issues like the one - // discovered by ChrisS here: http://bugs.jquery.com/ticket/12282#comment:15 - if ( document.readyState === "complete" ) { - // Handle it asynchronously to allow scripts the opportunity to delay ready - setTimeout( jQuery.ready ); - - // Standards-based browsers support DOMContentLoaded - } else if ( document.addEventListener ) { - // Use the handy event callback - document.addEventListener( "DOMContentLoaded", completed, false ); - - // A fallback to window.onload, that will always work - window.addEventListener( "load", completed, false ); - - // If IE event model is used - } else { - // Ensure firing before onload, maybe late but safe also for iframes - document.attachEvent( "onreadystatechange", completed ); - - // A fallback to window.onload, that will always work - window.attachEvent( "onload", completed ); - - // If IE and not a frame - // continually check to see if the document is ready - var top = false; - - try { - top = window.frameElement == null && document.documentElement; - } catch(e) {} - - if ( top && top.doScroll ) { - (function doScrollCheck() { - if ( !jQuery.isReady ) { - - try { - // Use the trick by Diego Perini - // http://javascript.nwbox.com/IEContentLoaded/ - top.doScroll("left"); - } catch(e) { - return setTimeout( doScrollCheck, 50 ); - } - - // detach all dom ready events - detach(); - - // and execute any waiting functions - jQuery.ready(); - } - })(); - } - } - } - return readyList.promise( obj ); -}; - -// Populate the class2type map -jQuery.each("Boolean Number String Function Array Date RegExp Object Error".split(" "), function(i, name) { - class2type[ "[object " + name + "]" ] = name.toLowerCase(); -}); - -function isArraylike( obj ) { - var length = obj.length, - type = jQuery.type( obj ); - - if ( jQuery.isWindow( obj ) ) { - return false; - } - - if ( obj.nodeType === 1 && length ) { - return true; - } - - return type === "array" || type !== "function" && - ( length === 0 || - typeof length === "number" && length > 0 && ( length - 1 ) in obj ); -} - -// All jQuery objects should point back to these -rootjQuery = jQuery(document); -/*! - * Sizzle CSS Selector Engine v1.10.2 - * http://sizzlejs.com/ - * - * Copyright 2013 jQuery Foundation, Inc. and other contributors - * Released under the MIT license - * http://jquery.org/license - * - * Date: 2013-07-03 - */ -(function( window, undefined ) { - -var i, - support, - cachedruns, - Expr, - getText, - isXML, - compile, - outermostContext, - sortInput, - - // Local document vars - setDocument, - document, - docElem, - documentIsHTML, - rbuggyQSA, - rbuggyMatches, - matches, - contains, - - // Instance-specific data - expando = "sizzle" + -(new Date()), - preferredDoc = window.document, - dirruns = 0, - done = 0, - classCache = createCache(), - tokenCache = createCache(), - compilerCache = createCache(), - hasDuplicate = false, - sortOrder = function( a, b ) { - if ( a === b ) { - hasDuplicate = true; - return 0; - } - return 0; - }, - - // General-purpose constants - strundefined = typeof undefined, - MAX_NEGATIVE = 1 << 31, - - // Instance methods - hasOwn = ({}).hasOwnProperty, - arr = [], - pop = arr.pop, - push_native = arr.push, - push = arr.push, - slice = arr.slice, - // Use a stripped-down indexOf if we can't use a native one - indexOf = arr.indexOf || function( elem ) { - var i = 0, - len = this.length; - for ( ; i < len; i++ ) { - if ( this[i] === elem ) { - return i; - } - } - return -1; - }, - - booleans = "checked|selected|async|autofocus|autoplay|controls|defer|disabled|hidden|ismap|loop|multiple|open|readonly|required|scoped", - - // Regular expressions - - // Whitespace characters http://www.w3.org/TR/css3-selectors/#whitespace - whitespace = "[\\x20\\t\\r\\n\\f]", - // http://www.w3.org/TR/css3-syntax/#characters - characterEncoding = "(?:\\\\.|[\\w-]|[^\\x00-\\xa0])+", - - // Loosely modeled on CSS identifier characters - // An unquoted value should be a CSS identifier http://www.w3.org/TR/css3-selectors/#attribute-selectors - // Proper syntax: http://www.w3.org/TR/CSS21/syndata.html#value-def-identifier - identifier = characterEncoding.replace( "w", "w#" ), - - // Acceptable operators http://www.w3.org/TR/selectors/#attribute-selectors - attributes = "\\[" + whitespace + "*(" + characterEncoding + ")" + whitespace + - "*(?:([*^$|!~]?=)" + whitespace + "*(?:(['\"])((?:\\\\.|[^\\\\])*?)\\3|(" + identifier + ")|)|)" + whitespace + "*\\]", - - // Prefer arguments quoted, - // then not containing pseudos/brackets, - // then attribute selectors/non-parenthetical expressions, - // then anything else - // These preferences are here to reduce the number of selectors - // needing tokenize in the PSEUDO preFilter - pseudos = ":(" + characterEncoding + ")(?:\\(((['\"])((?:\\\\.|[^\\\\])*?)\\3|((?:\\\\.|[^\\\\()[\\]]|" + attributes.replace( 3, 8 ) + ")*)|.*)\\)|)", - - // Leading and non-escaped trailing whitespace, capturing some non-whitespace characters preceding the latter - rtrim = new RegExp( "^" + whitespace + "+|((?:^|[^\\\\])(?:\\\\.)*)" + whitespace + "+$", "g" ), - - rcomma = new RegExp( "^" + whitespace + "*," + whitespace + "*" ), - rcombinators = new RegExp( "^" + whitespace + "*([>+~]|" + whitespace + ")" + whitespace + "*" ), - - rsibling = new RegExp( whitespace + "*[+~]" ), - rattributeQuotes = new RegExp( "=" + whitespace + "*([^\\]'\"]*)" + whitespace + "*\\]", "g" ), - - rpseudo = new RegExp( pseudos ), - ridentifier = new RegExp( "^" + identifier + "$" ), - - matchExpr = { - "ID": new RegExp( "^#(" + characterEncoding + ")" ), - "CLASS": new RegExp( "^\\.(" + characterEncoding + ")" ), - "TAG": new RegExp( "^(" + characterEncoding.replace( "w", "w*" ) + ")" ), - "ATTR": new RegExp( "^" + attributes ), - "PSEUDO": new RegExp( "^" + pseudos ), - "CHILD": new RegExp( "^:(only|first|last|nth|nth-last)-(child|of-type)(?:\\(" + whitespace + - "*(even|odd|(([+-]|)(\\d*)n|)" + whitespace + "*(?:([+-]|)" + whitespace + - "*(\\d+)|))" + whitespace + "*\\)|)", "i" ), - "bool": new RegExp( "^(?:" + booleans + ")$", "i" ), - // For use in libraries implementing .is() - // We use this for POS matching in `select` - "needsContext": new RegExp( "^" + whitespace + "*[>+~]|:(even|odd|eq|gt|lt|nth|first|last)(?:\\(" + - whitespace + "*((?:-\\d)?\\d*)" + whitespace + "*\\)|)(?=[^-]|$)", "i" ) - }, - - rnative = /^[^{]+\{\s*\[native \w/, - - // Easily-parseable/retrievable ID or TAG or CLASS selectors - rquickExpr = /^(?:#([\w-]+)|(\w+)|\.([\w-]+))$/, - - rinputs = /^(?:input|select|textarea|button)$/i, - rheader = /^h\d$/i, - - rescape = /'|\\/g, - - // CSS escapes http://www.w3.org/TR/CSS21/syndata.html#escaped-characters - runescape = new RegExp( "\\\\([\\da-f]{1,6}" + whitespace + "?|(" + whitespace + ")|.)", "ig" ), - funescape = function( _, escaped, escapedWhitespace ) { - var high = "0x" + escaped - 0x10000; - // NaN means non-codepoint - // Support: Firefox - // Workaround erroneous numeric interpretation of +"0x" - return high !== high || escapedWhitespace ? - escaped : - // BMP codepoint - high < 0 ? - String.fromCharCode( high + 0x10000 ) : - // Supplemental Plane codepoint (surrogate pair) - String.fromCharCode( high >> 10 | 0xD800, high & 0x3FF | 0xDC00 ); - }; - -// Optimize for push.apply( _, NodeList ) -try { - push.apply( - (arr = slice.call( preferredDoc.childNodes )), - preferredDoc.childNodes - ); - // Support: Android<4.0 - // Detect silently failing push.apply - arr[ preferredDoc.childNodes.length ].nodeType; -} catch ( e ) { - push = { apply: arr.length ? - - // Leverage slice if possible - function( target, els ) { - push_native.apply( target, slice.call(els) ); - } : - - // Support: IE<9 - // Otherwise append directly - function( target, els ) { - var j = target.length, - i = 0; - // Can't trust NodeList.length - while ( (target[j++] = els[i++]) ) {} - target.length = j - 1; - } - }; -} - -function Sizzle( selector, context, results, seed ) { - var match, elem, m, nodeType, - // QSA vars - i, groups, old, nid, newContext, newSelector; - - if ( ( context ? context.ownerDocument || context : preferredDoc ) !== document ) { - setDocument( context ); - } - - context = context || document; - results = results || []; - - if ( !selector || typeof selector !== "string" ) { - return results; - } - - if ( (nodeType = context.nodeType) !== 1 && nodeType !== 9 ) { - return []; - } - - if ( documentIsHTML && !seed ) { - - // Shortcuts - if ( (match = rquickExpr.exec( selector )) ) { - // Speed-up: Sizzle("#ID") - if ( (m = match[1]) ) { - if ( nodeType === 9 ) { - elem = context.getElementById( m ); - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - if ( elem && elem.parentNode ) { - // Handle the case where IE, Opera, and Webkit return items - // by name instead of ID - if ( elem.id === m ) { - results.push( elem ); - return results; - } - } else { - return results; - } - } else { - // Context is not a document - if ( context.ownerDocument && (elem = context.ownerDocument.getElementById( m )) && - contains( context, elem ) && elem.id === m ) { - results.push( elem ); - return results; - } - } - - // Speed-up: Sizzle("TAG") - } else if ( match[2] ) { - push.apply( results, context.getElementsByTagName( selector ) ); - return results; - - // Speed-up: Sizzle(".CLASS") - } else if ( (m = match[3]) && support.getElementsByClassName && context.getElementsByClassName ) { - push.apply( results, context.getElementsByClassName( m ) ); - return results; - } - } - - // QSA path - if ( support.qsa && (!rbuggyQSA || !rbuggyQSA.test( selector )) ) { - nid = old = expando; - newContext = context; - newSelector = nodeType === 9 && selector; - - // qSA works strangely on Element-rooted queries - // We can work around this by specifying an extra ID on the root - // and working up from there (Thanks to Andrew Dupont for the technique) - // IE 8 doesn't work on object elements - if ( nodeType === 1 && context.nodeName.toLowerCase() !== "object" ) { - groups = tokenize( selector ); - - if ( (old = context.getAttribute("id")) ) { - nid = old.replace( rescape, "\\$&" ); - } else { - context.setAttribute( "id", nid ); - } - nid = "[id='" + nid + "'] "; - - i = groups.length; - while ( i-- ) { - groups[i] = nid + toSelector( groups[i] ); - } - newContext = rsibling.test( selector ) && context.parentNode || context; - newSelector = groups.join(","); - } - - if ( newSelector ) { - try { - push.apply( results, - newContext.querySelectorAll( newSelector ) - ); - return results; - } catch(qsaError) { - } finally { - if ( !old ) { - context.removeAttribute("id"); - } - } - } - } - } - - // All others - return select( selector.replace( rtrim, "$1" ), context, results, seed ); -} - -/** - * Create key-value caches of limited size - * @returns {Function(string, Object)} Returns the Object data after storing it on itself with - * property name the (space-suffixed) string and (if the cache is larger than Expr.cacheLength) - * deleting the oldest entry - */ -function createCache() { - var keys = []; - - function cache( key, value ) { - // Use (key + " ") to avoid collision with native prototype properties (see Issue #157) - if ( keys.push( key += " " ) > Expr.cacheLength ) { - // Only keep the most recent entries - delete cache[ keys.shift() ]; - } - return (cache[ key ] = value); - } - return cache; -} - -/** - * Mark a function for special use by Sizzle - * @param {Function} fn The function to mark - */ -function markFunction( fn ) { - fn[ expando ] = true; - return fn; -} - -/** - * Support testing using an element - * @param {Function} fn Passed the created div and expects a boolean result - */ -function assert( fn ) { - var div = document.createElement("div"); - - try { - return !!fn( div ); - } catch (e) { - return false; - } finally { - // Remove from its parent by default - if ( div.parentNode ) { - div.parentNode.removeChild( div ); - } - // release memory in IE - div = null; - } -} - -/** - * Adds the same handler for all of the specified attrs - * @param {String} attrs Pipe-separated list of attributes - * @param {Function} handler The method that will be applied - */ -function addHandle( attrs, handler ) { - var arr = attrs.split("|"), - i = attrs.length; - - while ( i-- ) { - Expr.attrHandle[ arr[i] ] = handler; - } -} - -/** - * Checks document order of two siblings - * @param {Element} a - * @param {Element} b - * @returns {Number} Returns less than 0 if a precedes b, greater than 0 if a follows b - */ -function siblingCheck( a, b ) { - var cur = b && a, - diff = cur && a.nodeType === 1 && b.nodeType === 1 && - ( ~b.sourceIndex || MAX_NEGATIVE ) - - ( ~a.sourceIndex || MAX_NEGATIVE ); - - // Use IE sourceIndex if available on both nodes - if ( diff ) { - return diff; - } - - // Check if b follows a - if ( cur ) { - while ( (cur = cur.nextSibling) ) { - if ( cur === b ) { - return -1; - } - } - } - - return a ? 1 : -1; -} - -/** - * Returns a function to use in pseudos for input types - * @param {String} type - */ -function createInputPseudo( type ) { - return function( elem ) { - var name = elem.nodeName.toLowerCase(); - return name === "input" && elem.type === type; - }; -} - -/** - * Returns a function to use in pseudos for buttons - * @param {String} type - */ -function createButtonPseudo( type ) { - return function( elem ) { - var name = elem.nodeName.toLowerCase(); - return (name === "input" || name === "button") && elem.type === type; - }; -} - -/** - * Returns a function to use in pseudos for positionals - * @param {Function} fn - */ -function createPositionalPseudo( fn ) { - return markFunction(function( argument ) { - argument = +argument; - return markFunction(function( seed, matches ) { - var j, - matchIndexes = fn( [], seed.length, argument ), - i = matchIndexes.length; - - // Match elements found at the specified indexes - while ( i-- ) { - if ( seed[ (j = matchIndexes[i]) ] ) { - seed[j] = !(matches[j] = seed[j]); - } - } - }); - }); -} - -/** - * Detect xml - * @param {Element|Object} elem An element or a document - */ -isXML = Sizzle.isXML = function( elem ) { - // documentElement is verified for cases where it doesn't yet exist - // (such as loading iframes in IE - #4833) - var documentElement = elem && (elem.ownerDocument || elem).documentElement; - return documentElement ? documentElement.nodeName !== "HTML" : false; -}; - -// Expose support vars for convenience -support = Sizzle.support = {}; - -/** - * Sets document-related variables once based on the current document - * @param {Element|Object} [doc] An element or document object to use to set the document - * @returns {Object} Returns the current document - */ -setDocument = Sizzle.setDocument = function( node ) { - var doc = node ? node.ownerDocument || node : preferredDoc, - parent = doc.defaultView; - - // If no document and documentElement is available, return - if ( doc === document || doc.nodeType !== 9 || !doc.documentElement ) { - return document; - } - - // Set our document - document = doc; - docElem = doc.documentElement; - - // Support tests - documentIsHTML = !isXML( doc ); - - // Support: IE>8 - // If iframe document is assigned to "document" variable and if iframe has been reloaded, - // IE will throw "permission denied" error when accessing "document" variable, see jQuery #13936 - // IE6-8 do not support the defaultView property so parent will be undefined - if ( parent && parent.attachEvent && parent !== parent.top ) { - parent.attachEvent( "onbeforeunload", function() { - setDocument(); - }); - } - - /* Attributes - ---------------------------------------------------------------------- */ - - // Support: IE<8 - // Verify that getAttribute really returns attributes and not properties (excepting IE8 booleans) - support.attributes = assert(function( div ) { - div.className = "i"; - return !div.getAttribute("className"); - }); - - /* getElement(s)By* - ---------------------------------------------------------------------- */ - - // Check if getElementsByTagName("*") returns only elements - support.getElementsByTagName = assert(function( div ) { - div.appendChild( doc.createComment("") ); - return !div.getElementsByTagName("*").length; - }); - - // Check if getElementsByClassName can be trusted - support.getElementsByClassName = assert(function( div ) { - div.innerHTML = "
"; - - // Support: Safari<4 - // Catch class over-caching - div.firstChild.className = "i"; - // Support: Opera<10 - // Catch gEBCN failure to find non-leading classes - return div.getElementsByClassName("i").length === 2; - }); - - // Support: IE<10 - // Check if getElementById returns elements by name - // The broken getElementById methods don't pick up programatically-set names, - // so use a roundabout getElementsByName test - support.getById = assert(function( div ) { - docElem.appendChild( div ).id = expando; - return !doc.getElementsByName || !doc.getElementsByName( expando ).length; - }); - - // ID find and filter - if ( support.getById ) { - Expr.find["ID"] = function( id, context ) { - if ( typeof context.getElementById !== strundefined && documentIsHTML ) { - var m = context.getElementById( id ); - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - return m && m.parentNode ? [m] : []; - } - }; - Expr.filter["ID"] = function( id ) { - var attrId = id.replace( runescape, funescape ); - return function( elem ) { - return elem.getAttribute("id") === attrId; - }; - }; - } else { - // Support: IE6/7 - // getElementById is not reliable as a find shortcut - delete Expr.find["ID"]; - - Expr.filter["ID"] = function( id ) { - var attrId = id.replace( runescape, funescape ); - return function( elem ) { - var node = typeof elem.getAttributeNode !== strundefined && elem.getAttributeNode("id"); - return node && node.value === attrId; - }; - }; - } - - // Tag - Expr.find["TAG"] = support.getElementsByTagName ? - function( tag, context ) { - if ( typeof context.getElementsByTagName !== strundefined ) { - return context.getElementsByTagName( tag ); - } - } : - function( tag, context ) { - var elem, - tmp = [], - i = 0, - results = context.getElementsByTagName( tag ); - - // Filter out possible comments - if ( tag === "*" ) { - while ( (elem = results[i++]) ) { - if ( elem.nodeType === 1 ) { - tmp.push( elem ); - } - } - - return tmp; - } - return results; - }; - - // Class - Expr.find["CLASS"] = support.getElementsByClassName && function( className, context ) { - if ( typeof context.getElementsByClassName !== strundefined && documentIsHTML ) { - return context.getElementsByClassName( className ); - } - }; - - /* QSA/matchesSelector - ---------------------------------------------------------------------- */ - - // QSA and matchesSelector support - - // matchesSelector(:active) reports false when true (IE9/Opera 11.5) - rbuggyMatches = []; - - // qSa(:focus) reports false when true (Chrome 21) - // We allow this because of a bug in IE8/9 that throws an error - // whenever `document.activeElement` is accessed on an iframe - // So, we allow :focus to pass through QSA all the time to avoid the IE error - // See http://bugs.jquery.com/ticket/13378 - rbuggyQSA = []; - - if ( (support.qsa = rnative.test( doc.querySelectorAll )) ) { - // Build QSA regex - // Regex strategy adopted from Diego Perini - assert(function( div ) { - // Select is set to empty string on purpose - // This is to test IE's treatment of not explicitly - // setting a boolean content attribute, - // since its presence should be enough - // http://bugs.jquery.com/ticket/12359 - div.innerHTML = ""; - - // Support: IE8 - // Boolean attributes and "value" are not treated correctly - if ( !div.querySelectorAll("[selected]").length ) { - rbuggyQSA.push( "\\[" + whitespace + "*(?:value|" + booleans + ")" ); - } - - // Webkit/Opera - :checked should return selected option elements - // http://www.w3.org/TR/2011/REC-css3-selectors-20110929/#checked - // IE8 throws error here and will not see later tests - if ( !div.querySelectorAll(":checked").length ) { - rbuggyQSA.push(":checked"); - } - }); - - assert(function( div ) { - - // Support: Opera 10-12/IE8 - // ^= $= *= and empty values - // Should not select anything - // Support: Windows 8 Native Apps - // The type attribute is restricted during .innerHTML assignment - var input = doc.createElement("input"); - input.setAttribute( "type", "hidden" ); - div.appendChild( input ).setAttribute( "t", "" ); - - if ( div.querySelectorAll("[t^='']").length ) { - rbuggyQSA.push( "[*^$]=" + whitespace + "*(?:''|\"\")" ); - } - - // FF 3.5 - :enabled/:disabled and hidden elements (hidden elements are still enabled) - // IE8 throws error here and will not see later tests - if ( !div.querySelectorAll(":enabled").length ) { - rbuggyQSA.push( ":enabled", ":disabled" ); - } - - // Opera 10-11 does not throw on post-comma invalid pseudos - div.querySelectorAll("*,:x"); - rbuggyQSA.push(",.*:"); - }); - } - - if ( (support.matchesSelector = rnative.test( (matches = docElem.webkitMatchesSelector || - docElem.mozMatchesSelector || - docElem.oMatchesSelector || - docElem.msMatchesSelector) )) ) { - - assert(function( div ) { - // Check to see if it's possible to do matchesSelector - // on a disconnected node (IE 9) - support.disconnectedMatch = matches.call( div, "div" ); - - // This should fail with an exception - // Gecko does not error, returns false instead - matches.call( div, "[s!='']:x" ); - rbuggyMatches.push( "!=", pseudos ); - }); - } - - rbuggyQSA = rbuggyQSA.length && new RegExp( rbuggyQSA.join("|") ); - rbuggyMatches = rbuggyMatches.length && new RegExp( rbuggyMatches.join("|") ); - - /* Contains - ---------------------------------------------------------------------- */ - - // Element contains another - // Purposefully does not implement inclusive descendent - // As in, an element does not contain itself - contains = rnative.test( docElem.contains ) || docElem.compareDocumentPosition ? - function( a, b ) { - var adown = a.nodeType === 9 ? a.documentElement : a, - bup = b && b.parentNode; - return a === bup || !!( bup && bup.nodeType === 1 && ( - adown.contains ? - adown.contains( bup ) : - a.compareDocumentPosition && a.compareDocumentPosition( bup ) & 16 - )); - } : - function( a, b ) { - if ( b ) { - while ( (b = b.parentNode) ) { - if ( b === a ) { - return true; - } - } - } - return false; - }; - - /* Sorting - ---------------------------------------------------------------------- */ - - // Document order sorting - sortOrder = docElem.compareDocumentPosition ? - function( a, b ) { - - // Flag for duplicate removal - if ( a === b ) { - hasDuplicate = true; - return 0; - } - - var compare = b.compareDocumentPosition && a.compareDocumentPosition && a.compareDocumentPosition( b ); - - if ( compare ) { - // Disconnected nodes - if ( compare & 1 || - (!support.sortDetached && b.compareDocumentPosition( a ) === compare) ) { - - // Choose the first element that is related to our preferred document - if ( a === doc || contains(preferredDoc, a) ) { - return -1; - } - if ( b === doc || contains(preferredDoc, b) ) { - return 1; - } - - // Maintain original order - return sortInput ? - ( indexOf.call( sortInput, a ) - indexOf.call( sortInput, b ) ) : - 0; - } - - return compare & 4 ? -1 : 1; - } - - // Not directly comparable, sort on existence of method - return a.compareDocumentPosition ? -1 : 1; - } : - function( a, b ) { - var cur, - i = 0, - aup = a.parentNode, - bup = b.parentNode, - ap = [ a ], - bp = [ b ]; - - // Exit early if the nodes are identical - if ( a === b ) { - hasDuplicate = true; - return 0; - - // Parentless nodes are either documents or disconnected - } else if ( !aup || !bup ) { - return a === doc ? -1 : - b === doc ? 1 : - aup ? -1 : - bup ? 1 : - sortInput ? - ( indexOf.call( sortInput, a ) - indexOf.call( sortInput, b ) ) : - 0; - - // If the nodes are siblings, we can do a quick check - } else if ( aup === bup ) { - return siblingCheck( a, b ); - } - - // Otherwise we need full lists of their ancestors for comparison - cur = a; - while ( (cur = cur.parentNode) ) { - ap.unshift( cur ); - } - cur = b; - while ( (cur = cur.parentNode) ) { - bp.unshift( cur ); - } - - // Walk down the tree looking for a discrepancy - while ( ap[i] === bp[i] ) { - i++; - } - - return i ? - // Do a sibling check if the nodes have a common ancestor - siblingCheck( ap[i], bp[i] ) : - - // Otherwise nodes in our document sort first - ap[i] === preferredDoc ? -1 : - bp[i] === preferredDoc ? 1 : - 0; - }; - - return doc; -}; - -Sizzle.matches = function( expr, elements ) { - return Sizzle( expr, null, null, elements ); -}; - -Sizzle.matchesSelector = function( elem, expr ) { - // Set document vars if needed - if ( ( elem.ownerDocument || elem ) !== document ) { - setDocument( elem ); - } - - // Make sure that attribute selectors are quoted - expr = expr.replace( rattributeQuotes, "='$1']" ); - - if ( support.matchesSelector && documentIsHTML && - ( !rbuggyMatches || !rbuggyMatches.test( expr ) ) && - ( !rbuggyQSA || !rbuggyQSA.test( expr ) ) ) { - - try { - var ret = matches.call( elem, expr ); - - // IE 9's matchesSelector returns false on disconnected nodes - if ( ret || support.disconnectedMatch || - // As well, disconnected nodes are said to be in a document - // fragment in IE 9 - elem.document && elem.document.nodeType !== 11 ) { - return ret; - } - } catch(e) {} - } - - return Sizzle( expr, document, null, [elem] ).length > 0; -}; - -Sizzle.contains = function( context, elem ) { - // Set document vars if needed - if ( ( context.ownerDocument || context ) !== document ) { - setDocument( context ); - } - return contains( context, elem ); -}; - -Sizzle.attr = function( elem, name ) { - // Set document vars if needed - if ( ( elem.ownerDocument || elem ) !== document ) { - setDocument( elem ); - } - - var fn = Expr.attrHandle[ name.toLowerCase() ], - // Don't get fooled by Object.prototype properties (jQuery #13807) - val = fn && hasOwn.call( Expr.attrHandle, name.toLowerCase() ) ? - fn( elem, name, !documentIsHTML ) : - undefined; - - return val === undefined ? - support.attributes || !documentIsHTML ? - elem.getAttribute( name ) : - (val = elem.getAttributeNode(name)) && val.specified ? - val.value : - null : - val; -}; - -Sizzle.error = function( msg ) { - throw new Error( "Syntax error, unrecognized expression: " + msg ); -}; - -/** - * Document sorting and removing duplicates - * @param {ArrayLike} results - */ -Sizzle.uniqueSort = function( results ) { - var elem, - duplicates = [], - j = 0, - i = 0; - - // Unless we *know* we can detect duplicates, assume their presence - hasDuplicate = !support.detectDuplicates; - sortInput = !support.sortStable && results.slice( 0 ); - results.sort( sortOrder ); - - if ( hasDuplicate ) { - while ( (elem = results[i++]) ) { - if ( elem === results[ i ] ) { - j = duplicates.push( i ); - } - } - while ( j-- ) { - results.splice( duplicates[ j ], 1 ); - } - } - - return results; -}; - -/** - * Utility function for retrieving the text value of an array of DOM nodes - * @param {Array|Element} elem - */ -getText = Sizzle.getText = function( elem ) { - var node, - ret = "", - i = 0, - nodeType = elem.nodeType; - - if ( !nodeType ) { - // If no nodeType, this is expected to be an array - for ( ; (node = elem[i]); i++ ) { - // Do not traverse comment nodes - ret += getText( node ); - } - } else if ( nodeType === 1 || nodeType === 9 || nodeType === 11 ) { - // Use textContent for elements - // innerText usage removed for consistency of new lines (see #11153) - if ( typeof elem.textContent === "string" ) { - return elem.textContent; - } else { - // Traverse its children - for ( elem = elem.firstChild; elem; elem = elem.nextSibling ) { - ret += getText( elem ); - } - } - } else if ( nodeType === 3 || nodeType === 4 ) { - return elem.nodeValue; - } - // Do not include comment or processing instruction nodes - - return ret; -}; - -Expr = Sizzle.selectors = { - - // Can be adjusted by the user - cacheLength: 50, - - createPseudo: markFunction, - - match: matchExpr, - - attrHandle: {}, - - find: {}, - - relative: { - ">": { dir: "parentNode", first: true }, - " ": { dir: "parentNode" }, - "+": { dir: "previousSibling", first: true }, - "~": { dir: "previousSibling" } - }, - - preFilter: { - "ATTR": function( match ) { - match[1] = match[1].replace( runescape, funescape ); - - // Move the given value to match[3] whether quoted or unquoted - match[3] = ( match[4] || match[5] || "" ).replace( runescape, funescape ); - - if ( match[2] === "~=" ) { - match[3] = " " + match[3] + " "; - } - - return match.slice( 0, 4 ); - }, - - "CHILD": function( match ) { - /* matches from matchExpr["CHILD"] - 1 type (only|nth|...) - 2 what (child|of-type) - 3 argument (even|odd|\d*|\d*n([+-]\d+)?|...) - 4 xn-component of xn+y argument ([+-]?\d*n|) - 5 sign of xn-component - 6 x of xn-component - 7 sign of y-component - 8 y of y-component - */ - match[1] = match[1].toLowerCase(); - - if ( match[1].slice( 0, 3 ) === "nth" ) { - // nth-* requires argument - if ( !match[3] ) { - Sizzle.error( match[0] ); - } - - // numeric x and y parameters for Expr.filter.CHILD - // remember that false/true cast respectively to 0/1 - match[4] = +( match[4] ? match[5] + (match[6] || 1) : 2 * ( match[3] === "even" || match[3] === "odd" ) ); - match[5] = +( ( match[7] + match[8] ) || match[3] === "odd" ); - - // other types prohibit arguments - } else if ( match[3] ) { - Sizzle.error( match[0] ); - } - - return match; - }, - - "PSEUDO": function( match ) { - var excess, - unquoted = !match[5] && match[2]; - - if ( matchExpr["CHILD"].test( match[0] ) ) { - return null; - } - - // Accept quoted arguments as-is - if ( match[3] && match[4] !== undefined ) { - match[2] = match[4]; - - // Strip excess characters from unquoted arguments - } else if ( unquoted && rpseudo.test( unquoted ) && - // Get excess from tokenize (recursively) - (excess = tokenize( unquoted, true )) && - // advance to the next closing parenthesis - (excess = unquoted.indexOf( ")", unquoted.length - excess ) - unquoted.length) ) { - - // excess is a negative index - match[0] = match[0].slice( 0, excess ); - match[2] = unquoted.slice( 0, excess ); - } - - // Return only captures needed by the pseudo filter method (type and argument) - return match.slice( 0, 3 ); - } - }, - - filter: { - - "TAG": function( nodeNameSelector ) { - var nodeName = nodeNameSelector.replace( runescape, funescape ).toLowerCase(); - return nodeNameSelector === "*" ? - function() { return true; } : - function( elem ) { - return elem.nodeName && elem.nodeName.toLowerCase() === nodeName; - }; - }, - - "CLASS": function( className ) { - var pattern = classCache[ className + " " ]; - - return pattern || - (pattern = new RegExp( "(^|" + whitespace + ")" + className + "(" + whitespace + "|$)" )) && - classCache( className, function( elem ) { - return pattern.test( typeof elem.className === "string" && elem.className || typeof elem.getAttribute !== strundefined && elem.getAttribute("class") || "" ); - }); - }, - - "ATTR": function( name, operator, check ) { - return function( elem ) { - var result = Sizzle.attr( elem, name ); - - if ( result == null ) { - return operator === "!="; - } - if ( !operator ) { - return true; - } - - result += ""; - - return operator === "=" ? result === check : - operator === "!=" ? result !== check : - operator === "^=" ? check && result.indexOf( check ) === 0 : - operator === "*=" ? check && result.indexOf( check ) > -1 : - operator === "$=" ? check && result.slice( -check.length ) === check : - operator === "~=" ? ( " " + result + " " ).indexOf( check ) > -1 : - operator === "|=" ? result === check || result.slice( 0, check.length + 1 ) === check + "-" : - false; - }; - }, - - "CHILD": function( type, what, argument, first, last ) { - var simple = type.slice( 0, 3 ) !== "nth", - forward = type.slice( -4 ) !== "last", - ofType = what === "of-type"; - - return first === 1 && last === 0 ? - - // Shortcut for :nth-*(n) - function( elem ) { - return !!elem.parentNode; - } : - - function( elem, context, xml ) { - var cache, outerCache, node, diff, nodeIndex, start, - dir = simple !== forward ? "nextSibling" : "previousSibling", - parent = elem.parentNode, - name = ofType && elem.nodeName.toLowerCase(), - useCache = !xml && !ofType; - - if ( parent ) { - - // :(first|last|only)-(child|of-type) - if ( simple ) { - while ( dir ) { - node = elem; - while ( (node = node[ dir ]) ) { - if ( ofType ? node.nodeName.toLowerCase() === name : node.nodeType === 1 ) { - return false; - } - } - // Reverse direction for :only-* (if we haven't yet done so) - start = dir = type === "only" && !start && "nextSibling"; - } - return true; - } - - start = [ forward ? parent.firstChild : parent.lastChild ]; - - // non-xml :nth-child(...) stores cache data on `parent` - if ( forward && useCache ) { - // Seek `elem` from a previously-cached index - outerCache = parent[ expando ] || (parent[ expando ] = {}); - cache = outerCache[ type ] || []; - nodeIndex = cache[0] === dirruns && cache[1]; - diff = cache[0] === dirruns && cache[2]; - node = nodeIndex && parent.childNodes[ nodeIndex ]; - - while ( (node = ++nodeIndex && node && node[ dir ] || - - // Fallback to seeking `elem` from the start - (diff = nodeIndex = 0) || start.pop()) ) { - - // When found, cache indexes on `parent` and break - if ( node.nodeType === 1 && ++diff && node === elem ) { - outerCache[ type ] = [ dirruns, nodeIndex, diff ]; - break; - } - } - - // Use previously-cached element index if available - } else if ( useCache && (cache = (elem[ expando ] || (elem[ expando ] = {}))[ type ]) && cache[0] === dirruns ) { - diff = cache[1]; - - // xml :nth-child(...) or :nth-last-child(...) or :nth(-last)?-of-type(...) - } else { - // Use the same loop as above to seek `elem` from the start - while ( (node = ++nodeIndex && node && node[ dir ] || - (diff = nodeIndex = 0) || start.pop()) ) { - - if ( ( ofType ? node.nodeName.toLowerCase() === name : node.nodeType === 1 ) && ++diff ) { - // Cache the index of each encountered element - if ( useCache ) { - (node[ expando ] || (node[ expando ] = {}))[ type ] = [ dirruns, diff ]; - } - - if ( node === elem ) { - break; - } - } - } - } - - // Incorporate the offset, then check against cycle size - diff -= last; - return diff === first || ( diff % first === 0 && diff / first >= 0 ); - } - }; - }, - - "PSEUDO": function( pseudo, argument ) { - // pseudo-class names are case-insensitive - // http://www.w3.org/TR/selectors/#pseudo-classes - // Prioritize by case sensitivity in case custom pseudos are added with uppercase letters - // Remember that setFilters inherits from pseudos - var args, - fn = Expr.pseudos[ pseudo ] || Expr.setFilters[ pseudo.toLowerCase() ] || - Sizzle.error( "unsupported pseudo: " + pseudo ); - - // The user may use createPseudo to indicate that - // arguments are needed to create the filter function - // just as Sizzle does - if ( fn[ expando ] ) { - return fn( argument ); - } - - // But maintain support for old signatures - if ( fn.length > 1 ) { - args = [ pseudo, pseudo, "", argument ]; - return Expr.setFilters.hasOwnProperty( pseudo.toLowerCase() ) ? - markFunction(function( seed, matches ) { - var idx, - matched = fn( seed, argument ), - i = matched.length; - while ( i-- ) { - idx = indexOf.call( seed, matched[i] ); - seed[ idx ] = !( matches[ idx ] = matched[i] ); - } - }) : - function( elem ) { - return fn( elem, 0, args ); - }; - } - - return fn; - } - }, - - pseudos: { - // Potentially complex pseudos - "not": markFunction(function( selector ) { - // Trim the selector passed to compile - // to avoid treating leading and trailing - // spaces as combinators - var input = [], - results = [], - matcher = compile( selector.replace( rtrim, "$1" ) ); - - return matcher[ expando ] ? - markFunction(function( seed, matches, context, xml ) { - var elem, - unmatched = matcher( seed, null, xml, [] ), - i = seed.length; - - // Match elements unmatched by `matcher` - while ( i-- ) { - if ( (elem = unmatched[i]) ) { - seed[i] = !(matches[i] = elem); - } - } - }) : - function( elem, context, xml ) { - input[0] = elem; - matcher( input, null, xml, results ); - return !results.pop(); - }; - }), - - "has": markFunction(function( selector ) { - return function( elem ) { - return Sizzle( selector, elem ).length > 0; - }; - }), - - "contains": markFunction(function( text ) { - return function( elem ) { - return ( elem.textContent || elem.innerText || getText( elem ) ).indexOf( text ) > -1; - }; - }), - - // "Whether an element is represented by a :lang() selector - // is based solely on the element's language value - // being equal to the identifier C, - // or beginning with the identifier C immediately followed by "-". - // The matching of C against the element's language value is performed case-insensitively. - // The identifier C does not have to be a valid language name." - // http://www.w3.org/TR/selectors/#lang-pseudo - "lang": markFunction( function( lang ) { - // lang value must be a valid identifier - if ( !ridentifier.test(lang || "") ) { - Sizzle.error( "unsupported lang: " + lang ); - } - lang = lang.replace( runescape, funescape ).toLowerCase(); - return function( elem ) { - var elemLang; - do { - if ( (elemLang = documentIsHTML ? - elem.lang : - elem.getAttribute("xml:lang") || elem.getAttribute("lang")) ) { - - elemLang = elemLang.toLowerCase(); - return elemLang === lang || elemLang.indexOf( lang + "-" ) === 0; - } - } while ( (elem = elem.parentNode) && elem.nodeType === 1 ); - return false; - }; - }), - - // Miscellaneous - "target": function( elem ) { - var hash = window.location && window.location.hash; - return hash && hash.slice( 1 ) === elem.id; - }, - - "root": function( elem ) { - return elem === docElem; - }, - - "focus": function( elem ) { - return elem === document.activeElement && (!document.hasFocus || document.hasFocus()) && !!(elem.type || elem.href || ~elem.tabIndex); - }, - - // Boolean properties - "enabled": function( elem ) { - return elem.disabled === false; - }, - - "disabled": function( elem ) { - return elem.disabled === true; - }, - - "checked": function( elem ) { - // In CSS3, :checked should return both checked and selected elements - // http://www.w3.org/TR/2011/REC-css3-selectors-20110929/#checked - var nodeName = elem.nodeName.toLowerCase(); - return (nodeName === "input" && !!elem.checked) || (nodeName === "option" && !!elem.selected); - }, - - "selected": function( elem ) { - // Accessing this property makes selected-by-default - // options in Safari work properly - if ( elem.parentNode ) { - elem.parentNode.selectedIndex; - } - - return elem.selected === true; - }, - - // Contents - "empty": function( elem ) { - // http://www.w3.org/TR/selectors/#empty-pseudo - // :empty is only affected by element nodes and content nodes(including text(3), cdata(4)), - // not comment, processing instructions, or others - // Thanks to Diego Perini for the nodeName shortcut - // Greater than "@" means alpha characters (specifically not starting with "#" or "?") - for ( elem = elem.firstChild; elem; elem = elem.nextSibling ) { - if ( elem.nodeName > "@" || elem.nodeType === 3 || elem.nodeType === 4 ) { - return false; - } - } - return true; - }, - - "parent": function( elem ) { - return !Expr.pseudos["empty"]( elem ); - }, - - // Element/input types - "header": function( elem ) { - return rheader.test( elem.nodeName ); - }, - - "input": function( elem ) { - return rinputs.test( elem.nodeName ); - }, - - "button": function( elem ) { - var name = elem.nodeName.toLowerCase(); - return name === "input" && elem.type === "button" || name === "button"; - }, - - "text": function( elem ) { - var attr; - // IE6 and 7 will map elem.type to 'text' for new HTML5 types (search, etc) - // use getAttribute instead to test this case - return elem.nodeName.toLowerCase() === "input" && - elem.type === "text" && - ( (attr = elem.getAttribute("type")) == null || attr.toLowerCase() === elem.type ); - }, - - // Position-in-collection - "first": createPositionalPseudo(function() { - return [ 0 ]; - }), - - "last": createPositionalPseudo(function( matchIndexes, length ) { - return [ length - 1 ]; - }), - - "eq": createPositionalPseudo(function( matchIndexes, length, argument ) { - return [ argument < 0 ? argument + length : argument ]; - }), - - "even": createPositionalPseudo(function( matchIndexes, length ) { - var i = 0; - for ( ; i < length; i += 2 ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "odd": createPositionalPseudo(function( matchIndexes, length ) { - var i = 1; - for ( ; i < length; i += 2 ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "lt": createPositionalPseudo(function( matchIndexes, length, argument ) { - var i = argument < 0 ? argument + length : argument; - for ( ; --i >= 0; ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "gt": createPositionalPseudo(function( matchIndexes, length, argument ) { - var i = argument < 0 ? argument + length : argument; - for ( ; ++i < length; ) { - matchIndexes.push( i ); - } - return matchIndexes; - }) - } -}; - -Expr.pseudos["nth"] = Expr.pseudos["eq"]; - -// Add button/input type pseudos -for ( i in { radio: true, checkbox: true, file: true, password: true, image: true } ) { - Expr.pseudos[ i ] = createInputPseudo( i ); -} -for ( i in { submit: true, reset: true } ) { - Expr.pseudos[ i ] = createButtonPseudo( i ); -} - -// Easy API for creating new setFilters -function setFilters() {} -setFilters.prototype = Expr.filters = Expr.pseudos; -Expr.setFilters = new setFilters(); - -function tokenize( selector, parseOnly ) { - var matched, match, tokens, type, - soFar, groups, preFilters, - cached = tokenCache[ selector + " " ]; - - if ( cached ) { - return parseOnly ? 0 : cached.slice( 0 ); - } - - soFar = selector; - groups = []; - preFilters = Expr.preFilter; - - while ( soFar ) { - - // Comma and first run - if ( !matched || (match = rcomma.exec( soFar )) ) { - if ( match ) { - // Don't consume trailing commas as valid - soFar = soFar.slice( match[0].length ) || soFar; - } - groups.push( tokens = [] ); - } - - matched = false; - - // Combinators - if ( (match = rcombinators.exec( soFar )) ) { - matched = match.shift(); - tokens.push({ - value: matched, - // Cast descendant combinators to space - type: match[0].replace( rtrim, " " ) - }); - soFar = soFar.slice( matched.length ); - } - - // Filters - for ( type in Expr.filter ) { - if ( (match = matchExpr[ type ].exec( soFar )) && (!preFilters[ type ] || - (match = preFilters[ type ]( match ))) ) { - matched = match.shift(); - tokens.push({ - value: matched, - type: type, - matches: match - }); - soFar = soFar.slice( matched.length ); - } - } - - if ( !matched ) { - break; - } - } - - // Return the length of the invalid excess - // if we're just parsing - // Otherwise, throw an error or return tokens - return parseOnly ? - soFar.length : - soFar ? - Sizzle.error( selector ) : - // Cache the tokens - tokenCache( selector, groups ).slice( 0 ); -} - -function toSelector( tokens ) { - var i = 0, - len = tokens.length, - selector = ""; - for ( ; i < len; i++ ) { - selector += tokens[i].value; - } - return selector; -} - -function addCombinator( matcher, combinator, base ) { - var dir = combinator.dir, - checkNonElements = base && dir === "parentNode", - doneName = done++; - - return combinator.first ? - // Check against closest ancestor/preceding element - function( elem, context, xml ) { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - return matcher( elem, context, xml ); - } - } - } : - - // Check against all ancestor/preceding elements - function( elem, context, xml ) { - var data, cache, outerCache, - dirkey = dirruns + " " + doneName; - - // We can't set arbitrary data on XML nodes, so they don't benefit from dir caching - if ( xml ) { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - if ( matcher( elem, context, xml ) ) { - return true; - } - } - } - } else { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - outerCache = elem[ expando ] || (elem[ expando ] = {}); - if ( (cache = outerCache[ dir ]) && cache[0] === dirkey ) { - if ( (data = cache[1]) === true || data === cachedruns ) { - return data === true; - } - } else { - cache = outerCache[ dir ] = [ dirkey ]; - cache[1] = matcher( elem, context, xml ) || cachedruns; - if ( cache[1] === true ) { - return true; - } - } - } - } - } - }; -} - -function elementMatcher( matchers ) { - return matchers.length > 1 ? - function( elem, context, xml ) { - var i = matchers.length; - while ( i-- ) { - if ( !matchers[i]( elem, context, xml ) ) { - return false; - } - } - return true; - } : - matchers[0]; -} - -function condense( unmatched, map, filter, context, xml ) { - var elem, - newUnmatched = [], - i = 0, - len = unmatched.length, - mapped = map != null; - - for ( ; i < len; i++ ) { - if ( (elem = unmatched[i]) ) { - if ( !filter || filter( elem, context, xml ) ) { - newUnmatched.push( elem ); - if ( mapped ) { - map.push( i ); - } - } - } - } - - return newUnmatched; -} - -function setMatcher( preFilter, selector, matcher, postFilter, postFinder, postSelector ) { - if ( postFilter && !postFilter[ expando ] ) { - postFilter = setMatcher( postFilter ); - } - if ( postFinder && !postFinder[ expando ] ) { - postFinder = setMatcher( postFinder, postSelector ); - } - return markFunction(function( seed, results, context, xml ) { - var temp, i, elem, - preMap = [], - postMap = [], - preexisting = results.length, - - // Get initial elements from seed or context - elems = seed || multipleContexts( selector || "*", context.nodeType ? [ context ] : context, [] ), - - // Prefilter to get matcher input, preserving a map for seed-results synchronization - matcherIn = preFilter && ( seed || !selector ) ? - condense( elems, preMap, preFilter, context, xml ) : - elems, - - matcherOut = matcher ? - // If we have a postFinder, or filtered seed, or non-seed postFilter or preexisting results, - postFinder || ( seed ? preFilter : preexisting || postFilter ) ? - - // ...intermediate processing is necessary - [] : - - // ...otherwise use results directly - results : - matcherIn; - - // Find primary matches - if ( matcher ) { - matcher( matcherIn, matcherOut, context, xml ); - } - - // Apply postFilter - if ( postFilter ) { - temp = condense( matcherOut, postMap ); - postFilter( temp, [], context, xml ); - - // Un-match failing elements by moving them back to matcherIn - i = temp.length; - while ( i-- ) { - if ( (elem = temp[i]) ) { - matcherOut[ postMap[i] ] = !(matcherIn[ postMap[i] ] = elem); - } - } - } - - if ( seed ) { - if ( postFinder || preFilter ) { - if ( postFinder ) { - // Get the final matcherOut by condensing this intermediate into postFinder contexts - temp = []; - i = matcherOut.length; - while ( i-- ) { - if ( (elem = matcherOut[i]) ) { - // Restore matcherIn since elem is not yet a final match - temp.push( (matcherIn[i] = elem) ); - } - } - postFinder( null, (matcherOut = []), temp, xml ); - } - - // Move matched elements from seed to results to keep them synchronized - i = matcherOut.length; - while ( i-- ) { - if ( (elem = matcherOut[i]) && - (temp = postFinder ? indexOf.call( seed, elem ) : preMap[i]) > -1 ) { - - seed[temp] = !(results[temp] = elem); - } - } - } - - // Add elements to results, through postFinder if defined - } else { - matcherOut = condense( - matcherOut === results ? - matcherOut.splice( preexisting, matcherOut.length ) : - matcherOut - ); - if ( postFinder ) { - postFinder( null, results, matcherOut, xml ); - } else { - push.apply( results, matcherOut ); - } - } - }); -} - -function matcherFromTokens( tokens ) { - var checkContext, matcher, j, - len = tokens.length, - leadingRelative = Expr.relative[ tokens[0].type ], - implicitRelative = leadingRelative || Expr.relative[" "], - i = leadingRelative ? 1 : 0, - - // The foundational matcher ensures that elements are reachable from top-level context(s) - matchContext = addCombinator( function( elem ) { - return elem === checkContext; - }, implicitRelative, true ), - matchAnyContext = addCombinator( function( elem ) { - return indexOf.call( checkContext, elem ) > -1; - }, implicitRelative, true ), - matchers = [ function( elem, context, xml ) { - return ( !leadingRelative && ( xml || context !== outermostContext ) ) || ( - (checkContext = context).nodeType ? - matchContext( elem, context, xml ) : - matchAnyContext( elem, context, xml ) ); - } ]; - - for ( ; i < len; i++ ) { - if ( (matcher = Expr.relative[ tokens[i].type ]) ) { - matchers = [ addCombinator(elementMatcher( matchers ), matcher) ]; - } else { - matcher = Expr.filter[ tokens[i].type ].apply( null, tokens[i].matches ); - - // Return special upon seeing a positional matcher - if ( matcher[ expando ] ) { - // Find the next relative operator (if any) for proper handling - j = ++i; - for ( ; j < len; j++ ) { - if ( Expr.relative[ tokens[j].type ] ) { - break; - } - } - return setMatcher( - i > 1 && elementMatcher( matchers ), - i > 1 && toSelector( - // If the preceding token was a descendant combinator, insert an implicit any-element `*` - tokens.slice( 0, i - 1 ).concat({ value: tokens[ i - 2 ].type === " " ? "*" : "" }) - ).replace( rtrim, "$1" ), - matcher, - i < j && matcherFromTokens( tokens.slice( i, j ) ), - j < len && matcherFromTokens( (tokens = tokens.slice( j )) ), - j < len && toSelector( tokens ) - ); - } - matchers.push( matcher ); - } - } - - return elementMatcher( matchers ); -} - -function matcherFromGroupMatchers( elementMatchers, setMatchers ) { - // A counter to specify which element is currently being matched - var matcherCachedRuns = 0, - bySet = setMatchers.length > 0, - byElement = elementMatchers.length > 0, - superMatcher = function( seed, context, xml, results, expandContext ) { - var elem, j, matcher, - setMatched = [], - matchedCount = 0, - i = "0", - unmatched = seed && [], - outermost = expandContext != null, - contextBackup = outermostContext, - // We must always have either seed elements or context - elems = seed || byElement && Expr.find["TAG"]( "*", expandContext && context.parentNode || context ), - // Use integer dirruns iff this is the outermost matcher - dirrunsUnique = (dirruns += contextBackup == null ? 1 : Math.random() || 0.1); - - if ( outermost ) { - outermostContext = context !== document && context; - cachedruns = matcherCachedRuns; - } - - // Add elements passing elementMatchers directly to results - // Keep `i` a string if there are no elements so `matchedCount` will be "00" below - for ( ; (elem = elems[i]) != null; i++ ) { - if ( byElement && elem ) { - j = 0; - while ( (matcher = elementMatchers[j++]) ) { - if ( matcher( elem, context, xml ) ) { - results.push( elem ); - break; - } - } - if ( outermost ) { - dirruns = dirrunsUnique; - cachedruns = ++matcherCachedRuns; - } - } - - // Track unmatched elements for set filters - if ( bySet ) { - // They will have gone through all possible matchers - if ( (elem = !matcher && elem) ) { - matchedCount--; - } - - // Lengthen the array for every element, matched or not - if ( seed ) { - unmatched.push( elem ); - } - } - } - - // Apply set filters to unmatched elements - matchedCount += i; - if ( bySet && i !== matchedCount ) { - j = 0; - while ( (matcher = setMatchers[j++]) ) { - matcher( unmatched, setMatched, context, xml ); - } - - if ( seed ) { - // Reintegrate element matches to eliminate the need for sorting - if ( matchedCount > 0 ) { - while ( i-- ) { - if ( !(unmatched[i] || setMatched[i]) ) { - setMatched[i] = pop.call( results ); - } - } - } - - // Discard index placeholder values to get only actual matches - setMatched = condense( setMatched ); - } - - // Add matches to results - push.apply( results, setMatched ); - - // Seedless set matches succeeding multiple successful matchers stipulate sorting - if ( outermost && !seed && setMatched.length > 0 && - ( matchedCount + setMatchers.length ) > 1 ) { - - Sizzle.uniqueSort( results ); - } - } - - // Override manipulation of globals by nested matchers - if ( outermost ) { - dirruns = dirrunsUnique; - outermostContext = contextBackup; - } - - return unmatched; - }; - - return bySet ? - markFunction( superMatcher ) : - superMatcher; -} - -compile = Sizzle.compile = function( selector, group /* Internal Use Only */ ) { - var i, - setMatchers = [], - elementMatchers = [], - cached = compilerCache[ selector + " " ]; - - if ( !cached ) { - // Generate a function of recursive functions that can be used to check each element - if ( !group ) { - group = tokenize( selector ); - } - i = group.length; - while ( i-- ) { - cached = matcherFromTokens( group[i] ); - if ( cached[ expando ] ) { - setMatchers.push( cached ); - } else { - elementMatchers.push( cached ); - } - } - - // Cache the compiled function - cached = compilerCache( selector, matcherFromGroupMatchers( elementMatchers, setMatchers ) ); - } - return cached; -}; - -function multipleContexts( selector, contexts, results ) { - var i = 0, - len = contexts.length; - for ( ; i < len; i++ ) { - Sizzle( selector, contexts[i], results ); - } - return results; -} - -function select( selector, context, results, seed ) { - var i, tokens, token, type, find, - match = tokenize( selector ); - - if ( !seed ) { - // Try to minimize operations if there is only one group - if ( match.length === 1 ) { - - // Take a shortcut and set the context if the root selector is an ID - tokens = match[0] = match[0].slice( 0 ); - if ( tokens.length > 2 && (token = tokens[0]).type === "ID" && - support.getById && context.nodeType === 9 && documentIsHTML && - Expr.relative[ tokens[1].type ] ) { - - context = ( Expr.find["ID"]( token.matches[0].replace(runescape, funescape), context ) || [] )[0]; - if ( !context ) { - return results; - } - selector = selector.slice( tokens.shift().value.length ); - } - - // Fetch a seed set for right-to-left matching - i = matchExpr["needsContext"].test( selector ) ? 0 : tokens.length; - while ( i-- ) { - token = tokens[i]; - - // Abort if we hit a combinator - if ( Expr.relative[ (type = token.type) ] ) { - break; - } - if ( (find = Expr.find[ type ]) ) { - // Search, expanding context for leading sibling combinators - if ( (seed = find( - token.matches[0].replace( runescape, funescape ), - rsibling.test( tokens[0].type ) && context.parentNode || context - )) ) { - - // If seed is empty or no tokens remain, we can return early - tokens.splice( i, 1 ); - selector = seed.length && toSelector( tokens ); - if ( !selector ) { - push.apply( results, seed ); - return results; - } - - break; - } - } - } - } - } - - // Compile and execute a filtering function - // Provide `match` to avoid retokenization if we modified the selector above - compile( selector, match )( - seed, - context, - !documentIsHTML, - results, - rsibling.test( selector ) - ); - return results; -} - -// One-time assignments - -// Sort stability -support.sortStable = expando.split("").sort( sortOrder ).join("") === expando; - -// Support: Chrome<14 -// Always assume duplicates if they aren't passed to the comparison function -support.detectDuplicates = hasDuplicate; - -// Initialize against the default document -setDocument(); - -// Support: Webkit<537.32 - Safari 6.0.3/Chrome 25 (fixed in Chrome 27) -// Detached nodes confoundingly follow *each other* -support.sortDetached = assert(function( div1 ) { - // Should return 1, but returns 4 (following) - return div1.compareDocumentPosition( document.createElement("div") ) & 1; -}); - -// Support: IE<8 -// Prevent attribute/property "interpolation" -// http://msdn.microsoft.com/en-us/library/ms536429%28VS.85%29.aspx -if ( !assert(function( div ) { - div.innerHTML = ""; - return div.firstChild.getAttribute("href") === "#" ; -}) ) { - addHandle( "type|href|height|width", function( elem, name, isXML ) { - if ( !isXML ) { - return elem.getAttribute( name, name.toLowerCase() === "type" ? 1 : 2 ); - } - }); -} - -// Support: IE<9 -// Use defaultValue in place of getAttribute("value") -if ( !support.attributes || !assert(function( div ) { - div.innerHTML = ""; - div.firstChild.setAttribute( "value", "" ); - return div.firstChild.getAttribute( "value" ) === ""; -}) ) { - addHandle( "value", function( elem, name, isXML ) { - if ( !isXML && elem.nodeName.toLowerCase() === "input" ) { - return elem.defaultValue; - } - }); -} - -// Support: IE<9 -// Use getAttributeNode to fetch booleans when getAttribute lies -if ( !assert(function( div ) { - return div.getAttribute("disabled") == null; -}) ) { - addHandle( booleans, function( elem, name, isXML ) { - var val; - if ( !isXML ) { - return (val = elem.getAttributeNode( name )) && val.specified ? - val.value : - elem[ name ] === true ? name.toLowerCase() : null; - } - }); -} - -jQuery.find = Sizzle; -jQuery.expr = Sizzle.selectors; -jQuery.expr[":"] = jQuery.expr.pseudos; -jQuery.unique = Sizzle.uniqueSort; -jQuery.text = Sizzle.getText; -jQuery.isXMLDoc = Sizzle.isXML; -jQuery.contains = Sizzle.contains; - - -})( window ); -// String to Object options format cache -var optionsCache = {}; - -// Convert String-formatted options into Object-formatted ones and store in cache -function createOptions( options ) { - var object = optionsCache[ options ] = {}; - jQuery.each( options.match( core_rnotwhite ) || [], function( _, flag ) { - object[ flag ] = true; - }); - return object; -} - -/* - * Create a callback list using the following parameters: - * - * options: an optional list of space-separated options that will change how - * the callback list behaves or a more traditional option object - * - * By default a callback list will act like an event callback list and can be - * "fired" multiple times. - * - * Possible options: - * - * once: will ensure the callback list can only be fired once (like a Deferred) - * - * memory: will keep track of previous values and will call any callback added - * after the list has been fired right away with the latest "memorized" - * values (like a Deferred) - * - * unique: will ensure a callback can only be added once (no duplicate in the list) - * - * stopOnFalse: interrupt callings when a callback returns false - * - */ -jQuery.Callbacks = function( options ) { - - // Convert options from String-formatted to Object-formatted if needed - // (we check in cache first) - options = typeof options === "string" ? - ( optionsCache[ options ] || createOptions( options ) ) : - jQuery.extend( {}, options ); - - var // Flag to know if list is currently firing - firing, - // Last fire value (for non-forgettable lists) - memory, - // Flag to know if list was already fired - fired, - // End of the loop when firing - firingLength, - // Index of currently firing callback (modified by remove if needed) - firingIndex, - // First callback to fire (used internally by add and fireWith) - firingStart, - // Actual callback list - list = [], - // Stack of fire calls for repeatable lists - stack = !options.once && [], - // Fire callbacks - fire = function( data ) { - memory = options.memory && data; - fired = true; - firingIndex = firingStart || 0; - firingStart = 0; - firingLength = list.length; - firing = true; - for ( ; list && firingIndex < firingLength; firingIndex++ ) { - if ( list[ firingIndex ].apply( data[ 0 ], data[ 1 ] ) === false && options.stopOnFalse ) { - memory = false; // To prevent further calls using add - break; - } - } - firing = false; - if ( list ) { - if ( stack ) { - if ( stack.length ) { - fire( stack.shift() ); - } - } else if ( memory ) { - list = []; - } else { - self.disable(); - } - } - }, - // Actual Callbacks object - self = { - // Add a callback or a collection of callbacks to the list - add: function() { - if ( list ) { - // First, we save the current length - var start = list.length; - (function add( args ) { - jQuery.each( args, function( _, arg ) { - var type = jQuery.type( arg ); - if ( type === "function" ) { - if ( !options.unique || !self.has( arg ) ) { - list.push( arg ); - } - } else if ( arg && arg.length && type !== "string" ) { - // Inspect recursively - add( arg ); - } - }); - })( arguments ); - // Do we need to add the callbacks to the - // current firing batch? - if ( firing ) { - firingLength = list.length; - // With memory, if we're not firing then - // we should call right away - } else if ( memory ) { - firingStart = start; - fire( memory ); - } - } - return this; - }, - // Remove a callback from the list - remove: function() { - if ( list ) { - jQuery.each( arguments, function( _, arg ) { - var index; - while( ( index = jQuery.inArray( arg, list, index ) ) > -1 ) { - list.splice( index, 1 ); - // Handle firing indexes - if ( firing ) { - if ( index <= firingLength ) { - firingLength--; - } - if ( index <= firingIndex ) { - firingIndex--; - } - } - } - }); - } - return this; - }, - // Check if a given callback is in the list. - // If no argument is given, return whether or not list has callbacks attached. - has: function( fn ) { - return fn ? jQuery.inArray( fn, list ) > -1 : !!( list && list.length ); - }, - // Remove all callbacks from the list - empty: function() { - list = []; - firingLength = 0; - return this; - }, - // Have the list do nothing anymore - disable: function() { - list = stack = memory = undefined; - return this; - }, - // Is it disabled? - disabled: function() { - return !list; - }, - // Lock the list in its current state - lock: function() { - stack = undefined; - if ( !memory ) { - self.disable(); - } - return this; - }, - // Is it locked? - locked: function() { - return !stack; - }, - // Call all callbacks with the given context and arguments - fireWith: function( context, args ) { - if ( list && ( !fired || stack ) ) { - args = args || []; - args = [ context, args.slice ? args.slice() : args ]; - if ( firing ) { - stack.push( args ); - } else { - fire( args ); - } - } - return this; - }, - // Call all the callbacks with the given arguments - fire: function() { - self.fireWith( this, arguments ); - return this; - }, - // To know if the callbacks have already been called at least once - fired: function() { - return !!fired; - } - }; - - return self; -}; -jQuery.extend({ - - Deferred: function( func ) { - var tuples = [ - // action, add listener, listener list, final state - [ "resolve", "done", jQuery.Callbacks("once memory"), "resolved" ], - [ "reject", "fail", jQuery.Callbacks("once memory"), "rejected" ], - [ "notify", "progress", jQuery.Callbacks("memory") ] - ], - state = "pending", - promise = { - state: function() { - return state; - }, - always: function() { - deferred.done( arguments ).fail( arguments ); - return this; - }, - then: function( /* fnDone, fnFail, fnProgress */ ) { - var fns = arguments; - return jQuery.Deferred(function( newDefer ) { - jQuery.each( tuples, function( i, tuple ) { - var action = tuple[ 0 ], - fn = jQuery.isFunction( fns[ i ] ) && fns[ i ]; - // deferred[ done | fail | progress ] for forwarding actions to newDefer - deferred[ tuple[1] ](function() { - var returned = fn && fn.apply( this, arguments ); - if ( returned && jQuery.isFunction( returned.promise ) ) { - returned.promise() - .done( newDefer.resolve ) - .fail( newDefer.reject ) - .progress( newDefer.notify ); - } else { - newDefer[ action + "With" ]( this === promise ? newDefer.promise() : this, fn ? [ returned ] : arguments ); - } - }); - }); - fns = null; - }).promise(); - }, - // Get a promise for this deferred - // If obj is provided, the promise aspect is added to the object - promise: function( obj ) { - return obj != null ? jQuery.extend( obj, promise ) : promise; - } - }, - deferred = {}; - - // Keep pipe for back-compat - promise.pipe = promise.then; - - // Add list-specific methods - jQuery.each( tuples, function( i, tuple ) { - var list = tuple[ 2 ], - stateString = tuple[ 3 ]; - - // promise[ done | fail | progress ] = list.add - promise[ tuple[1] ] = list.add; - - // Handle state - if ( stateString ) { - list.add(function() { - // state = [ resolved | rejected ] - state = stateString; - - // [ reject_list | resolve_list ].disable; progress_list.lock - }, tuples[ i ^ 1 ][ 2 ].disable, tuples[ 2 ][ 2 ].lock ); - } - - // deferred[ resolve | reject | notify ] - deferred[ tuple[0] ] = function() { - deferred[ tuple[0] + "With" ]( this === deferred ? promise : this, arguments ); - return this; - }; - deferred[ tuple[0] + "With" ] = list.fireWith; - }); - - // Make the deferred a promise - promise.promise( deferred ); - - // Call given func if any - if ( func ) { - func.call( deferred, deferred ); - } - - // All done! - return deferred; - }, - - // Deferred helper - when: function( subordinate /* , ..., subordinateN */ ) { - var i = 0, - resolveValues = core_slice.call( arguments ), - length = resolveValues.length, - - // the count of uncompleted subordinates - remaining = length !== 1 || ( subordinate && jQuery.isFunction( subordinate.promise ) ) ? length : 0, - - // the master Deferred. If resolveValues consist of only a single Deferred, just use that. - deferred = remaining === 1 ? subordinate : jQuery.Deferred(), - - // Update function for both resolve and progress values - updateFunc = function( i, contexts, values ) { - return function( value ) { - contexts[ i ] = this; - values[ i ] = arguments.length > 1 ? core_slice.call( arguments ) : value; - if( values === progressValues ) { - deferred.notifyWith( contexts, values ); - } else if ( !( --remaining ) ) { - deferred.resolveWith( contexts, values ); - } - }; - }, - - progressValues, progressContexts, resolveContexts; - - // add listeners to Deferred subordinates; treat others as resolved - if ( length > 1 ) { - progressValues = new Array( length ); - progressContexts = new Array( length ); - resolveContexts = new Array( length ); - for ( ; i < length; i++ ) { - if ( resolveValues[ i ] && jQuery.isFunction( resolveValues[ i ].promise ) ) { - resolveValues[ i ].promise() - .done( updateFunc( i, resolveContexts, resolveValues ) ) - .fail( deferred.reject ) - .progress( updateFunc( i, progressContexts, progressValues ) ); - } else { - --remaining; - } - } - } - - // if we're not waiting on anything, resolve the master - if ( !remaining ) { - deferred.resolveWith( resolveContexts, resolveValues ); - } - - return deferred.promise(); - } -}); -jQuery.support = (function( support ) { - - var all, a, input, select, fragment, opt, eventName, isSupported, i, - div = document.createElement("div"); - - // Setup - div.setAttribute( "className", "t" ); - div.innerHTML = "
a"; - - // Finish early in limited (non-browser) environments - all = div.getElementsByTagName("*") || []; - a = div.getElementsByTagName("a")[ 0 ]; - if ( !a || !a.style || !all.length ) { - return support; - } - - // First batch of tests - select = document.createElement("select"); - opt = select.appendChild( document.createElement("option") ); - input = div.getElementsByTagName("input")[ 0 ]; - - a.style.cssText = "top:1px;float:left;opacity:.5"; - - // Test setAttribute on camelCase class. If it works, we need attrFixes when doing get/setAttribute (ie6/7) - support.getSetAttribute = div.className !== "t"; - - // IE strips leading whitespace when .innerHTML is used - support.leadingWhitespace = div.firstChild.nodeType === 3; - - // Make sure that tbody elements aren't automatically inserted - // IE will insert them into empty tables - support.tbody = !div.getElementsByTagName("tbody").length; - - // Make sure that link elements get serialized correctly by innerHTML - // This requires a wrapper element in IE - support.htmlSerialize = !!div.getElementsByTagName("link").length; - - // Get the style information from getAttribute - // (IE uses .cssText instead) - support.style = /top/.test( a.getAttribute("style") ); - - // Make sure that URLs aren't manipulated - // (IE normalizes it by default) - support.hrefNormalized = a.getAttribute("href") === "/a"; - - // Make sure that element opacity exists - // (IE uses filter instead) - // Use a regex to work around a WebKit issue. See #5145 - support.opacity = /^0.5/.test( a.style.opacity ); - - // Verify style float existence - // (IE uses styleFloat instead of cssFloat) - support.cssFloat = !!a.style.cssFloat; - - // Check the default checkbox/radio value ("" on WebKit; "on" elsewhere) - support.checkOn = !!input.value; - - // Make sure that a selected-by-default option has a working selected property. - // (WebKit defaults to false instead of true, IE too, if it's in an optgroup) - support.optSelected = opt.selected; - - // Tests for enctype support on a form (#6743) - support.enctype = !!document.createElement("form").enctype; - - // Makes sure cloning an html5 element does not cause problems - // Where outerHTML is undefined, this still works - support.html5Clone = document.createElement("nav").cloneNode( true ).outerHTML !== "<:nav>"; - - // Will be defined later - support.inlineBlockNeedsLayout = false; - support.shrinkWrapBlocks = false; - support.pixelPosition = false; - support.deleteExpando = true; - support.noCloneEvent = true; - support.reliableMarginRight = true; - support.boxSizingReliable = true; - - // Make sure checked status is properly cloned - input.checked = true; - support.noCloneChecked = input.cloneNode( true ).checked; - - // Make sure that the options inside disabled selects aren't marked as disabled - // (WebKit marks them as disabled) - select.disabled = true; - support.optDisabled = !opt.disabled; - - // Support: IE<9 - try { - delete div.test; - } catch( e ) { - support.deleteExpando = false; - } - - // Check if we can trust getAttribute("value") - input = document.createElement("input"); - input.setAttribute( "value", "" ); - support.input = input.getAttribute( "value" ) === ""; - - // Check if an input maintains its value after becoming a radio - input.value = "t"; - input.setAttribute( "type", "radio" ); - support.radioValue = input.value === "t"; - - // #11217 - WebKit loses check when the name is after the checked attribute - input.setAttribute( "checked", "t" ); - input.setAttribute( "name", "t" ); - - fragment = document.createDocumentFragment(); - fragment.appendChild( input ); - - // Check if a disconnected checkbox will retain its checked - // value of true after appended to the DOM (IE6/7) - support.appendChecked = input.checked; - - // WebKit doesn't clone checked state correctly in fragments - support.checkClone = fragment.cloneNode( true ).cloneNode( true ).lastChild.checked; - - // Support: IE<9 - // Opera does not clone events (and typeof div.attachEvent === undefined). - // IE9-10 clones events bound via attachEvent, but they don't trigger with .click() - if ( div.attachEvent ) { - div.attachEvent( "onclick", function() { - support.noCloneEvent = false; - }); - - div.cloneNode( true ).click(); - } - - // Support: IE<9 (lack submit/change bubble), Firefox 17+ (lack focusin event) - // Beware of CSP restrictions (https://developer.mozilla.org/en/Security/CSP) - for ( i in { submit: true, change: true, focusin: true }) { - div.setAttribute( eventName = "on" + i, "t" ); - - support[ i + "Bubbles" ] = eventName in window || div.attributes[ eventName ].expando === false; - } - - div.style.backgroundClip = "content-box"; - div.cloneNode( true ).style.backgroundClip = ""; - support.clearCloneStyle = div.style.backgroundClip === "content-box"; - - // Support: IE<9 - // Iteration over object's inherited properties before its own. - for ( i in jQuery( support ) ) { - break; - } - support.ownLast = i !== "0"; - - // Run tests that need a body at doc ready - jQuery(function() { - var container, marginDiv, tds, - divReset = "padding:0;margin:0;border:0;display:block;box-sizing:content-box;-moz-box-sizing:content-box;-webkit-box-sizing:content-box;", - body = document.getElementsByTagName("body")[0]; - - if ( !body ) { - // Return for frameset docs that don't have a body - return; - } - - container = document.createElement("div"); - container.style.cssText = "border:0;width:0;height:0;position:absolute;top:0;left:-9999px;margin-top:1px"; - - body.appendChild( container ).appendChild( div ); - - // Support: IE8 - // Check if table cells still have offsetWidth/Height when they are set - // to display:none and there are still other visible table cells in a - // table row; if so, offsetWidth/Height are not reliable for use when - // determining if an element has been hidden directly using - // display:none (it is still safe to use offsets if a parent element is - // hidden; don safety goggles and see bug #4512 for more information). - div.innerHTML = "
t
"; - tds = div.getElementsByTagName("td"); - tds[ 0 ].style.cssText = "padding:0;margin:0;border:0;display:none"; - isSupported = ( tds[ 0 ].offsetHeight === 0 ); - - tds[ 0 ].style.display = ""; - tds[ 1 ].style.display = "none"; - - // Support: IE8 - // Check if empty table cells still have offsetWidth/Height - support.reliableHiddenOffsets = isSupported && ( tds[ 0 ].offsetHeight === 0 ); - - // Check box-sizing and margin behavior. - div.innerHTML = ""; - div.style.cssText = "box-sizing:border-box;-moz-box-sizing:border-box;-webkit-box-sizing:border-box;padding:1px;border:1px;display:block;width:4px;margin-top:1%;position:absolute;top:1%;"; - - // Workaround failing boxSizing test due to offsetWidth returning wrong value - // with some non-1 values of body zoom, ticket #13543 - jQuery.swap( body, body.style.zoom != null ? { zoom: 1 } : {}, function() { - support.boxSizing = div.offsetWidth === 4; - }); - - // Use window.getComputedStyle because jsdom on node.js will break without it. - if ( window.getComputedStyle ) { - support.pixelPosition = ( window.getComputedStyle( div, null ) || {} ).top !== "1%"; - support.boxSizingReliable = ( window.getComputedStyle( div, null ) || { width: "4px" } ).width === "4px"; - - // Check if div with explicit width and no margin-right incorrectly - // gets computed margin-right based on width of container. (#3333) - // Fails in WebKit before Feb 2011 nightlies - // WebKit Bug 13343 - getComputedStyle returns wrong value for margin-right - marginDiv = div.appendChild( document.createElement("div") ); - marginDiv.style.cssText = div.style.cssText = divReset; - marginDiv.style.marginRight = marginDiv.style.width = "0"; - div.style.width = "1px"; - - support.reliableMarginRight = - !parseFloat( ( window.getComputedStyle( marginDiv, null ) || {} ).marginRight ); - } - - if ( typeof div.style.zoom !== core_strundefined ) { - // Support: IE<8 - // Check if natively block-level elements act like inline-block - // elements when setting their display to 'inline' and giving - // them layout - div.innerHTML = ""; - div.style.cssText = divReset + "width:1px;padding:1px;display:inline;zoom:1"; - support.inlineBlockNeedsLayout = ( div.offsetWidth === 3 ); - - // Support: IE6 - // Check if elements with layout shrink-wrap their children - div.style.display = "block"; - div.innerHTML = "
"; - div.firstChild.style.width = "5px"; - support.shrinkWrapBlocks = ( div.offsetWidth !== 3 ); - - if ( support.inlineBlockNeedsLayout ) { - // Prevent IE 6 from affecting layout for positioned elements #11048 - // Prevent IE from shrinking the body in IE 7 mode #12869 - // Support: IE<8 - body.style.zoom = 1; - } - } - - body.removeChild( container ); - - // Null elements to avoid leaks in IE - container = div = tds = marginDiv = null; - }); - - // Null elements to avoid leaks in IE - all = select = fragment = opt = a = input = null; - - return support; -})({}); - -var rbrace = /(?:\{[\s\S]*\}|\[[\s\S]*\])$/, - rmultiDash = /([A-Z])/g; - -function internalData( elem, name, data, pvt /* Internal Use Only */ ){ - if ( !jQuery.acceptData( elem ) ) { - return; - } - - var ret, thisCache, - internalKey = jQuery.expando, - - // We have to handle DOM nodes and JS objects differently because IE6-7 - // can't GC object references properly across the DOM-JS boundary - isNode = elem.nodeType, - - // Only DOM nodes need the global jQuery cache; JS object data is - // attached directly to the object so GC can occur automatically - cache = isNode ? jQuery.cache : elem, - - // Only defining an ID for JS objects if its cache already exists allows - // the code to shortcut on the same path as a DOM node with no cache - id = isNode ? elem[ internalKey ] : elem[ internalKey ] && internalKey; - - // Avoid doing any more work than we need to when trying to get data on an - // object that has no data at all - if ( (!id || !cache[id] || (!pvt && !cache[id].data)) && data === undefined && typeof name === "string" ) { - return; - } - - if ( !id ) { - // Only DOM nodes need a new unique ID for each element since their data - // ends up in the global cache - if ( isNode ) { - id = elem[ internalKey ] = core_deletedIds.pop() || jQuery.guid++; - } else { - id = internalKey; - } - } - - if ( !cache[ id ] ) { - // Avoid exposing jQuery metadata on plain JS objects when the object - // is serialized using JSON.stringify - cache[ id ] = isNode ? {} : { toJSON: jQuery.noop }; - } - - // An object can be passed to jQuery.data instead of a key/value pair; this gets - // shallow copied over onto the existing cache - if ( typeof name === "object" || typeof name === "function" ) { - if ( pvt ) { - cache[ id ] = jQuery.extend( cache[ id ], name ); - } else { - cache[ id ].data = jQuery.extend( cache[ id ].data, name ); - } - } - - thisCache = cache[ id ]; - - // jQuery data() is stored in a separate object inside the object's internal data - // cache in order to avoid key collisions between internal data and user-defined - // data. - if ( !pvt ) { - if ( !thisCache.data ) { - thisCache.data = {}; - } - - thisCache = thisCache.data; - } - - if ( data !== undefined ) { - thisCache[ jQuery.camelCase( name ) ] = data; - } - - // Check for both converted-to-camel and non-converted data property names - // If a data property was specified - if ( typeof name === "string" ) { - - // First Try to find as-is property data - ret = thisCache[ name ]; - - // Test for null|undefined property data - if ( ret == null ) { - - // Try to find the camelCased property - ret = thisCache[ jQuery.camelCase( name ) ]; - } - } else { - ret = thisCache; - } - - return ret; -} - -function internalRemoveData( elem, name, pvt ) { - if ( !jQuery.acceptData( elem ) ) { - return; - } - - var thisCache, i, - isNode = elem.nodeType, - - // See jQuery.data for more information - cache = isNode ? jQuery.cache : elem, - id = isNode ? elem[ jQuery.expando ] : jQuery.expando; - - // If there is already no cache entry for this object, there is no - // purpose in continuing - if ( !cache[ id ] ) { - return; - } - - if ( name ) { - - thisCache = pvt ? cache[ id ] : cache[ id ].data; - - if ( thisCache ) { - - // Support array or space separated string names for data keys - if ( !jQuery.isArray( name ) ) { - - // try the string as a key before any manipulation - if ( name in thisCache ) { - name = [ name ]; - } else { - - // split the camel cased version by spaces unless a key with the spaces exists - name = jQuery.camelCase( name ); - if ( name in thisCache ) { - name = [ name ]; - } else { - name = name.split(" "); - } - } - } else { - // If "name" is an array of keys... - // When data is initially created, via ("key", "val") signature, - // keys will be converted to camelCase. - // Since there is no way to tell _how_ a key was added, remove - // both plain key and camelCase key. #12786 - // This will only penalize the array argument path. - name = name.concat( jQuery.map( name, jQuery.camelCase ) ); - } - - i = name.length; - while ( i-- ) { - delete thisCache[ name[i] ]; - } - - // If there is no data left in the cache, we want to continue - // and let the cache object itself get destroyed - if ( pvt ? !isEmptyDataObject(thisCache) : !jQuery.isEmptyObject(thisCache) ) { - return; - } - } - } - - // See jQuery.data for more information - if ( !pvt ) { - delete cache[ id ].data; - - // Don't destroy the parent cache unless the internal data object - // had been the only thing left in it - if ( !isEmptyDataObject( cache[ id ] ) ) { - return; - } - } - - // Destroy the cache - if ( isNode ) { - jQuery.cleanData( [ elem ], true ); - - // Use delete when supported for expandos or `cache` is not a window per isWindow (#10080) - /* jshint eqeqeq: false */ - } else if ( jQuery.support.deleteExpando || cache != cache.window ) { - /* jshint eqeqeq: true */ - delete cache[ id ]; - - // When all else fails, null - } else { - cache[ id ] = null; - } -} - -jQuery.extend({ - cache: {}, - - // The following elements throw uncatchable exceptions if you - // attempt to add expando properties to them. - noData: { - "applet": true, - "embed": true, - // Ban all objects except for Flash (which handle expandos) - "object": "clsid:D27CDB6E-AE6D-11cf-96B8-444553540000" - }, - - hasData: function( elem ) { - elem = elem.nodeType ? jQuery.cache[ elem[jQuery.expando] ] : elem[ jQuery.expando ]; - return !!elem && !isEmptyDataObject( elem ); - }, - - data: function( elem, name, data ) { - return internalData( elem, name, data ); - }, - - removeData: function( elem, name ) { - return internalRemoveData( elem, name ); - }, - - // For internal use only. - _data: function( elem, name, data ) { - return internalData( elem, name, data, true ); - }, - - _removeData: function( elem, name ) { - return internalRemoveData( elem, name, true ); - }, - - // A method for determining if a DOM node can handle the data expando - acceptData: function( elem ) { - // Do not set data on non-element because it will not be cleared (#8335). - if ( elem.nodeType && elem.nodeType !== 1 && elem.nodeType !== 9 ) { - return false; - } - - var noData = elem.nodeName && jQuery.noData[ elem.nodeName.toLowerCase() ]; - - // nodes accept data unless otherwise specified; rejection can be conditional - return !noData || noData !== true && elem.getAttribute("classid") === noData; - } -}); - -jQuery.fn.extend({ - data: function( key, value ) { - var attrs, name, - data = null, - i = 0, - elem = this[0]; - - // Special expections of .data basically thwart jQuery.access, - // so implement the relevant behavior ourselves - - // Gets all values - if ( key === undefined ) { - if ( this.length ) { - data = jQuery.data( elem ); - - if ( elem.nodeType === 1 && !jQuery._data( elem, "parsedAttrs" ) ) { - attrs = elem.attributes; - for ( ; i < attrs.length; i++ ) { - name = attrs[i].name; - - if ( name.indexOf("data-") === 0 ) { - name = jQuery.camelCase( name.slice(5) ); - - dataAttr( elem, name, data[ name ] ); - } - } - jQuery._data( elem, "parsedAttrs", true ); - } - } - - return data; - } - - // Sets multiple values - if ( typeof key === "object" ) { - return this.each(function() { - jQuery.data( this, key ); - }); - } - - return arguments.length > 1 ? - - // Sets one value - this.each(function() { - jQuery.data( this, key, value ); - }) : - - // Gets one value - // Try to fetch any internally stored data first - elem ? dataAttr( elem, key, jQuery.data( elem, key ) ) : null; - }, - - removeData: function( key ) { - return this.each(function() { - jQuery.removeData( this, key ); - }); - } -}); - -function dataAttr( elem, key, data ) { - // If nothing was found internally, try to fetch any - // data from the HTML5 data-* attribute - if ( data === undefined && elem.nodeType === 1 ) { - - var name = "data-" + key.replace( rmultiDash, "-$1" ).toLowerCase(); - - data = elem.getAttribute( name ); - - if ( typeof data === "string" ) { - try { - data = data === "true" ? true : - data === "false" ? false : - data === "null" ? null : - // Only convert to a number if it doesn't change the string - +data + "" === data ? +data : - rbrace.test( data ) ? jQuery.parseJSON( data ) : - data; - } catch( e ) {} - - // Make sure we set the data so it isn't changed later - jQuery.data( elem, key, data ); - - } else { - data = undefined; - } - } - - return data; -} - -// checks a cache object for emptiness -function isEmptyDataObject( obj ) { - var name; - for ( name in obj ) { - - // if the public data object is empty, the private is still empty - if ( name === "data" && jQuery.isEmptyObject( obj[name] ) ) { - continue; - } - if ( name !== "toJSON" ) { - return false; - } - } - - return true; -} -jQuery.extend({ - queue: function( elem, type, data ) { - var queue; - - if ( elem ) { - type = ( type || "fx" ) + "queue"; - queue = jQuery._data( elem, type ); - - // Speed up dequeue by getting out quickly if this is just a lookup - if ( data ) { - if ( !queue || jQuery.isArray(data) ) { - queue = jQuery._data( elem, type, jQuery.makeArray(data) ); - } else { - queue.push( data ); - } - } - return queue || []; - } - }, - - dequeue: function( elem, type ) { - type = type || "fx"; - - var queue = jQuery.queue( elem, type ), - startLength = queue.length, - fn = queue.shift(), - hooks = jQuery._queueHooks( elem, type ), - next = function() { - jQuery.dequeue( elem, type ); - }; - - // If the fx queue is dequeued, always remove the progress sentinel - if ( fn === "inprogress" ) { - fn = queue.shift(); - startLength--; - } - - if ( fn ) { - - // Add a progress sentinel to prevent the fx queue from being - // automatically dequeued - if ( type === "fx" ) { - queue.unshift( "inprogress" ); - } - - // clear up the last queue stop function - delete hooks.stop; - fn.call( elem, next, hooks ); - } - - if ( !startLength && hooks ) { - hooks.empty.fire(); - } - }, - - // not intended for public consumption - generates a queueHooks object, or returns the current one - _queueHooks: function( elem, type ) { - var key = type + "queueHooks"; - return jQuery._data( elem, key ) || jQuery._data( elem, key, { - empty: jQuery.Callbacks("once memory").add(function() { - jQuery._removeData( elem, type + "queue" ); - jQuery._removeData( elem, key ); - }) - }); - } -}); - -jQuery.fn.extend({ - queue: function( type, data ) { - var setter = 2; - - if ( typeof type !== "string" ) { - data = type; - type = "fx"; - setter--; - } - - if ( arguments.length < setter ) { - return jQuery.queue( this[0], type ); - } - - return data === undefined ? - this : - this.each(function() { - var queue = jQuery.queue( this, type, data ); - - // ensure a hooks for this queue - jQuery._queueHooks( this, type ); - - if ( type === "fx" && queue[0] !== "inprogress" ) { - jQuery.dequeue( this, type ); - } - }); - }, - dequeue: function( type ) { - return this.each(function() { - jQuery.dequeue( this, type ); - }); - }, - // Based off of the plugin by Clint Helfers, with permission. - // http://blindsignals.com/index.php/2009/07/jquery-delay/ - delay: function( time, type ) { - time = jQuery.fx ? jQuery.fx.speeds[ time ] || time : time; - type = type || "fx"; - - return this.queue( type, function( next, hooks ) { - var timeout = setTimeout( next, time ); - hooks.stop = function() { - clearTimeout( timeout ); - }; - }); - }, - clearQueue: function( type ) { - return this.queue( type || "fx", [] ); - }, - // Get a promise resolved when queues of a certain type - // are emptied (fx is the type by default) - promise: function( type, obj ) { - var tmp, - count = 1, - defer = jQuery.Deferred(), - elements = this, - i = this.length, - resolve = function() { - if ( !( --count ) ) { - defer.resolveWith( elements, [ elements ] ); - } - }; - - if ( typeof type !== "string" ) { - obj = type; - type = undefined; - } - type = type || "fx"; - - while( i-- ) { - tmp = jQuery._data( elements[ i ], type + "queueHooks" ); - if ( tmp && tmp.empty ) { - count++; - tmp.empty.add( resolve ); - } - } - resolve(); - return defer.promise( obj ); - } -}); -var nodeHook, boolHook, - rclass = /[\t\r\n\f]/g, - rreturn = /\r/g, - rfocusable = /^(?:input|select|textarea|button|object)$/i, - rclickable = /^(?:a|area)$/i, - ruseDefault = /^(?:checked|selected)$/i, - getSetAttribute = jQuery.support.getSetAttribute, - getSetInput = jQuery.support.input; - -jQuery.fn.extend({ - attr: function( name, value ) { - return jQuery.access( this, jQuery.attr, name, value, arguments.length > 1 ); - }, - - removeAttr: function( name ) { - return this.each(function() { - jQuery.removeAttr( this, name ); - }); - }, - - prop: function( name, value ) { - return jQuery.access( this, jQuery.prop, name, value, arguments.length > 1 ); - }, - - removeProp: function( name ) { - name = jQuery.propFix[ name ] || name; - return this.each(function() { - // try/catch handles cases where IE balks (such as removing a property on window) - try { - this[ name ] = undefined; - delete this[ name ]; - } catch( e ) {} - }); - }, - - addClass: function( value ) { - var classes, elem, cur, clazz, j, - i = 0, - len = this.length, - proceed = typeof value === "string" && value; - - if ( jQuery.isFunction( value ) ) { - return this.each(function( j ) { - jQuery( this ).addClass( value.call( this, j, this.className ) ); - }); - } - - if ( proceed ) { - // The disjunction here is for better compressibility (see removeClass) - classes = ( value || "" ).match( core_rnotwhite ) || []; - - for ( ; i < len; i++ ) { - elem = this[ i ]; - cur = elem.nodeType === 1 && ( elem.className ? - ( " " + elem.className + " " ).replace( rclass, " " ) : - " " - ); - - if ( cur ) { - j = 0; - while ( (clazz = classes[j++]) ) { - if ( cur.indexOf( " " + clazz + " " ) < 0 ) { - cur += clazz + " "; - } - } - elem.className = jQuery.trim( cur ); - - } - } - } - - return this; - }, - - removeClass: function( value ) { - var classes, elem, cur, clazz, j, - i = 0, - len = this.length, - proceed = arguments.length === 0 || typeof value === "string" && value; - - if ( jQuery.isFunction( value ) ) { - return this.each(function( j ) { - jQuery( this ).removeClass( value.call( this, j, this.className ) ); - }); - } - if ( proceed ) { - classes = ( value || "" ).match( core_rnotwhite ) || []; - - for ( ; i < len; i++ ) { - elem = this[ i ]; - // This expression is here for better compressibility (see addClass) - cur = elem.nodeType === 1 && ( elem.className ? - ( " " + elem.className + " " ).replace( rclass, " " ) : - "" - ); - - if ( cur ) { - j = 0; - while ( (clazz = classes[j++]) ) { - // Remove *all* instances - while ( cur.indexOf( " " + clazz + " " ) >= 0 ) { - cur = cur.replace( " " + clazz + " ", " " ); - } - } - elem.className = value ? jQuery.trim( cur ) : ""; - } - } - } - - return this; - }, - - toggleClass: function( value, stateVal ) { - var type = typeof value; - - if ( typeof stateVal === "boolean" && type === "string" ) { - return stateVal ? this.addClass( value ) : this.removeClass( value ); - } - - if ( jQuery.isFunction( value ) ) { - return this.each(function( i ) { - jQuery( this ).toggleClass( value.call(this, i, this.className, stateVal), stateVal ); - }); - } - - return this.each(function() { - if ( type === "string" ) { - // toggle individual class names - var className, - i = 0, - self = jQuery( this ), - classNames = value.match( core_rnotwhite ) || []; - - while ( (className = classNames[ i++ ]) ) { - // check each className given, space separated list - if ( self.hasClass( className ) ) { - self.removeClass( className ); - } else { - self.addClass( className ); - } - } - - // Toggle whole class name - } else if ( type === core_strundefined || type === "boolean" ) { - if ( this.className ) { - // store className if set - jQuery._data( this, "__className__", this.className ); - } - - // If the element has a class name or if we're passed "false", - // then remove the whole classname (if there was one, the above saved it). - // Otherwise bring back whatever was previously saved (if anything), - // falling back to the empty string if nothing was stored. - this.className = this.className || value === false ? "" : jQuery._data( this, "__className__" ) || ""; - } - }); - }, - - hasClass: function( selector ) { - var className = " " + selector + " ", - i = 0, - l = this.length; - for ( ; i < l; i++ ) { - if ( this[i].nodeType === 1 && (" " + this[i].className + " ").replace(rclass, " ").indexOf( className ) >= 0 ) { - return true; - } - } - - return false; - }, - - val: function( value ) { - var ret, hooks, isFunction, - elem = this[0]; - - if ( !arguments.length ) { - if ( elem ) { - hooks = jQuery.valHooks[ elem.type ] || jQuery.valHooks[ elem.nodeName.toLowerCase() ]; - - if ( hooks && "get" in hooks && (ret = hooks.get( elem, "value" )) !== undefined ) { - return ret; - } - - ret = elem.value; - - return typeof ret === "string" ? - // handle most common string cases - ret.replace(rreturn, "") : - // handle cases where value is null/undef or number - ret == null ? "" : ret; - } - - return; - } - - isFunction = jQuery.isFunction( value ); - - return this.each(function( i ) { - var val; - - if ( this.nodeType !== 1 ) { - return; - } - - if ( isFunction ) { - val = value.call( this, i, jQuery( this ).val() ); - } else { - val = value; - } - - // Treat null/undefined as ""; convert numbers to string - if ( val == null ) { - val = ""; - } else if ( typeof val === "number" ) { - val += ""; - } else if ( jQuery.isArray( val ) ) { - val = jQuery.map(val, function ( value ) { - return value == null ? "" : value + ""; - }); - } - - hooks = jQuery.valHooks[ this.type ] || jQuery.valHooks[ this.nodeName.toLowerCase() ]; - - // If set returns undefined, fall back to normal setting - if ( !hooks || !("set" in hooks) || hooks.set( this, val, "value" ) === undefined ) { - this.value = val; - } - }); - } -}); - -jQuery.extend({ - valHooks: { - option: { - get: function( elem ) { - // Use proper attribute retrieval(#6932, #12072) - var val = jQuery.find.attr( elem, "value" ); - return val != null ? - val : - elem.text; - } - }, - select: { - get: function( elem ) { - var value, option, - options = elem.options, - index = elem.selectedIndex, - one = elem.type === "select-one" || index < 0, - values = one ? null : [], - max = one ? index + 1 : options.length, - i = index < 0 ? - max : - one ? index : 0; - - // Loop through all the selected options - for ( ; i < max; i++ ) { - option = options[ i ]; - - // oldIE doesn't update selected after form reset (#2551) - if ( ( option.selected || i === index ) && - // Don't return options that are disabled or in a disabled optgroup - ( jQuery.support.optDisabled ? !option.disabled : option.getAttribute("disabled") === null ) && - ( !option.parentNode.disabled || !jQuery.nodeName( option.parentNode, "optgroup" ) ) ) { - - // Get the specific value for the option - value = jQuery( option ).val(); - - // We don't need an array for one selects - if ( one ) { - return value; - } - - // Multi-Selects return an array - values.push( value ); - } - } - - return values; - }, - - set: function( elem, value ) { - var optionSet, option, - options = elem.options, - values = jQuery.makeArray( value ), - i = options.length; - - while ( i-- ) { - option = options[ i ]; - if ( (option.selected = jQuery.inArray( jQuery(option).val(), values ) >= 0) ) { - optionSet = true; - } - } - - // force browsers to behave consistently when non-matching value is set - if ( !optionSet ) { - elem.selectedIndex = -1; - } - return values; - } - } - }, - - attr: function( elem, name, value ) { - var hooks, ret, - nType = elem.nodeType; - - // don't get/set attributes on text, comment and attribute nodes - if ( !elem || nType === 3 || nType === 8 || nType === 2 ) { - return; - } - - // Fallback to prop when attributes are not supported - if ( typeof elem.getAttribute === core_strundefined ) { - return jQuery.prop( elem, name, value ); - } - - // All attributes are lowercase - // Grab necessary hook if one is defined - if ( nType !== 1 || !jQuery.isXMLDoc( elem ) ) { - name = name.toLowerCase(); - hooks = jQuery.attrHooks[ name ] || - ( jQuery.expr.match.bool.test( name ) ? boolHook : nodeHook ); - } - - if ( value !== undefined ) { - - if ( value === null ) { - jQuery.removeAttr( elem, name ); - - } else if ( hooks && "set" in hooks && (ret = hooks.set( elem, value, name )) !== undefined ) { - return ret; - - } else { - elem.setAttribute( name, value + "" ); - return value; - } - - } else if ( hooks && "get" in hooks && (ret = hooks.get( elem, name )) !== null ) { - return ret; - - } else { - ret = jQuery.find.attr( elem, name ); - - // Non-existent attributes return null, we normalize to undefined - return ret == null ? - undefined : - ret; - } - }, - - removeAttr: function( elem, value ) { - var name, propName, - i = 0, - attrNames = value && value.match( core_rnotwhite ); - - if ( attrNames && elem.nodeType === 1 ) { - while ( (name = attrNames[i++]) ) { - propName = jQuery.propFix[ name ] || name; - - // Boolean attributes get special treatment (#10870) - if ( jQuery.expr.match.bool.test( name ) ) { - // Set corresponding property to false - if ( getSetInput && getSetAttribute || !ruseDefault.test( name ) ) { - elem[ propName ] = false; - // Support: IE<9 - // Also clear defaultChecked/defaultSelected (if appropriate) - } else { - elem[ jQuery.camelCase( "default-" + name ) ] = - elem[ propName ] = false; - } - - // See #9699 for explanation of this approach (setting first, then removal) - } else { - jQuery.attr( elem, name, "" ); - } - - elem.removeAttribute( getSetAttribute ? name : propName ); - } - } - }, - - attrHooks: { - type: { - set: function( elem, value ) { - if ( !jQuery.support.radioValue && value === "radio" && jQuery.nodeName(elem, "input") ) { - // Setting the type on a radio button after the value resets the value in IE6-9 - // Reset value to default in case type is set after value during creation - var val = elem.value; - elem.setAttribute( "type", value ); - if ( val ) { - elem.value = val; - } - return value; - } - } - } - }, - - propFix: { - "for": "htmlFor", - "class": "className" - }, - - prop: function( elem, name, value ) { - var ret, hooks, notxml, - nType = elem.nodeType; - - // don't get/set properties on text, comment and attribute nodes - if ( !elem || nType === 3 || nType === 8 || nType === 2 ) { - return; - } - - notxml = nType !== 1 || !jQuery.isXMLDoc( elem ); - - if ( notxml ) { - // Fix name and attach hooks - name = jQuery.propFix[ name ] || name; - hooks = jQuery.propHooks[ name ]; - } - - if ( value !== undefined ) { - return hooks && "set" in hooks && (ret = hooks.set( elem, value, name )) !== undefined ? - ret : - ( elem[ name ] = value ); - - } else { - return hooks && "get" in hooks && (ret = hooks.get( elem, name )) !== null ? - ret : - elem[ name ]; - } - }, - - propHooks: { - tabIndex: { - get: function( elem ) { - // elem.tabIndex doesn't always return the correct value when it hasn't been explicitly set - // http://fluidproject.org/blog/2008/01/09/getting-setting-and-removing-tabindex-values-with-javascript/ - // Use proper attribute retrieval(#12072) - var tabindex = jQuery.find.attr( elem, "tabindex" ); - - return tabindex ? - parseInt( tabindex, 10 ) : - rfocusable.test( elem.nodeName ) || rclickable.test( elem.nodeName ) && elem.href ? - 0 : - -1; - } - } - } -}); - -// Hooks for boolean attributes -boolHook = { - set: function( elem, value, name ) { - if ( value === false ) { - // Remove boolean attributes when set to false - jQuery.removeAttr( elem, name ); - } else if ( getSetInput && getSetAttribute || !ruseDefault.test( name ) ) { - // IE<8 needs the *property* name - elem.setAttribute( !getSetAttribute && jQuery.propFix[ name ] || name, name ); - - // Use defaultChecked and defaultSelected for oldIE - } else { - elem[ jQuery.camelCase( "default-" + name ) ] = elem[ name ] = true; - } - - return name; - } -}; -jQuery.each( jQuery.expr.match.bool.source.match( /\w+/g ), function( i, name ) { - var getter = jQuery.expr.attrHandle[ name ] || jQuery.find.attr; - - jQuery.expr.attrHandle[ name ] = getSetInput && getSetAttribute || !ruseDefault.test( name ) ? - function( elem, name, isXML ) { - var fn = jQuery.expr.attrHandle[ name ], - ret = isXML ? - undefined : - /* jshint eqeqeq: false */ - (jQuery.expr.attrHandle[ name ] = undefined) != - getter( elem, name, isXML ) ? - - name.toLowerCase() : - null; - jQuery.expr.attrHandle[ name ] = fn; - return ret; - } : - function( elem, name, isXML ) { - return isXML ? - undefined : - elem[ jQuery.camelCase( "default-" + name ) ] ? - name.toLowerCase() : - null; - }; -}); - -// fix oldIE attroperties -if ( !getSetInput || !getSetAttribute ) { - jQuery.attrHooks.value = { - set: function( elem, value, name ) { - if ( jQuery.nodeName( elem, "input" ) ) { - // Does not return so that setAttribute is also used - elem.defaultValue = value; - } else { - // Use nodeHook if defined (#1954); otherwise setAttribute is fine - return nodeHook && nodeHook.set( elem, value, name ); - } - } - }; -} - -// IE6/7 do not support getting/setting some attributes with get/setAttribute -if ( !getSetAttribute ) { - - // Use this for any attribute in IE6/7 - // This fixes almost every IE6/7 issue - nodeHook = { - set: function( elem, value, name ) { - // Set the existing or create a new attribute node - var ret = elem.getAttributeNode( name ); - if ( !ret ) { - elem.setAttributeNode( - (ret = elem.ownerDocument.createAttribute( name )) - ); - } - - ret.value = value += ""; - - // Break association with cloned elements by also using setAttribute (#9646) - return name === "value" || value === elem.getAttribute( name ) ? - value : - undefined; - } - }; - jQuery.expr.attrHandle.id = jQuery.expr.attrHandle.name = jQuery.expr.attrHandle.coords = - // Some attributes are constructed with empty-string values when not defined - function( elem, name, isXML ) { - var ret; - return isXML ? - undefined : - (ret = elem.getAttributeNode( name )) && ret.value !== "" ? - ret.value : - null; - }; - jQuery.valHooks.button = { - get: function( elem, name ) { - var ret = elem.getAttributeNode( name ); - return ret && ret.specified ? - ret.value : - undefined; - }, - set: nodeHook.set - }; - - // Set contenteditable to false on removals(#10429) - // Setting to empty string throws an error as an invalid value - jQuery.attrHooks.contenteditable = { - set: function( elem, value, name ) { - nodeHook.set( elem, value === "" ? false : value, name ); - } - }; - - // Set width and height to auto instead of 0 on empty string( Bug #8150 ) - // This is for removals - jQuery.each([ "width", "height" ], function( i, name ) { - jQuery.attrHooks[ name ] = { - set: function( elem, value ) { - if ( value === "" ) { - elem.setAttribute( name, "auto" ); - return value; - } - } - }; - }); -} - - -// Some attributes require a special call on IE -// http://msdn.microsoft.com/en-us/library/ms536429%28VS.85%29.aspx -if ( !jQuery.support.hrefNormalized ) { - // href/src property should get the full normalized URL (#10299/#12915) - jQuery.each([ "href", "src" ], function( i, name ) { - jQuery.propHooks[ name ] = { - get: function( elem ) { - return elem.getAttribute( name, 4 ); - } - }; - }); -} - -if ( !jQuery.support.style ) { - jQuery.attrHooks.style = { - get: function( elem ) { - // Return undefined in the case of empty string - // Note: IE uppercases css property names, but if we were to .toLowerCase() - // .cssText, that would destroy case senstitivity in URL's, like in "background" - return elem.style.cssText || undefined; - }, - set: function( elem, value ) { - return ( elem.style.cssText = value + "" ); - } - }; -} - -// Safari mis-reports the default selected property of an option -// Accessing the parent's selectedIndex property fixes it -if ( !jQuery.support.optSelected ) { - jQuery.propHooks.selected = { - get: function( elem ) { - var parent = elem.parentNode; - - if ( parent ) { - parent.selectedIndex; - - // Make sure that it also works with optgroups, see #5701 - if ( parent.parentNode ) { - parent.parentNode.selectedIndex; - } - } - return null; - } - }; -} - -jQuery.each([ - "tabIndex", - "readOnly", - "maxLength", - "cellSpacing", - "cellPadding", - "rowSpan", - "colSpan", - "useMap", - "frameBorder", - "contentEditable" -], function() { - jQuery.propFix[ this.toLowerCase() ] = this; -}); - -// IE6/7 call enctype encoding -if ( !jQuery.support.enctype ) { - jQuery.propFix.enctype = "encoding"; -} - -// Radios and checkboxes getter/setter -jQuery.each([ "radio", "checkbox" ], function() { - jQuery.valHooks[ this ] = { - set: function( elem, value ) { - if ( jQuery.isArray( value ) ) { - return ( elem.checked = jQuery.inArray( jQuery(elem).val(), value ) >= 0 ); - } - } - }; - if ( !jQuery.support.checkOn ) { - jQuery.valHooks[ this ].get = function( elem ) { - // Support: Webkit - // "" is returned instead of "on" if a value isn't specified - return elem.getAttribute("value") === null ? "on" : elem.value; - }; - } -}); -var rformElems = /^(?:input|select|textarea)$/i, - rkeyEvent = /^key/, - rmouseEvent = /^(?:mouse|contextmenu)|click/, - rfocusMorph = /^(?:focusinfocus|focusoutblur)$/, - rtypenamespace = /^([^.]*)(?:\.(.+)|)$/; - -function returnTrue() { - return true; -} - -function returnFalse() { - return false; -} - -function safeActiveElement() { - try { - return document.activeElement; - } catch ( err ) { } -} - -/* - * Helper functions for managing events -- not part of the public interface. - * Props to Dean Edwards' addEvent library for many of the ideas. - */ -jQuery.event = { - - global: {}, - - add: function( elem, types, handler, data, selector ) { - var tmp, events, t, handleObjIn, - special, eventHandle, handleObj, - handlers, type, namespaces, origType, - elemData = jQuery._data( elem ); - - // Don't attach events to noData or text/comment nodes (but allow plain objects) - if ( !elemData ) { - return; - } - - // Caller can pass in an object of custom data in lieu of the handler - if ( handler.handler ) { - handleObjIn = handler; - handler = handleObjIn.handler; - selector = handleObjIn.selector; - } - - // Make sure that the handler has a unique ID, used to find/remove it later - if ( !handler.guid ) { - handler.guid = jQuery.guid++; - } - - // Init the element's event structure and main handler, if this is the first - if ( !(events = elemData.events) ) { - events = elemData.events = {}; - } - if ( !(eventHandle = elemData.handle) ) { - eventHandle = elemData.handle = function( e ) { - // Discard the second event of a jQuery.event.trigger() and - // when an event is called after a page has unloaded - return typeof jQuery !== core_strundefined && (!e || jQuery.event.triggered !== e.type) ? - jQuery.event.dispatch.apply( eventHandle.elem, arguments ) : - undefined; - }; - // Add elem as a property of the handle fn to prevent a memory leak with IE non-native events - eventHandle.elem = elem; - } - - // Handle multiple events separated by a space - types = ( types || "" ).match( core_rnotwhite ) || [""]; - t = types.length; - while ( t-- ) { - tmp = rtypenamespace.exec( types[t] ) || []; - type = origType = tmp[1]; - namespaces = ( tmp[2] || "" ).split( "." ).sort(); - - // There *must* be a type, no attaching namespace-only handlers - if ( !type ) { - continue; - } - - // If event changes its type, use the special event handlers for the changed type - special = jQuery.event.special[ type ] || {}; - - // If selector defined, determine special event api type, otherwise given type - type = ( selector ? special.delegateType : special.bindType ) || type; - - // Update special based on newly reset type - special = jQuery.event.special[ type ] || {}; - - // handleObj is passed to all event handlers - handleObj = jQuery.extend({ - type: type, - origType: origType, - data: data, - handler: handler, - guid: handler.guid, - selector: selector, - needsContext: selector && jQuery.expr.match.needsContext.test( selector ), - namespace: namespaces.join(".") - }, handleObjIn ); - - // Init the event handler queue if we're the first - if ( !(handlers = events[ type ]) ) { - handlers = events[ type ] = []; - handlers.delegateCount = 0; - - // Only use addEventListener/attachEvent if the special events handler returns false - if ( !special.setup || special.setup.call( elem, data, namespaces, eventHandle ) === false ) { - // Bind the global event handler to the element - if ( elem.addEventListener ) { - elem.addEventListener( type, eventHandle, false ); - - } else if ( elem.attachEvent ) { - elem.attachEvent( "on" + type, eventHandle ); - } - } - } - - if ( special.add ) { - special.add.call( elem, handleObj ); - - if ( !handleObj.handler.guid ) { - handleObj.handler.guid = handler.guid; - } - } - - // Add to the element's handler list, delegates in front - if ( selector ) { - handlers.splice( handlers.delegateCount++, 0, handleObj ); - } else { - handlers.push( handleObj ); - } - - // Keep track of which events have ever been used, for event optimization - jQuery.event.global[ type ] = true; - } - - // Nullify elem to prevent memory leaks in IE - elem = null; - }, - - // Detach an event or set of events from an element - remove: function( elem, types, handler, selector, mappedTypes ) { - var j, handleObj, tmp, - origCount, t, events, - special, handlers, type, - namespaces, origType, - elemData = jQuery.hasData( elem ) && jQuery._data( elem ); - - if ( !elemData || !(events = elemData.events) ) { - return; - } - - // Once for each type.namespace in types; type may be omitted - types = ( types || "" ).match( core_rnotwhite ) || [""]; - t = types.length; - while ( t-- ) { - tmp = rtypenamespace.exec( types[t] ) || []; - type = origType = tmp[1]; - namespaces = ( tmp[2] || "" ).split( "." ).sort(); - - // Unbind all events (on this namespace, if provided) for the element - if ( !type ) { - for ( type in events ) { - jQuery.event.remove( elem, type + types[ t ], handler, selector, true ); - } - continue; - } - - special = jQuery.event.special[ type ] || {}; - type = ( selector ? special.delegateType : special.bindType ) || type; - handlers = events[ type ] || []; - tmp = tmp[2] && new RegExp( "(^|\\.)" + namespaces.join("\\.(?:.*\\.|)") + "(\\.|$)" ); - - // Remove matching events - origCount = j = handlers.length; - while ( j-- ) { - handleObj = handlers[ j ]; - - if ( ( mappedTypes || origType === handleObj.origType ) && - ( !handler || handler.guid === handleObj.guid ) && - ( !tmp || tmp.test( handleObj.namespace ) ) && - ( !selector || selector === handleObj.selector || selector === "**" && handleObj.selector ) ) { - handlers.splice( j, 1 ); - - if ( handleObj.selector ) { - handlers.delegateCount--; - } - if ( special.remove ) { - special.remove.call( elem, handleObj ); - } - } - } - - // Remove generic event handler if we removed something and no more handlers exist - // (avoids potential for endless recursion during removal of special event handlers) - if ( origCount && !handlers.length ) { - if ( !special.teardown || special.teardown.call( elem, namespaces, elemData.handle ) === false ) { - jQuery.removeEvent( elem, type, elemData.handle ); - } - - delete events[ type ]; - } - } - - // Remove the expando if it's no longer used - if ( jQuery.isEmptyObject( events ) ) { - delete elemData.handle; - - // removeData also checks for emptiness and clears the expando if empty - // so use it instead of delete - jQuery._removeData( elem, "events" ); - } - }, - - trigger: function( event, data, elem, onlyHandlers ) { - var handle, ontype, cur, - bubbleType, special, tmp, i, - eventPath = [ elem || document ], - type = core_hasOwn.call( event, "type" ) ? event.type : event, - namespaces = core_hasOwn.call( event, "namespace" ) ? event.namespace.split(".") : []; - - cur = tmp = elem = elem || document; - - // Don't do events on text and comment nodes - if ( elem.nodeType === 3 || elem.nodeType === 8 ) { - return; - } - - // focus/blur morphs to focusin/out; ensure we're not firing them right now - if ( rfocusMorph.test( type + jQuery.event.triggered ) ) { - return; - } - - if ( type.indexOf(".") >= 0 ) { - // Namespaced trigger; create a regexp to match event type in handle() - namespaces = type.split("."); - type = namespaces.shift(); - namespaces.sort(); - } - ontype = type.indexOf(":") < 0 && "on" + type; - - // Caller can pass in a jQuery.Event object, Object, or just an event type string - event = event[ jQuery.expando ] ? - event : - new jQuery.Event( type, typeof event === "object" && event ); - - // Trigger bitmask: & 1 for native handlers; & 2 for jQuery (always true) - event.isTrigger = onlyHandlers ? 2 : 3; - event.namespace = namespaces.join("."); - event.namespace_re = event.namespace ? - new RegExp( "(^|\\.)" + namespaces.join("\\.(?:.*\\.|)") + "(\\.|$)" ) : - null; - - // Clean up the event in case it is being reused - event.result = undefined; - if ( !event.target ) { - event.target = elem; - } - - // Clone any incoming data and prepend the event, creating the handler arg list - data = data == null ? - [ event ] : - jQuery.makeArray( data, [ event ] ); - - // Allow special events to draw outside the lines - special = jQuery.event.special[ type ] || {}; - if ( !onlyHandlers && special.trigger && special.trigger.apply( elem, data ) === false ) { - return; - } - - // Determine event propagation path in advance, per W3C events spec (#9951) - // Bubble up to document, then to window; watch for a global ownerDocument var (#9724) - if ( !onlyHandlers && !special.noBubble && !jQuery.isWindow( elem ) ) { - - bubbleType = special.delegateType || type; - if ( !rfocusMorph.test( bubbleType + type ) ) { - cur = cur.parentNode; - } - for ( ; cur; cur = cur.parentNode ) { - eventPath.push( cur ); - tmp = cur; - } - - // Only add window if we got to document (e.g., not plain obj or detached DOM) - if ( tmp === (elem.ownerDocument || document) ) { - eventPath.push( tmp.defaultView || tmp.parentWindow || window ); - } - } - - // Fire handlers on the event path - i = 0; - while ( (cur = eventPath[i++]) && !event.isPropagationStopped() ) { - - event.type = i > 1 ? - bubbleType : - special.bindType || type; - - // jQuery handler - handle = ( jQuery._data( cur, "events" ) || {} )[ event.type ] && jQuery._data( cur, "handle" ); - if ( handle ) { - handle.apply( cur, data ); - } - - // Native handler - handle = ontype && cur[ ontype ]; - if ( handle && jQuery.acceptData( cur ) && handle.apply && handle.apply( cur, data ) === false ) { - event.preventDefault(); - } - } - event.type = type; - - // If nobody prevented the default action, do it now - if ( !onlyHandlers && !event.isDefaultPrevented() ) { - - if ( (!special._default || special._default.apply( eventPath.pop(), data ) === false) && - jQuery.acceptData( elem ) ) { - - // Call a native DOM method on the target with the same name name as the event. - // Can't use an .isFunction() check here because IE6/7 fails that test. - // Don't do default actions on window, that's where global variables be (#6170) - if ( ontype && elem[ type ] && !jQuery.isWindow( elem ) ) { - - // Don't re-trigger an onFOO event when we call its FOO() method - tmp = elem[ ontype ]; - - if ( tmp ) { - elem[ ontype ] = null; - } - - // Prevent re-triggering of the same event, since we already bubbled it above - jQuery.event.triggered = type; - try { - elem[ type ](); - } catch ( e ) { - // IE<9 dies on focus/blur to hidden element (#1486,#12518) - // only reproducible on winXP IE8 native, not IE9 in IE8 mode - } - jQuery.event.triggered = undefined; - - if ( tmp ) { - elem[ ontype ] = tmp; - } - } - } - } - - return event.result; - }, - - dispatch: function( event ) { - - // Make a writable jQuery.Event from the native event object - event = jQuery.event.fix( event ); - - var i, ret, handleObj, matched, j, - handlerQueue = [], - args = core_slice.call( arguments ), - handlers = ( jQuery._data( this, "events" ) || {} )[ event.type ] || [], - special = jQuery.event.special[ event.type ] || {}; - - // Use the fix-ed jQuery.Event rather than the (read-only) native event - args[0] = event; - event.delegateTarget = this; - - // Call the preDispatch hook for the mapped type, and let it bail if desired - if ( special.preDispatch && special.preDispatch.call( this, event ) === false ) { - return; - } - - // Determine handlers - handlerQueue = jQuery.event.handlers.call( this, event, handlers ); - - // Run delegates first; they may want to stop propagation beneath us - i = 0; - while ( (matched = handlerQueue[ i++ ]) && !event.isPropagationStopped() ) { - event.currentTarget = matched.elem; - - j = 0; - while ( (handleObj = matched.handlers[ j++ ]) && !event.isImmediatePropagationStopped() ) { - - // Triggered event must either 1) have no namespace, or - // 2) have namespace(s) a subset or equal to those in the bound event (both can have no namespace). - if ( !event.namespace_re || event.namespace_re.test( handleObj.namespace ) ) { - - event.handleObj = handleObj; - event.data = handleObj.data; - - ret = ( (jQuery.event.special[ handleObj.origType ] || {}).handle || handleObj.handler ) - .apply( matched.elem, args ); - - if ( ret !== undefined ) { - if ( (event.result = ret) === false ) { - event.preventDefault(); - event.stopPropagation(); - } - } - } - } - } - - // Call the postDispatch hook for the mapped type - if ( special.postDispatch ) { - special.postDispatch.call( this, event ); - } - - return event.result; - }, - - handlers: function( event, handlers ) { - var sel, handleObj, matches, i, - handlerQueue = [], - delegateCount = handlers.delegateCount, - cur = event.target; - - // Find delegate handlers - // Black-hole SVG instance trees (#13180) - // Avoid non-left-click bubbling in Firefox (#3861) - if ( delegateCount && cur.nodeType && (!event.button || event.type !== "click") ) { - - /* jshint eqeqeq: false */ - for ( ; cur != this; cur = cur.parentNode || this ) { - /* jshint eqeqeq: true */ - - // Don't check non-elements (#13208) - // Don't process clicks on disabled elements (#6911, #8165, #11382, #11764) - if ( cur.nodeType === 1 && (cur.disabled !== true || event.type !== "click") ) { - matches = []; - for ( i = 0; i < delegateCount; i++ ) { - handleObj = handlers[ i ]; - - // Don't conflict with Object.prototype properties (#13203) - sel = handleObj.selector + " "; - - if ( matches[ sel ] === undefined ) { - matches[ sel ] = handleObj.needsContext ? - jQuery( sel, this ).index( cur ) >= 0 : - jQuery.find( sel, this, null, [ cur ] ).length; - } - if ( matches[ sel ] ) { - matches.push( handleObj ); - } - } - if ( matches.length ) { - handlerQueue.push({ elem: cur, handlers: matches }); - } - } - } - } - - // Add the remaining (directly-bound) handlers - if ( delegateCount < handlers.length ) { - handlerQueue.push({ elem: this, handlers: handlers.slice( delegateCount ) }); - } - - return handlerQueue; - }, - - fix: function( event ) { - if ( event[ jQuery.expando ] ) { - return event; - } - - // Create a writable copy of the event object and normalize some properties - var i, prop, copy, - type = event.type, - originalEvent = event, - fixHook = this.fixHooks[ type ]; - - if ( !fixHook ) { - this.fixHooks[ type ] = fixHook = - rmouseEvent.test( type ) ? this.mouseHooks : - rkeyEvent.test( type ) ? this.keyHooks : - {}; - } - copy = fixHook.props ? this.props.concat( fixHook.props ) : this.props; - - event = new jQuery.Event( originalEvent ); - - i = copy.length; - while ( i-- ) { - prop = copy[ i ]; - event[ prop ] = originalEvent[ prop ]; - } - - // Support: IE<9 - // Fix target property (#1925) - if ( !event.target ) { - event.target = originalEvent.srcElement || document; - } - - // Support: Chrome 23+, Safari? - // Target should not be a text node (#504, #13143) - if ( event.target.nodeType === 3 ) { - event.target = event.target.parentNode; - } - - // Support: IE<9 - // For mouse/key events, metaKey==false if it's undefined (#3368, #11328) - event.metaKey = !!event.metaKey; - - return fixHook.filter ? fixHook.filter( event, originalEvent ) : event; - }, - - // Includes some event props shared by KeyEvent and MouseEvent - props: "altKey bubbles cancelable ctrlKey currentTarget eventPhase metaKey relatedTarget shiftKey target timeStamp view which".split(" "), - - fixHooks: {}, - - keyHooks: { - props: "char charCode key keyCode".split(" "), - filter: function( event, original ) { - - // Add which for key events - if ( event.which == null ) { - event.which = original.charCode != null ? original.charCode : original.keyCode; - } - - return event; - } - }, - - mouseHooks: { - props: "button buttons clientX clientY fromElement offsetX offsetY pageX pageY screenX screenY toElement".split(" "), - filter: function( event, original ) { - var body, eventDoc, doc, - button = original.button, - fromElement = original.fromElement; - - // Calculate pageX/Y if missing and clientX/Y available - if ( event.pageX == null && original.clientX != null ) { - eventDoc = event.target.ownerDocument || document; - doc = eventDoc.documentElement; - body = eventDoc.body; - - event.pageX = original.clientX + ( doc && doc.scrollLeft || body && body.scrollLeft || 0 ) - ( doc && doc.clientLeft || body && body.clientLeft || 0 ); - event.pageY = original.clientY + ( doc && doc.scrollTop || body && body.scrollTop || 0 ) - ( doc && doc.clientTop || body && body.clientTop || 0 ); - } - - // Add relatedTarget, if necessary - if ( !event.relatedTarget && fromElement ) { - event.relatedTarget = fromElement === event.target ? original.toElement : fromElement; - } - - // Add which for click: 1 === left; 2 === middle; 3 === right - // Note: button is not normalized, so don't use it - if ( !event.which && button !== undefined ) { - event.which = ( button & 1 ? 1 : ( button & 2 ? 3 : ( button & 4 ? 2 : 0 ) ) ); - } - - return event; - } - }, - - special: { - load: { - // Prevent triggered image.load events from bubbling to window.load - noBubble: true - }, - focus: { - // Fire native event if possible so blur/focus sequence is correct - trigger: function() { - if ( this !== safeActiveElement() && this.focus ) { - try { - this.focus(); - return false; - } catch ( e ) { - // Support: IE<9 - // If we error on focus to hidden element (#1486, #12518), - // let .trigger() run the handlers - } - } - }, - delegateType: "focusin" - }, - blur: { - trigger: function() { - if ( this === safeActiveElement() && this.blur ) { - this.blur(); - return false; - } - }, - delegateType: "focusout" - }, - click: { - // For checkbox, fire native event so checked state will be right - trigger: function() { - if ( jQuery.nodeName( this, "input" ) && this.type === "checkbox" && this.click ) { - this.click(); - return false; - } - }, - - // For cross-browser consistency, don't fire native .click() on links - _default: function( event ) { - return jQuery.nodeName( event.target, "a" ); - } - }, - - beforeunload: { - postDispatch: function( event ) { - - // Even when returnValue equals to undefined Firefox will still show alert - if ( event.result !== undefined ) { - event.originalEvent.returnValue = event.result; - } - } - } - }, - - simulate: function( type, elem, event, bubble ) { - // Piggyback on a donor event to simulate a different one. - // Fake originalEvent to avoid donor's stopPropagation, but if the - // simulated event prevents default then we do the same on the donor. - var e = jQuery.extend( - new jQuery.Event(), - event, - { - type: type, - isSimulated: true, - originalEvent: {} - } - ); - if ( bubble ) { - jQuery.event.trigger( e, null, elem ); - } else { - jQuery.event.dispatch.call( elem, e ); - } - if ( e.isDefaultPrevented() ) { - event.preventDefault(); - } - } -}; - -jQuery.removeEvent = document.removeEventListener ? - function( elem, type, handle ) { - if ( elem.removeEventListener ) { - elem.removeEventListener( type, handle, false ); - } - } : - function( elem, type, handle ) { - var name = "on" + type; - - if ( elem.detachEvent ) { - - // #8545, #7054, preventing memory leaks for custom events in IE6-8 - // detachEvent needed property on element, by name of that event, to properly expose it to GC - if ( typeof elem[ name ] === core_strundefined ) { - elem[ name ] = null; - } - - elem.detachEvent( name, handle ); - } - }; - -jQuery.Event = function( src, props ) { - // Allow instantiation without the 'new' keyword - if ( !(this instanceof jQuery.Event) ) { - return new jQuery.Event( src, props ); - } - - // Event object - if ( src && src.type ) { - this.originalEvent = src; - this.type = src.type; - - // Events bubbling up the document may have been marked as prevented - // by a handler lower down the tree; reflect the correct value. - this.isDefaultPrevented = ( src.defaultPrevented || src.returnValue === false || - src.getPreventDefault && src.getPreventDefault() ) ? returnTrue : returnFalse; - - // Event type - } else { - this.type = src; - } - - // Put explicitly provided properties onto the event object - if ( props ) { - jQuery.extend( this, props ); - } - - // Create a timestamp if incoming event doesn't have one - this.timeStamp = src && src.timeStamp || jQuery.now(); - - // Mark it as fixed - this[ jQuery.expando ] = true; -}; - -// jQuery.Event is based on DOM3 Events as specified by the ECMAScript Language Binding -// http://www.w3.org/TR/2003/WD-DOM-Level-3-Events-20030331/ecma-script-binding.html -jQuery.Event.prototype = { - isDefaultPrevented: returnFalse, - isPropagationStopped: returnFalse, - isImmediatePropagationStopped: returnFalse, - - preventDefault: function() { - var e = this.originalEvent; - - this.isDefaultPrevented = returnTrue; - if ( !e ) { - return; - } - - // If preventDefault exists, run it on the original event - if ( e.preventDefault ) { - e.preventDefault(); - - // Support: IE - // Otherwise set the returnValue property of the original event to false - } else { - e.returnValue = false; - } - }, - stopPropagation: function() { - var e = this.originalEvent; - - this.isPropagationStopped = returnTrue; - if ( !e ) { - return; - } - // If stopPropagation exists, run it on the original event - if ( e.stopPropagation ) { - e.stopPropagation(); - } - - // Support: IE - // Set the cancelBubble property of the original event to true - e.cancelBubble = true; - }, - stopImmediatePropagation: function() { - this.isImmediatePropagationStopped = returnTrue; - this.stopPropagation(); - } -}; - -// Create mouseenter/leave events using mouseover/out and event-time checks -jQuery.each({ - mouseenter: "mouseover", - mouseleave: "mouseout" -}, function( orig, fix ) { - jQuery.event.special[ orig ] = { - delegateType: fix, - bindType: fix, - - handle: function( event ) { - var ret, - target = this, - related = event.relatedTarget, - handleObj = event.handleObj; - - // For mousenter/leave call the handler if related is outside the target. - // NB: No relatedTarget if the mouse left/entered the browser window - if ( !related || (related !== target && !jQuery.contains( target, related )) ) { - event.type = handleObj.origType; - ret = handleObj.handler.apply( this, arguments ); - event.type = fix; - } - return ret; - } - }; -}); - -// IE submit delegation -if ( !jQuery.support.submitBubbles ) { - - jQuery.event.special.submit = { - setup: function() { - // Only need this for delegated form submit events - if ( jQuery.nodeName( this, "form" ) ) { - return false; - } - - // Lazy-add a submit handler when a descendant form may potentially be submitted - jQuery.event.add( this, "click._submit keypress._submit", function( e ) { - // Node name check avoids a VML-related crash in IE (#9807) - var elem = e.target, - form = jQuery.nodeName( elem, "input" ) || jQuery.nodeName( elem, "button" ) ? elem.form : undefined; - if ( form && !jQuery._data( form, "submitBubbles" ) ) { - jQuery.event.add( form, "submit._submit", function( event ) { - event._submit_bubble = true; - }); - jQuery._data( form, "submitBubbles", true ); - } - }); - // return undefined since we don't need an event listener - }, - - postDispatch: function( event ) { - // If form was submitted by the user, bubble the event up the tree - if ( event._submit_bubble ) { - delete event._submit_bubble; - if ( this.parentNode && !event.isTrigger ) { - jQuery.event.simulate( "submit", this.parentNode, event, true ); - } - } - }, - - teardown: function() { - // Only need this for delegated form submit events - if ( jQuery.nodeName( this, "form" ) ) { - return false; - } - - // Remove delegated handlers; cleanData eventually reaps submit handlers attached above - jQuery.event.remove( this, "._submit" ); - } - }; -} - -// IE change delegation and checkbox/radio fix -if ( !jQuery.support.changeBubbles ) { - - jQuery.event.special.change = { - - setup: function() { - - if ( rformElems.test( this.nodeName ) ) { - // IE doesn't fire change on a check/radio until blur; trigger it on click - // after a propertychange. Eat the blur-change in special.change.handle. - // This still fires onchange a second time for check/radio after blur. - if ( this.type === "checkbox" || this.type === "radio" ) { - jQuery.event.add( this, "propertychange._change", function( event ) { - if ( event.originalEvent.propertyName === "checked" ) { - this._just_changed = true; - } - }); - jQuery.event.add( this, "click._change", function( event ) { - if ( this._just_changed && !event.isTrigger ) { - this._just_changed = false; - } - // Allow triggered, simulated change events (#11500) - jQuery.event.simulate( "change", this, event, true ); - }); - } - return false; - } - // Delegated event; lazy-add a change handler on descendant inputs - jQuery.event.add( this, "beforeactivate._change", function( e ) { - var elem = e.target; - - if ( rformElems.test( elem.nodeName ) && !jQuery._data( elem, "changeBubbles" ) ) { - jQuery.event.add( elem, "change._change", function( event ) { - if ( this.parentNode && !event.isSimulated && !event.isTrigger ) { - jQuery.event.simulate( "change", this.parentNode, event, true ); - } - }); - jQuery._data( elem, "changeBubbles", true ); - } - }); - }, - - handle: function( event ) { - var elem = event.target; - - // Swallow native change events from checkbox/radio, we already triggered them above - if ( this !== elem || event.isSimulated || event.isTrigger || (elem.type !== "radio" && elem.type !== "checkbox") ) { - return event.handleObj.handler.apply( this, arguments ); - } - }, - - teardown: function() { - jQuery.event.remove( this, "._change" ); - - return !rformElems.test( this.nodeName ); - } - }; -} - -// Create "bubbling" focus and blur events -if ( !jQuery.support.focusinBubbles ) { - jQuery.each({ focus: "focusin", blur: "focusout" }, function( orig, fix ) { - - // Attach a single capturing handler while someone wants focusin/focusout - var attaches = 0, - handler = function( event ) { - jQuery.event.simulate( fix, event.target, jQuery.event.fix( event ), true ); - }; - - jQuery.event.special[ fix ] = { - setup: function() { - if ( attaches++ === 0 ) { - document.addEventListener( orig, handler, true ); - } - }, - teardown: function() { - if ( --attaches === 0 ) { - document.removeEventListener( orig, handler, true ); - } - } - }; - }); -} - -jQuery.fn.extend({ - - on: function( types, selector, data, fn, /*INTERNAL*/ one ) { - var type, origFn; - - // Types can be a map of types/handlers - if ( typeof types === "object" ) { - // ( types-Object, selector, data ) - if ( typeof selector !== "string" ) { - // ( types-Object, data ) - data = data || selector; - selector = undefined; - } - for ( type in types ) { - this.on( type, selector, data, types[ type ], one ); - } - return this; - } - - if ( data == null && fn == null ) { - // ( types, fn ) - fn = selector; - data = selector = undefined; - } else if ( fn == null ) { - if ( typeof selector === "string" ) { - // ( types, selector, fn ) - fn = data; - data = undefined; - } else { - // ( types, data, fn ) - fn = data; - data = selector; - selector = undefined; - } - } - if ( fn === false ) { - fn = returnFalse; - } else if ( !fn ) { - return this; - } - - if ( one === 1 ) { - origFn = fn; - fn = function( event ) { - // Can use an empty set, since event contains the info - jQuery().off( event ); - return origFn.apply( this, arguments ); - }; - // Use same guid so caller can remove using origFn - fn.guid = origFn.guid || ( origFn.guid = jQuery.guid++ ); - } - return this.each( function() { - jQuery.event.add( this, types, fn, data, selector ); - }); - }, - one: function( types, selector, data, fn ) { - return this.on( types, selector, data, fn, 1 ); - }, - off: function( types, selector, fn ) { - var handleObj, type; - if ( types && types.preventDefault && types.handleObj ) { - // ( event ) dispatched jQuery.Event - handleObj = types.handleObj; - jQuery( types.delegateTarget ).off( - handleObj.namespace ? handleObj.origType + "." + handleObj.namespace : handleObj.origType, - handleObj.selector, - handleObj.handler - ); - return this; - } - if ( typeof types === "object" ) { - // ( types-object [, selector] ) - for ( type in types ) { - this.off( type, selector, types[ type ] ); - } - return this; - } - if ( selector === false || typeof selector === "function" ) { - // ( types [, fn] ) - fn = selector; - selector = undefined; - } - if ( fn === false ) { - fn = returnFalse; - } - return this.each(function() { - jQuery.event.remove( this, types, fn, selector ); - }); - }, - - trigger: function( type, data ) { - return this.each(function() { - jQuery.event.trigger( type, data, this ); - }); - }, - triggerHandler: function( type, data ) { - var elem = this[0]; - if ( elem ) { - return jQuery.event.trigger( type, data, elem, true ); - } - } -}); -var isSimple = /^.[^:#\[\.,]*$/, - rparentsprev = /^(?:parents|prev(?:Until|All))/, - rneedsContext = jQuery.expr.match.needsContext, - // methods guaranteed to produce a unique set when starting from a unique set - guaranteedUnique = { - children: true, - contents: true, - next: true, - prev: true - }; - -jQuery.fn.extend({ - find: function( selector ) { - var i, - ret = [], - self = this, - len = self.length; - - if ( typeof selector !== "string" ) { - return this.pushStack( jQuery( selector ).filter(function() { - for ( i = 0; i < len; i++ ) { - if ( jQuery.contains( self[ i ], this ) ) { - return true; - } - } - }) ); - } - - for ( i = 0; i < len; i++ ) { - jQuery.find( selector, self[ i ], ret ); - } - - // Needed because $( selector, context ) becomes $( context ).find( selector ) - ret = this.pushStack( len > 1 ? jQuery.unique( ret ) : ret ); - ret.selector = this.selector ? this.selector + " " + selector : selector; - return ret; - }, - - has: function( target ) { - var i, - targets = jQuery( target, this ), - len = targets.length; - - return this.filter(function() { - for ( i = 0; i < len; i++ ) { - if ( jQuery.contains( this, targets[i] ) ) { - return true; - } - } - }); - }, - - not: function( selector ) { - return this.pushStack( winnow(this, selector || [], true) ); - }, - - filter: function( selector ) { - return this.pushStack( winnow(this, selector || [], false) ); - }, - - is: function( selector ) { - return !!winnow( - this, - - // If this is a positional/relative selector, check membership in the returned set - // so $("p:first").is("p:last") won't return true for a doc with two "p". - typeof selector === "string" && rneedsContext.test( selector ) ? - jQuery( selector ) : - selector || [], - false - ).length; - }, - - closest: function( selectors, context ) { - var cur, - i = 0, - l = this.length, - ret = [], - pos = rneedsContext.test( selectors ) || typeof selectors !== "string" ? - jQuery( selectors, context || this.context ) : - 0; - - for ( ; i < l; i++ ) { - for ( cur = this[i]; cur && cur !== context; cur = cur.parentNode ) { - // Always skip document fragments - if ( cur.nodeType < 11 && (pos ? - pos.index(cur) > -1 : - - // Don't pass non-elements to Sizzle - cur.nodeType === 1 && - jQuery.find.matchesSelector(cur, selectors)) ) { - - cur = ret.push( cur ); - break; - } - } - } - - return this.pushStack( ret.length > 1 ? jQuery.unique( ret ) : ret ); - }, - - // Determine the position of an element within - // the matched set of elements - index: function( elem ) { - - // No argument, return index in parent - if ( !elem ) { - return ( this[0] && this[0].parentNode ) ? this.first().prevAll().length : -1; - } - - // index in selector - if ( typeof elem === "string" ) { - return jQuery.inArray( this[0], jQuery( elem ) ); - } - - // Locate the position of the desired element - return jQuery.inArray( - // If it receives a jQuery object, the first element is used - elem.jquery ? elem[0] : elem, this ); - }, - - add: function( selector, context ) { - var set = typeof selector === "string" ? - jQuery( selector, context ) : - jQuery.makeArray( selector && selector.nodeType ? [ selector ] : selector ), - all = jQuery.merge( this.get(), set ); - - return this.pushStack( jQuery.unique(all) ); - }, - - addBack: function( selector ) { - return this.add( selector == null ? - this.prevObject : this.prevObject.filter(selector) - ); - } -}); - -function sibling( cur, dir ) { - do { - cur = cur[ dir ]; - } while ( cur && cur.nodeType !== 1 ); - - return cur; -} - -jQuery.each({ - parent: function( elem ) { - var parent = elem.parentNode; - return parent && parent.nodeType !== 11 ? parent : null; - }, - parents: function( elem ) { - return jQuery.dir( elem, "parentNode" ); - }, - parentsUntil: function( elem, i, until ) { - return jQuery.dir( elem, "parentNode", until ); - }, - next: function( elem ) { - return sibling( elem, "nextSibling" ); - }, - prev: function( elem ) { - return sibling( elem, "previousSibling" ); - }, - nextAll: function( elem ) { - return jQuery.dir( elem, "nextSibling" ); - }, - prevAll: function( elem ) { - return jQuery.dir( elem, "previousSibling" ); - }, - nextUntil: function( elem, i, until ) { - return jQuery.dir( elem, "nextSibling", until ); - }, - prevUntil: function( elem, i, until ) { - return jQuery.dir( elem, "previousSibling", until ); - }, - siblings: function( elem ) { - return jQuery.sibling( ( elem.parentNode || {} ).firstChild, elem ); - }, - children: function( elem ) { - return jQuery.sibling( elem.firstChild ); - }, - contents: function( elem ) { - return jQuery.nodeName( elem, "iframe" ) ? - elem.contentDocument || elem.contentWindow.document : - jQuery.merge( [], elem.childNodes ); - } -}, function( name, fn ) { - jQuery.fn[ name ] = function( until, selector ) { - var ret = jQuery.map( this, fn, until ); - - if ( name.slice( -5 ) !== "Until" ) { - selector = until; - } - - if ( selector && typeof selector === "string" ) { - ret = jQuery.filter( selector, ret ); - } - - if ( this.length > 1 ) { - // Remove duplicates - if ( !guaranteedUnique[ name ] ) { - ret = jQuery.unique( ret ); - } - - // Reverse order for parents* and prev-derivatives - if ( rparentsprev.test( name ) ) { - ret = ret.reverse(); - } - } - - return this.pushStack( ret ); - }; -}); - -jQuery.extend({ - filter: function( expr, elems, not ) { - var elem = elems[ 0 ]; - - if ( not ) { - expr = ":not(" + expr + ")"; - } - - return elems.length === 1 && elem.nodeType === 1 ? - jQuery.find.matchesSelector( elem, expr ) ? [ elem ] : [] : - jQuery.find.matches( expr, jQuery.grep( elems, function( elem ) { - return elem.nodeType === 1; - })); - }, - - dir: function( elem, dir, until ) { - var matched = [], - cur = elem[ dir ]; - - while ( cur && cur.nodeType !== 9 && (until === undefined || cur.nodeType !== 1 || !jQuery( cur ).is( until )) ) { - if ( cur.nodeType === 1 ) { - matched.push( cur ); - } - cur = cur[dir]; - } - return matched; - }, - - sibling: function( n, elem ) { - var r = []; - - for ( ; n; n = n.nextSibling ) { - if ( n.nodeType === 1 && n !== elem ) { - r.push( n ); - } - } - - return r; - } -}); - -// Implement the identical functionality for filter and not -function winnow( elements, qualifier, not ) { - if ( jQuery.isFunction( qualifier ) ) { - return jQuery.grep( elements, function( elem, i ) { - /* jshint -W018 */ - return !!qualifier.call( elem, i, elem ) !== not; - }); - - } - - if ( qualifier.nodeType ) { - return jQuery.grep( elements, function( elem ) { - return ( elem === qualifier ) !== not; - }); - - } - - if ( typeof qualifier === "string" ) { - if ( isSimple.test( qualifier ) ) { - return jQuery.filter( qualifier, elements, not ); - } - - qualifier = jQuery.filter( qualifier, elements ); - } - - return jQuery.grep( elements, function( elem ) { - return ( jQuery.inArray( elem, qualifier ) >= 0 ) !== not; - }); -} -function createSafeFragment( document ) { - var list = nodeNames.split( "|" ), - safeFrag = document.createDocumentFragment(); - - if ( safeFrag.createElement ) { - while ( list.length ) { - safeFrag.createElement( - list.pop() - ); - } - } - return safeFrag; -} - -var nodeNames = "abbr|article|aside|audio|bdi|canvas|data|datalist|details|figcaption|figure|footer|" + - "header|hgroup|mark|meter|nav|output|progress|section|summary|time|video", - rinlinejQuery = / jQuery\d+="(?:null|\d+)"/g, - rnoshimcache = new RegExp("<(?:" + nodeNames + ")[\\s/>]", "i"), - rleadingWhitespace = /^\s+/, - rxhtmlTag = /<(?!area|br|col|embed|hr|img|input|link|meta|param)(([\w:]+)[^>]*)\/>/gi, - rtagName = /<([\w:]+)/, - rtbody = /\s*$/g, - - // We have to close these tags to support XHTML (#13200) - wrapMap = { - option: [ 1, "" ], - legend: [ 1, "
", "
" ], - area: [ 1, "", "" ], - param: [ 1, "", "" ], - thead: [ 1, "", "
" ], - tr: [ 2, "", "
" ], - col: [ 2, "", "
" ], - td: [ 3, "", "
" ], - - // IE6-8 can't serialize link, script, style, or any html5 (NoScope) tags, - // unless wrapped in a div with non-breaking characters in front of it. - _default: jQuery.support.htmlSerialize ? [ 0, "", "" ] : [ 1, "X
", "
" ] - }, - safeFragment = createSafeFragment( document ), - fragmentDiv = safeFragment.appendChild( document.createElement("div") ); - -wrapMap.optgroup = wrapMap.option; -wrapMap.tbody = wrapMap.tfoot = wrapMap.colgroup = wrapMap.caption = wrapMap.thead; -wrapMap.th = wrapMap.td; - -jQuery.fn.extend({ - text: function( value ) { - return jQuery.access( this, function( value ) { - return value === undefined ? - jQuery.text( this ) : - this.empty().append( ( this[0] && this[0].ownerDocument || document ).createTextNode( value ) ); - }, null, value, arguments.length ); - }, - - append: function() { - return this.domManip( arguments, function( elem ) { - if ( this.nodeType === 1 || this.nodeType === 11 || this.nodeType === 9 ) { - var target = manipulationTarget( this, elem ); - target.appendChild( elem ); - } - }); - }, - - prepend: function() { - return this.domManip( arguments, function( elem ) { - if ( this.nodeType === 1 || this.nodeType === 11 || this.nodeType === 9 ) { - var target = manipulationTarget( this, elem ); - target.insertBefore( elem, target.firstChild ); - } - }); - }, - - before: function() { - return this.domManip( arguments, function( elem ) { - if ( this.parentNode ) { - this.parentNode.insertBefore( elem, this ); - } - }); - }, - - after: function() { - return this.domManip( arguments, function( elem ) { - if ( this.parentNode ) { - this.parentNode.insertBefore( elem, this.nextSibling ); - } - }); - }, - - // keepData is for internal use only--do not document - remove: function( selector, keepData ) { - var elem, - elems = selector ? jQuery.filter( selector, this ) : this, - i = 0; - - for ( ; (elem = elems[i]) != null; i++ ) { - - if ( !keepData && elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem ) ); - } - - if ( elem.parentNode ) { - if ( keepData && jQuery.contains( elem.ownerDocument, elem ) ) { - setGlobalEval( getAll( elem, "script" ) ); - } - elem.parentNode.removeChild( elem ); - } - } - - return this; - }, - - empty: function() { - var elem, - i = 0; - - for ( ; (elem = this[i]) != null; i++ ) { - // Remove element nodes and prevent memory leaks - if ( elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem, false ) ); - } - - // Remove any remaining nodes - while ( elem.firstChild ) { - elem.removeChild( elem.firstChild ); - } - - // If this is a select, ensure that it displays empty (#12336) - // Support: IE<9 - if ( elem.options && jQuery.nodeName( elem, "select" ) ) { - elem.options.length = 0; - } - } - - return this; - }, - - clone: function( dataAndEvents, deepDataAndEvents ) { - dataAndEvents = dataAndEvents == null ? false : dataAndEvents; - deepDataAndEvents = deepDataAndEvents == null ? dataAndEvents : deepDataAndEvents; - - return this.map( function () { - return jQuery.clone( this, dataAndEvents, deepDataAndEvents ); - }); - }, - - html: function( value ) { - return jQuery.access( this, function( value ) { - var elem = this[0] || {}, - i = 0, - l = this.length; - - if ( value === undefined ) { - return elem.nodeType === 1 ? - elem.innerHTML.replace( rinlinejQuery, "" ) : - undefined; - } - - // See if we can take a shortcut and just use innerHTML - if ( typeof value === "string" && !rnoInnerhtml.test( value ) && - ( jQuery.support.htmlSerialize || !rnoshimcache.test( value ) ) && - ( jQuery.support.leadingWhitespace || !rleadingWhitespace.test( value ) ) && - !wrapMap[ ( rtagName.exec( value ) || ["", ""] )[1].toLowerCase() ] ) { - - value = value.replace( rxhtmlTag, "<$1>" ); - - try { - for (; i < l; i++ ) { - // Remove element nodes and prevent memory leaks - elem = this[i] || {}; - if ( elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem, false ) ); - elem.innerHTML = value; - } - } - - elem = 0; - - // If using innerHTML throws an exception, use the fallback method - } catch(e) {} - } - - if ( elem ) { - this.empty().append( value ); - } - }, null, value, arguments.length ); - }, - - replaceWith: function() { - var - // Snapshot the DOM in case .domManip sweeps something relevant into its fragment - args = jQuery.map( this, function( elem ) { - return [ elem.nextSibling, elem.parentNode ]; - }), - i = 0; - - // Make the changes, replacing each context element with the new content - this.domManip( arguments, function( elem ) { - var next = args[ i++ ], - parent = args[ i++ ]; - - if ( parent ) { - // Don't use the snapshot next if it has moved (#13810) - if ( next && next.parentNode !== parent ) { - next = this.nextSibling; - } - jQuery( this ).remove(); - parent.insertBefore( elem, next ); - } - // Allow new content to include elements from the context set - }, true ); - - // Force removal if there was no new content (e.g., from empty arguments) - return i ? this : this.remove(); - }, - - detach: function( selector ) { - return this.remove( selector, true ); - }, - - domManip: function( args, callback, allowIntersection ) { - - // Flatten any nested arrays - args = core_concat.apply( [], args ); - - var first, node, hasScripts, - scripts, doc, fragment, - i = 0, - l = this.length, - set = this, - iNoClone = l - 1, - value = args[0], - isFunction = jQuery.isFunction( value ); - - // We can't cloneNode fragments that contain checked, in WebKit - if ( isFunction || !( l <= 1 || typeof value !== "string" || jQuery.support.checkClone || !rchecked.test( value ) ) ) { - return this.each(function( index ) { - var self = set.eq( index ); - if ( isFunction ) { - args[0] = value.call( this, index, self.html() ); - } - self.domManip( args, callback, allowIntersection ); - }); - } - - if ( l ) { - fragment = jQuery.buildFragment( args, this[ 0 ].ownerDocument, false, !allowIntersection && this ); - first = fragment.firstChild; - - if ( fragment.childNodes.length === 1 ) { - fragment = first; - } - - if ( first ) { - scripts = jQuery.map( getAll( fragment, "script" ), disableScript ); - hasScripts = scripts.length; - - // Use the original fragment for the last item instead of the first because it can end up - // being emptied incorrectly in certain situations (#8070). - for ( ; i < l; i++ ) { - node = fragment; - - if ( i !== iNoClone ) { - node = jQuery.clone( node, true, true ); - - // Keep references to cloned scripts for later restoration - if ( hasScripts ) { - jQuery.merge( scripts, getAll( node, "script" ) ); - } - } - - callback.call( this[i], node, i ); - } - - if ( hasScripts ) { - doc = scripts[ scripts.length - 1 ].ownerDocument; - - // Reenable scripts - jQuery.map( scripts, restoreScript ); - - // Evaluate executable scripts on first document insertion - for ( i = 0; i < hasScripts; i++ ) { - node = scripts[ i ]; - if ( rscriptType.test( node.type || "" ) && - !jQuery._data( node, "globalEval" ) && jQuery.contains( doc, node ) ) { - - if ( node.src ) { - // Hope ajax is available... - jQuery._evalUrl( node.src ); - } else { - jQuery.globalEval( ( node.text || node.textContent || node.innerHTML || "" ).replace( rcleanScript, "" ) ); - } - } - } - } - - // Fix #11809: Avoid leaking memory - fragment = first = null; - } - } - - return this; - } -}); - -// Support: IE<8 -// Manipulating tables requires a tbody -function manipulationTarget( elem, content ) { - return jQuery.nodeName( elem, "table" ) && - jQuery.nodeName( content.nodeType === 1 ? content : content.firstChild, "tr" ) ? - - elem.getElementsByTagName("tbody")[0] || - elem.appendChild( elem.ownerDocument.createElement("tbody") ) : - elem; -} - -// Replace/restore the type attribute of script elements for safe DOM manipulation -function disableScript( elem ) { - elem.type = (jQuery.find.attr( elem, "type" ) !== null) + "/" + elem.type; - return elem; -} -function restoreScript( elem ) { - var match = rscriptTypeMasked.exec( elem.type ); - if ( match ) { - elem.type = match[1]; - } else { - elem.removeAttribute("type"); - } - return elem; -} - -// Mark scripts as having already been evaluated -function setGlobalEval( elems, refElements ) { - var elem, - i = 0; - for ( ; (elem = elems[i]) != null; i++ ) { - jQuery._data( elem, "globalEval", !refElements || jQuery._data( refElements[i], "globalEval" ) ); - } -} - -function cloneCopyEvent( src, dest ) { - - if ( dest.nodeType !== 1 || !jQuery.hasData( src ) ) { - return; - } - - var type, i, l, - oldData = jQuery._data( src ), - curData = jQuery._data( dest, oldData ), - events = oldData.events; - - if ( events ) { - delete curData.handle; - curData.events = {}; - - for ( type in events ) { - for ( i = 0, l = events[ type ].length; i < l; i++ ) { - jQuery.event.add( dest, type, events[ type ][ i ] ); - } - } - } - - // make the cloned public data object a copy from the original - if ( curData.data ) { - curData.data = jQuery.extend( {}, curData.data ); - } -} - -function fixCloneNodeIssues( src, dest ) { - var nodeName, e, data; - - // We do not need to do anything for non-Elements - if ( dest.nodeType !== 1 ) { - return; - } - - nodeName = dest.nodeName.toLowerCase(); - - // IE6-8 copies events bound via attachEvent when using cloneNode. - if ( !jQuery.support.noCloneEvent && dest[ jQuery.expando ] ) { - data = jQuery._data( dest ); - - for ( e in data.events ) { - jQuery.removeEvent( dest, e, data.handle ); - } - - // Event data gets referenced instead of copied if the expando gets copied too - dest.removeAttribute( jQuery.expando ); - } - - // IE blanks contents when cloning scripts, and tries to evaluate newly-set text - if ( nodeName === "script" && dest.text !== src.text ) { - disableScript( dest ).text = src.text; - restoreScript( dest ); - - // IE6-10 improperly clones children of object elements using classid. - // IE10 throws NoModificationAllowedError if parent is null, #12132. - } else if ( nodeName === "object" ) { - if ( dest.parentNode ) { - dest.outerHTML = src.outerHTML; - } - - // This path appears unavoidable for IE9. When cloning an object - // element in IE9, the outerHTML strategy above is not sufficient. - // If the src has innerHTML and the destination does not, - // copy the src.innerHTML into the dest.innerHTML. #10324 - if ( jQuery.support.html5Clone && ( src.innerHTML && !jQuery.trim(dest.innerHTML) ) ) { - dest.innerHTML = src.innerHTML; - } - - } else if ( nodeName === "input" && manipulation_rcheckableType.test( src.type ) ) { - // IE6-8 fails to persist the checked state of a cloned checkbox - // or radio button. Worse, IE6-7 fail to give the cloned element - // a checked appearance if the defaultChecked value isn't also set - - dest.defaultChecked = dest.checked = src.checked; - - // IE6-7 get confused and end up setting the value of a cloned - // checkbox/radio button to an empty string instead of "on" - if ( dest.value !== src.value ) { - dest.value = src.value; - } - - // IE6-8 fails to return the selected option to the default selected - // state when cloning options - } else if ( nodeName === "option" ) { - dest.defaultSelected = dest.selected = src.defaultSelected; - - // IE6-8 fails to set the defaultValue to the correct value when - // cloning other types of input fields - } else if ( nodeName === "input" || nodeName === "textarea" ) { - dest.defaultValue = src.defaultValue; - } -} - -jQuery.each({ - appendTo: "append", - prependTo: "prepend", - insertBefore: "before", - insertAfter: "after", - replaceAll: "replaceWith" -}, function( name, original ) { - jQuery.fn[ name ] = function( selector ) { - var elems, - i = 0, - ret = [], - insert = jQuery( selector ), - last = insert.length - 1; - - for ( ; i <= last; i++ ) { - elems = i === last ? this : this.clone(true); - jQuery( insert[i] )[ original ]( elems ); - - // Modern browsers can apply jQuery collections as arrays, but oldIE needs a .get() - core_push.apply( ret, elems.get() ); - } - - return this.pushStack( ret ); - }; -}); - -function getAll( context, tag ) { - var elems, elem, - i = 0, - found = typeof context.getElementsByTagName !== core_strundefined ? context.getElementsByTagName( tag || "*" ) : - typeof context.querySelectorAll !== core_strundefined ? context.querySelectorAll( tag || "*" ) : - undefined; - - if ( !found ) { - for ( found = [], elems = context.childNodes || context; (elem = elems[i]) != null; i++ ) { - if ( !tag || jQuery.nodeName( elem, tag ) ) { - found.push( elem ); - } else { - jQuery.merge( found, getAll( elem, tag ) ); - } - } - } - - return tag === undefined || tag && jQuery.nodeName( context, tag ) ? - jQuery.merge( [ context ], found ) : - found; -} - -// Used in buildFragment, fixes the defaultChecked property -function fixDefaultChecked( elem ) { - if ( manipulation_rcheckableType.test( elem.type ) ) { - elem.defaultChecked = elem.checked; - } -} - -jQuery.extend({ - clone: function( elem, dataAndEvents, deepDataAndEvents ) { - var destElements, node, clone, i, srcElements, - inPage = jQuery.contains( elem.ownerDocument, elem ); - - if ( jQuery.support.html5Clone || jQuery.isXMLDoc(elem) || !rnoshimcache.test( "<" + elem.nodeName + ">" ) ) { - clone = elem.cloneNode( true ); - - // IE<=8 does not properly clone detached, unknown element nodes - } else { - fragmentDiv.innerHTML = elem.outerHTML; - fragmentDiv.removeChild( clone = fragmentDiv.firstChild ); - } - - if ( (!jQuery.support.noCloneEvent || !jQuery.support.noCloneChecked) && - (elem.nodeType === 1 || elem.nodeType === 11) && !jQuery.isXMLDoc(elem) ) { - - // We eschew Sizzle here for performance reasons: http://jsperf.com/getall-vs-sizzle/2 - destElements = getAll( clone ); - srcElements = getAll( elem ); - - // Fix all IE cloning issues - for ( i = 0; (node = srcElements[i]) != null; ++i ) { - // Ensure that the destination node is not null; Fixes #9587 - if ( destElements[i] ) { - fixCloneNodeIssues( node, destElements[i] ); - } - } - } - - // Copy the events from the original to the clone - if ( dataAndEvents ) { - if ( deepDataAndEvents ) { - srcElements = srcElements || getAll( elem ); - destElements = destElements || getAll( clone ); - - for ( i = 0; (node = srcElements[i]) != null; i++ ) { - cloneCopyEvent( node, destElements[i] ); - } - } else { - cloneCopyEvent( elem, clone ); - } - } - - // Preserve script evaluation history - destElements = getAll( clone, "script" ); - if ( destElements.length > 0 ) { - setGlobalEval( destElements, !inPage && getAll( elem, "script" ) ); - } - - destElements = srcElements = node = null; - - // Return the cloned set - return clone; - }, - - buildFragment: function( elems, context, scripts, selection ) { - var j, elem, contains, - tmp, tag, tbody, wrap, - l = elems.length, - - // Ensure a safe fragment - safe = createSafeFragment( context ), - - nodes = [], - i = 0; - - for ( ; i < l; i++ ) { - elem = elems[ i ]; - - if ( elem || elem === 0 ) { - - // Add nodes directly - if ( jQuery.type( elem ) === "object" ) { - jQuery.merge( nodes, elem.nodeType ? [ elem ] : elem ); - - // Convert non-html into a text node - } else if ( !rhtml.test( elem ) ) { - nodes.push( context.createTextNode( elem ) ); - - // Convert html into DOM nodes - } else { - tmp = tmp || safe.appendChild( context.createElement("div") ); - - // Deserialize a standard representation - tag = ( rtagName.exec( elem ) || ["", ""] )[1].toLowerCase(); - wrap = wrapMap[ tag ] || wrapMap._default; - - tmp.innerHTML = wrap[1] + elem.replace( rxhtmlTag, "<$1>" ) + wrap[2]; - - // Descend through wrappers to the right content - j = wrap[0]; - while ( j-- ) { - tmp = tmp.lastChild; - } - - // Manually add leading whitespace removed by IE - if ( !jQuery.support.leadingWhitespace && rleadingWhitespace.test( elem ) ) { - nodes.push( context.createTextNode( rleadingWhitespace.exec( elem )[0] ) ); - } - - // Remove IE's autoinserted from table fragments - if ( !jQuery.support.tbody ) { - - // String was a , *may* have spurious - elem = tag === "table" && !rtbody.test( elem ) ? - tmp.firstChild : - - // String was a bare or - wrap[1] === "
" && !rtbody.test( elem ) ? - tmp : - 0; - - j = elem && elem.childNodes.length; - while ( j-- ) { - if ( jQuery.nodeName( (tbody = elem.childNodes[j]), "tbody" ) && !tbody.childNodes.length ) { - elem.removeChild( tbody ); - } - } - } - - jQuery.merge( nodes, tmp.childNodes ); - - // Fix #12392 for WebKit and IE > 9 - tmp.textContent = ""; - - // Fix #12392 for oldIE - while ( tmp.firstChild ) { - tmp.removeChild( tmp.firstChild ); - } - - // Remember the top-level container for proper cleanup - tmp = safe.lastChild; - } - } - } - - // Fix #11356: Clear elements from fragment - if ( tmp ) { - safe.removeChild( tmp ); - } - - // Reset defaultChecked for any radios and checkboxes - // about to be appended to the DOM in IE 6/7 (#8060) - if ( !jQuery.support.appendChecked ) { - jQuery.grep( getAll( nodes, "input" ), fixDefaultChecked ); - } - - i = 0; - while ( (elem = nodes[ i++ ]) ) { - - // #4087 - If origin and destination elements are the same, and this is - // that element, do not do anything - if ( selection && jQuery.inArray( elem, selection ) !== -1 ) { - continue; - } - - contains = jQuery.contains( elem.ownerDocument, elem ); - - // Append to fragment - tmp = getAll( safe.appendChild( elem ), "script" ); - - // Preserve script evaluation history - if ( contains ) { - setGlobalEval( tmp ); - } - - // Capture executables - if ( scripts ) { - j = 0; - while ( (elem = tmp[ j++ ]) ) { - if ( rscriptType.test( elem.type || "" ) ) { - scripts.push( elem ); - } - } - } - } - - tmp = null; - - return safe; - }, - - cleanData: function( elems, /* internal */ acceptData ) { - var elem, type, id, data, - i = 0, - internalKey = jQuery.expando, - cache = jQuery.cache, - deleteExpando = jQuery.support.deleteExpando, - special = jQuery.event.special; - - for ( ; (elem = elems[i]) != null; i++ ) { - - if ( acceptData || jQuery.acceptData( elem ) ) { - - id = elem[ internalKey ]; - data = id && cache[ id ]; - - if ( data ) { - if ( data.events ) { - for ( type in data.events ) { - if ( special[ type ] ) { - jQuery.event.remove( elem, type ); - - // This is a shortcut to avoid jQuery.event.remove's overhead - } else { - jQuery.removeEvent( elem, type, data.handle ); - } - } - } - - // Remove cache only if it was not already removed by jQuery.event.remove - if ( cache[ id ] ) { - - delete cache[ id ]; - - // IE does not allow us to delete expando properties from nodes, - // nor does it have a removeAttribute function on Document nodes; - // we must handle all of these cases - if ( deleteExpando ) { - delete elem[ internalKey ]; - - } else if ( typeof elem.removeAttribute !== core_strundefined ) { - elem.removeAttribute( internalKey ); - - } else { - elem[ internalKey ] = null; - } - - core_deletedIds.push( id ); - } - } - } - } - }, - - _evalUrl: function( url ) { - return jQuery.ajax({ - url: url, - type: "GET", - dataType: "script", - async: false, - global: false, - "throws": true - }); - } -}); -jQuery.fn.extend({ - wrapAll: function( html ) { - if ( jQuery.isFunction( html ) ) { - return this.each(function(i) { - jQuery(this).wrapAll( html.call(this, i) ); - }); - } - - if ( this[0] ) { - // The elements to wrap the target around - var wrap = jQuery( html, this[0].ownerDocument ).eq(0).clone(true); - - if ( this[0].parentNode ) { - wrap.insertBefore( this[0] ); - } - - wrap.map(function() { - var elem = this; - - while ( elem.firstChild && elem.firstChild.nodeType === 1 ) { - elem = elem.firstChild; - } - - return elem; - }).append( this ); - } - - return this; - }, - - wrapInner: function( html ) { - if ( jQuery.isFunction( html ) ) { - return this.each(function(i) { - jQuery(this).wrapInner( html.call(this, i) ); - }); - } - - return this.each(function() { - var self = jQuery( this ), - contents = self.contents(); - - if ( contents.length ) { - contents.wrapAll( html ); - - } else { - self.append( html ); - } - }); - }, - - wrap: function( html ) { - var isFunction = jQuery.isFunction( html ); - - return this.each(function(i) { - jQuery( this ).wrapAll( isFunction ? html.call(this, i) : html ); - }); - }, - - unwrap: function() { - return this.parent().each(function() { - if ( !jQuery.nodeName( this, "body" ) ) { - jQuery( this ).replaceWith( this.childNodes ); - } - }).end(); - } -}); -var iframe, getStyles, curCSS, - ralpha = /alpha\([^)]*\)/i, - ropacity = /opacity\s*=\s*([^)]*)/, - rposition = /^(top|right|bottom|left)$/, - // swappable if display is none or starts with table except "table", "table-cell", or "table-caption" - // see here for display values: https://developer.mozilla.org/en-US/docs/CSS/display - rdisplayswap = /^(none|table(?!-c[ea]).+)/, - rmargin = /^margin/, - rnumsplit = new RegExp( "^(" + core_pnum + ")(.*)$", "i" ), - rnumnonpx = new RegExp( "^(" + core_pnum + ")(?!px)[a-z%]+$", "i" ), - rrelNum = new RegExp( "^([+-])=(" + core_pnum + ")", "i" ), - elemdisplay = { BODY: "block" }, - - cssShow = { position: "absolute", visibility: "hidden", display: "block" }, - cssNormalTransform = { - letterSpacing: 0, - fontWeight: 400 - }, - - cssExpand = [ "Top", "Right", "Bottom", "Left" ], - cssPrefixes = [ "Webkit", "O", "Moz", "ms" ]; - -// return a css property mapped to a potentially vendor prefixed property -function vendorPropName( style, name ) { - - // shortcut for names that are not vendor prefixed - if ( name in style ) { - return name; - } - - // check for vendor prefixed names - var capName = name.charAt(0).toUpperCase() + name.slice(1), - origName = name, - i = cssPrefixes.length; - - while ( i-- ) { - name = cssPrefixes[ i ] + capName; - if ( name in style ) { - return name; - } - } - - return origName; -} - -function isHidden( elem, el ) { - // isHidden might be called from jQuery#filter function; - // in that case, element will be second argument - elem = el || elem; - return jQuery.css( elem, "display" ) === "none" || !jQuery.contains( elem.ownerDocument, elem ); -} - -function showHide( elements, show ) { - var display, elem, hidden, - values = [], - index = 0, - length = elements.length; - - for ( ; index < length; index++ ) { - elem = elements[ index ]; - if ( !elem.style ) { - continue; - } - - values[ index ] = jQuery._data( elem, "olddisplay" ); - display = elem.style.display; - if ( show ) { - // Reset the inline display of this element to learn if it is - // being hidden by cascaded rules or not - if ( !values[ index ] && display === "none" ) { - elem.style.display = ""; - } - - // Set elements which have been overridden with display: none - // in a stylesheet to whatever the default browser style is - // for such an element - if ( elem.style.display === "" && isHidden( elem ) ) { - values[ index ] = jQuery._data( elem, "olddisplay", css_defaultDisplay(elem.nodeName) ); - } - } else { - - if ( !values[ index ] ) { - hidden = isHidden( elem ); - - if ( display && display !== "none" || !hidden ) { - jQuery._data( elem, "olddisplay", hidden ? display : jQuery.css( elem, "display" ) ); - } - } - } - } - - // Set the display of most of the elements in a second loop - // to avoid the constant reflow - for ( index = 0; index < length; index++ ) { - elem = elements[ index ]; - if ( !elem.style ) { - continue; - } - if ( !show || elem.style.display === "none" || elem.style.display === "" ) { - elem.style.display = show ? values[ index ] || "" : "none"; - } - } - - return elements; -} - -jQuery.fn.extend({ - css: function( name, value ) { - return jQuery.access( this, function( elem, name, value ) { - var len, styles, - map = {}, - i = 0; - - if ( jQuery.isArray( name ) ) { - styles = getStyles( elem ); - len = name.length; - - for ( ; i < len; i++ ) { - map[ name[ i ] ] = jQuery.css( elem, name[ i ], false, styles ); - } - - return map; - } - - return value !== undefined ? - jQuery.style( elem, name, value ) : - jQuery.css( elem, name ); - }, name, value, arguments.length > 1 ); - }, - show: function() { - return showHide( this, true ); - }, - hide: function() { - return showHide( this ); - }, - toggle: function( state ) { - if ( typeof state === "boolean" ) { - return state ? this.show() : this.hide(); - } - - return this.each(function() { - if ( isHidden( this ) ) { - jQuery( this ).show(); - } else { - jQuery( this ).hide(); - } - }); - } -}); - -jQuery.extend({ - // Add in style property hooks for overriding the default - // behavior of getting and setting a style property - cssHooks: { - opacity: { - get: function( elem, computed ) { - if ( computed ) { - // We should always get a number back from opacity - var ret = curCSS( elem, "opacity" ); - return ret === "" ? "1" : ret; - } - } - } - }, - - // Don't automatically add "px" to these possibly-unitless properties - cssNumber: { - "columnCount": true, - "fillOpacity": true, - "fontWeight": true, - "lineHeight": true, - "opacity": true, - "order": true, - "orphans": true, - "widows": true, - "zIndex": true, - "zoom": true - }, - - // Add in properties whose names you wish to fix before - // setting or getting the value - cssProps: { - // normalize float css property - "float": jQuery.support.cssFloat ? "cssFloat" : "styleFloat" - }, - - // Get and set the style property on a DOM Node - style: function( elem, name, value, extra ) { - // Don't set styles on text and comment nodes - if ( !elem || elem.nodeType === 3 || elem.nodeType === 8 || !elem.style ) { - return; - } - - // Make sure that we're working with the right name - var ret, type, hooks, - origName = jQuery.camelCase( name ), - style = elem.style; - - name = jQuery.cssProps[ origName ] || ( jQuery.cssProps[ origName ] = vendorPropName( style, origName ) ); - - // gets hook for the prefixed version - // followed by the unprefixed version - hooks = jQuery.cssHooks[ name ] || jQuery.cssHooks[ origName ]; - - // Check if we're setting a value - if ( value !== undefined ) { - type = typeof value; - - // convert relative number strings (+= or -=) to relative numbers. #7345 - if ( type === "string" && (ret = rrelNum.exec( value )) ) { - value = ( ret[1] + 1 ) * ret[2] + parseFloat( jQuery.css( elem, name ) ); - // Fixes bug #9237 - type = "number"; - } - - // Make sure that NaN and null values aren't set. See: #7116 - if ( value == null || type === "number" && isNaN( value ) ) { - return; - } - - // If a number was passed in, add 'px' to the (except for certain CSS properties) - if ( type === "number" && !jQuery.cssNumber[ origName ] ) { - value += "px"; - } - - // Fixes #8908, it can be done more correctly by specifing setters in cssHooks, - // but it would mean to define eight (for every problematic property) identical functions - if ( !jQuery.support.clearCloneStyle && value === "" && name.indexOf("background") === 0 ) { - style[ name ] = "inherit"; - } - - // If a hook was provided, use that value, otherwise just set the specified value - if ( !hooks || !("set" in hooks) || (value = hooks.set( elem, value, extra )) !== undefined ) { - - // Wrapped to prevent IE from throwing errors when 'invalid' values are provided - // Fixes bug #5509 - try { - style[ name ] = value; - } catch(e) {} - } - - } else { - // If a hook was provided get the non-computed value from there - if ( hooks && "get" in hooks && (ret = hooks.get( elem, false, extra )) !== undefined ) { - return ret; - } - - // Otherwise just get the value from the style object - return style[ name ]; - } - }, - - css: function( elem, name, extra, styles ) { - var num, val, hooks, - origName = jQuery.camelCase( name ); - - // Make sure that we're working with the right name - name = jQuery.cssProps[ origName ] || ( jQuery.cssProps[ origName ] = vendorPropName( elem.style, origName ) ); - - // gets hook for the prefixed version - // followed by the unprefixed version - hooks = jQuery.cssHooks[ name ] || jQuery.cssHooks[ origName ]; - - // If a hook was provided get the computed value from there - if ( hooks && "get" in hooks ) { - val = hooks.get( elem, true, extra ); - } - - // Otherwise, if a way to get the computed value exists, use that - if ( val === undefined ) { - val = curCSS( elem, name, styles ); - } - - //convert "normal" to computed value - if ( val === "normal" && name in cssNormalTransform ) { - val = cssNormalTransform[ name ]; - } - - // Return, converting to number if forced or a qualifier was provided and val looks numeric - if ( extra === "" || extra ) { - num = parseFloat( val ); - return extra === true || jQuery.isNumeric( num ) ? num || 0 : val; - } - return val; - } -}); - -// NOTE: we've included the "window" in window.getComputedStyle -// because jsdom on node.js will break without it. -if ( window.getComputedStyle ) { - getStyles = function( elem ) { - return window.getComputedStyle( elem, null ); - }; - - curCSS = function( elem, name, _computed ) { - var width, minWidth, maxWidth, - computed = _computed || getStyles( elem ), - - // getPropertyValue is only needed for .css('filter') in IE9, see #12537 - ret = computed ? computed.getPropertyValue( name ) || computed[ name ] : undefined, - style = elem.style; - - if ( computed ) { - - if ( ret === "" && !jQuery.contains( elem.ownerDocument, elem ) ) { - ret = jQuery.style( elem, name ); - } - - // A tribute to the "awesome hack by Dean Edwards" - // Chrome < 17 and Safari 5.0 uses "computed value" instead of "used value" for margin-right - // Safari 5.1.7 (at least) returns percentage for a larger set of values, but width seems to be reliably pixels - // this is against the CSSOM draft spec: http://dev.w3.org/csswg/cssom/#resolved-values - if ( rnumnonpx.test( ret ) && rmargin.test( name ) ) { - - // Remember the original values - width = style.width; - minWidth = style.minWidth; - maxWidth = style.maxWidth; - - // Put in the new values to get a computed value out - style.minWidth = style.maxWidth = style.width = ret; - ret = computed.width; - - // Revert the changed values - style.width = width; - style.minWidth = minWidth; - style.maxWidth = maxWidth; - } - } - - return ret; - }; -} else if ( document.documentElement.currentStyle ) { - getStyles = function( elem ) { - return elem.currentStyle; - }; - - curCSS = function( elem, name, _computed ) { - var left, rs, rsLeft, - computed = _computed || getStyles( elem ), - ret = computed ? computed[ name ] : undefined, - style = elem.style; - - // Avoid setting ret to empty string here - // so we don't default to auto - if ( ret == null && style && style[ name ] ) { - ret = style[ name ]; - } - - // From the awesome hack by Dean Edwards - // http://erik.eae.net/archives/2007/07/27/18.54.15/#comment-102291 - - // If we're not dealing with a regular pixel number - // but a number that has a weird ending, we need to convert it to pixels - // but not position css attributes, as those are proportional to the parent element instead - // and we can't measure the parent instead because it might trigger a "stacking dolls" problem - if ( rnumnonpx.test( ret ) && !rposition.test( name ) ) { - - // Remember the original values - left = style.left; - rs = elem.runtimeStyle; - rsLeft = rs && rs.left; - - // Put in the new values to get a computed value out - if ( rsLeft ) { - rs.left = elem.currentStyle.left; - } - style.left = name === "fontSize" ? "1em" : ret; - ret = style.pixelLeft + "px"; - - // Revert the changed values - style.left = left; - if ( rsLeft ) { - rs.left = rsLeft; - } - } - - return ret === "" ? "auto" : ret; - }; -} - -function setPositiveNumber( elem, value, subtract ) { - var matches = rnumsplit.exec( value ); - return matches ? - // Guard against undefined "subtract", e.g., when used as in cssHooks - Math.max( 0, matches[ 1 ] - ( subtract || 0 ) ) + ( matches[ 2 ] || "px" ) : - value; -} - -function augmentWidthOrHeight( elem, name, extra, isBorderBox, styles ) { - var i = extra === ( isBorderBox ? "border" : "content" ) ? - // If we already have the right measurement, avoid augmentation - 4 : - // Otherwise initialize for horizontal or vertical properties - name === "width" ? 1 : 0, - - val = 0; - - for ( ; i < 4; i += 2 ) { - // both box models exclude margin, so add it if we want it - if ( extra === "margin" ) { - val += jQuery.css( elem, extra + cssExpand[ i ], true, styles ); - } - - if ( isBorderBox ) { - // border-box includes padding, so remove it if we want content - if ( extra === "content" ) { - val -= jQuery.css( elem, "padding" + cssExpand[ i ], true, styles ); - } - - // at this point, extra isn't border nor margin, so remove border - if ( extra !== "margin" ) { - val -= jQuery.css( elem, "border" + cssExpand[ i ] + "Width", true, styles ); - } - } else { - // at this point, extra isn't content, so add padding - val += jQuery.css( elem, "padding" + cssExpand[ i ], true, styles ); - - // at this point, extra isn't content nor padding, so add border - if ( extra !== "padding" ) { - val += jQuery.css( elem, "border" + cssExpand[ i ] + "Width", true, styles ); - } - } - } - - return val; -} - -function getWidthOrHeight( elem, name, extra ) { - - // Start with offset property, which is equivalent to the border-box value - var valueIsBorderBox = true, - val = name === "width" ? elem.offsetWidth : elem.offsetHeight, - styles = getStyles( elem ), - isBorderBox = jQuery.support.boxSizing && jQuery.css( elem, "boxSizing", false, styles ) === "border-box"; - - // some non-html elements return undefined for offsetWidth, so check for null/undefined - // svg - https://bugzilla.mozilla.org/show_bug.cgi?id=649285 - // MathML - https://bugzilla.mozilla.org/show_bug.cgi?id=491668 - if ( val <= 0 || val == null ) { - // Fall back to computed then uncomputed css if necessary - val = curCSS( elem, name, styles ); - if ( val < 0 || val == null ) { - val = elem.style[ name ]; - } - - // Computed unit is not pixels. Stop here and return. - if ( rnumnonpx.test(val) ) { - return val; - } - - // we need the check for style in case a browser which returns unreliable values - // for getComputedStyle silently falls back to the reliable elem.style - valueIsBorderBox = isBorderBox && ( jQuery.support.boxSizingReliable || val === elem.style[ name ] ); - - // Normalize "", auto, and prepare for extra - val = parseFloat( val ) || 0; - } - - // use the active box-sizing model to add/subtract irrelevant styles - return ( val + - augmentWidthOrHeight( - elem, - name, - extra || ( isBorderBox ? "border" : "content" ), - valueIsBorderBox, - styles - ) - ) + "px"; -} - -// Try to determine the default display value of an element -function css_defaultDisplay( nodeName ) { - var doc = document, - display = elemdisplay[ nodeName ]; - - if ( !display ) { - display = actualDisplay( nodeName, doc ); - - // If the simple way fails, read from inside an iframe - if ( display === "none" || !display ) { - // Use the already-created iframe if possible - iframe = ( iframe || - jQuery("