From 043b464b1f9ba657d714d0e0357919971df20ef7 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 28 Nov 2022 09:18:59 +0100 Subject: [PATCH 001/183] [VPTOOP][WIP] Create a demonstrator of Design Document handling. * tools/vptool/vptool/vp_pack.py (Item.__init__): Set defaults for Design Doc references: ref mode 'page', viewer 'firefox'. * tools/vptool/vptool/vp.py (MyTextWidget.__init__): Add a grid-based area for design doc information. Include selectors for reference mode (page or section) and for document viewer (firefix or evince). Reduce size of design doc location. Fix typos. (MyTextWidget.vew_file): New. (MyTextWidget.refmode_btn_selected): Ditto. (MyTextWidget.docviewer_btn_selected): Ditto. (MyTextWidget.pack): Do not pack Requirement Location text at the MyText level. (MyTextWidget.update_ref_mode): New. (MyMain.update_desc_widget): Update ref mode state and child widget based on item state. (MyMain.update_ref_mode): New. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 88 ++++++++++++++++++++++++++++++++-- tools/vptool/vptool/vp_pack.py | 4 ++ 2 files changed, 89 insertions(+), 3 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index af214b54d..f6dcf8406 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -557,6 +557,42 @@ class MyTextWidget(ttk.LabelFrame): text=vp_config.yaml_config["gui"]["requirement_loc"]["label"], style="enabled.TLabelframe", ) + # Design doc information uses a grid layout. + # - first row is a URL of the document + # - second row contains selectors for page/section mode and value, and a 'View' button. + self.text1frame.grid(column=0, row=0, padx=20, pady=20) + url_label = ttk.Label(self.text1frame, text="Path or URL", anchor=tk.E) + url_label.grid(column=0, row=0, sticky=tk.E, padx=10, pady=10) + mode_label = ttk.Label(self.text1frame, text="Refer to...", anchor=tk.E) + mode_label.grid(column=0, row=1, sticky=tk.E, padx=10) + self.page_num_var = tk.StringVar(self) + page_entry = ttk.Entry(self.text1frame, textvariable=self.page_num_var, width=4) + page_entry.grid(column=2, row=1, sticky=tk.W) + self.section_num_var= tk.StringVar(self) + section_entry = ttk.Entry(self.text1frame, textvariable=self.section_num_var, width=4) + section_entry.grid(column=2, row=2, sticky=tk.W) + view_btn = ttk.Button(self.text1frame, text="Show design doc", command=self.view_file) + view_btn.grid(column=5, row=2, sticky=tk.E) + self.ref_mode_var = tk.StringVar(self) + ref_mode_names = ("(consecutive) page #", "section #") + ref_mode_values = ("page", "section") + row = 1 + for (name, value) in zip(ref_mode_names, ref_mode_values): + btn = ttk.Radiobutton(self.text1frame, text=name, value=value, variable=self.ref_mode_var, command=self.refmode_btn_selected) + btn.grid(column=1, row=row, sticky=tk.W) + row +=1 + # Label of the viewer selector buttons + viewer_label = ttk.Label(self.text1frame, text="Design doc viewer", anchor=tk.E) + viewer_label.grid(column=3, row=1, sticky=tk.E) + self.viewer_var = tk.StringVar(self) + viewer_names = ("Mozilla Firefox", "Evince PDF viewer") + viewer_values = ("firefox", "evince") + row = 1 + for (name, value) in zip(viewer_names, viewer_values): + btn = ttk.Radiobutton(self.text1frame, text=name, value=value, variable=self.viewer_var, command=self.docviewer_btn_selected) + btn.grid(column=4, row=row, sticky=tk.W) + row += 1 + self.text3frame = ttk.LabelFrame( self, text=vp_config.yaml_config["gui"]["verif_goals"]["label"], @@ -578,7 +614,7 @@ class MyTextWidget(ttk.LabelFrame): style="enabled.TLabelframe", ) # Selectors of verif point properties (PFC, TT, CM) and applicable cores use a layout - # different from the surrounding widgets, so we pack the in a canvas of their own. + # different from the surrounding widgets, so we pack them in a canvas of their own. self.selector_canvas = tk.Canvas(self) self.settings_frame = ttk.LabelFrame( self.selector_canvas, @@ -646,11 +682,12 @@ class MyTextWidget(ttk.LabelFrame): self.text1frame, cue_text=vp_config.yaml_config["gui"]["requirement_loc"]["cue_text"], state="disabled", - height=4, + height=1, bg=BG_COLOR, undo=True, wrap="word", ) + self.text1.grid(column=1, row=0, sticky=tk.W, columnspan=5) self.text3 = MyText( self.text3frame, cue_text=vp_config.yaml_config["gui"]["verif_goals"]["cue_text"], @@ -797,6 +834,41 @@ class MyTextWidget(ttk.LabelFrame): self.bcancel.pack(side="left") self.pack(side, padx, pady) + def view_file(self): + """ + View the requirement file (Design Doc) at the position specified in Requirement Location frame. + """ + print(f"### Calling MyTextWidget.view_file('{self.text1.get(0.0, tk.END).rstrip()}', '#page={self.page_num_var.get()}|#nameddest=section.{self.section_num_var.get()}'" + ) + if self.ref_mode_var.get() == "page": + ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" + elif self.ref_mode_var.get() == "section": + ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" + else: + ref_in_doc = "" + command = "firefox " + \ + self.text1.get(0.0, tk.END).rstrip() + ref_in_doc + print(f"### ==> command = {command}") + os.system(command) + + def refmode_btn_selected(self): + """ + Callback to handle the selection of the Design Doc reference mode. + Sets the value of the corresponding item attribute. + """ + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_mode = self.ref_mode_var.get() + + def docviewer_btn_selected(self): + """ + Callback to handle the selection of the design doc viewer. + Sets the value of the corresponding item attribute. + """ + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().viewer = self.viewer_var.get() + def all_cores_btn_selected(self): print("### self.cores_all.get() = %d" % self.cores_all.get()) if self.cores_all.get() == 1: @@ -910,7 +982,7 @@ class MyTextWidget(ttk.LabelFrame): def pack(self, side, padx, pady): self.text.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) - self.text1.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) + #self.text1.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text3.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text4.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text5.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) @@ -984,6 +1056,10 @@ class MyTextWidget(ttk.LabelFrame): def button_pack_forget(self): self.bframe.pack_forget() + def update_ref_mode(self, mode): + self.ref_mode = mode + self.ref_mode_var.set(mode) + def update_item_tag(self, in_text): self.text6.configure(state="normal") self.text6.delete("1.0", tk.END) @@ -1609,6 +1685,8 @@ class MyMain: self.desc_widget.text5, current_item.coverage_loc ) self.desc_widget.update_item_tag(current_item.tag) + ref_mode = current_item.ref_mode if hasattr(current_item, "ref_mode") else "page" + self.desc_widget.update_ref_mode(ref_mode) pfc = current_item.pfc self.desc_widget.update_pfc(pfc) test_type = current_item.test_type @@ -1652,6 +1730,10 @@ class MyMain: self.update_desc_widget() # reprint current item initial value self.unfreeze_all() + def update_ref_mode(self): + self.get_current_item().ref_mode = self.desc_widget.ref_mode_var.get() + self.desc_widget.update_ref_mode(self.desc_widget.ref_mode_var.get()) + def update_pfc(self): self.get_current_item().pfc = self.desc_widget.pfc.get() self.desc_widget.update_pfc(self.desc_widget.pfc.get()) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 052d0c6f3..3360f7f27 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -74,6 +74,10 @@ class Item: self.verif_goals = "" # Location of coverage data self.coverage_loc = "" + # Use page as the default reference mode for design docs. + # This will work with all files (no reliance on named dests). + self.ref_mode = "page" + self.viewer = "firefox" # FIXME: Propagate default value from YAML config. self.pfc = -1 # none selected, must choose self.test_type = -1 # none selected, must choose From f9b7be394339f00ec60a39a16c3a472913ffaaec Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 28 Nov 2022 20:50:53 +0100 Subject: [PATCH 002/183] [VPTOOL] Add fully functional requirement visualization widget. * tools/vptool/vptool/vp.py (MyTextWidget.__init__): Add callback trigger to page and section number fields. (MyTextWidget.ref_page_num_changed): New callback. (MyTextWidget.ref_section_num_changed): Ditto. (MyTextWidget.view_file): Do not print input args on console. Construct command line args according to viewing mode (HTML/PDF). Run command in background to allow editing while viewing the requirement doc. (MyTextWidget.viewer_btn_selected): Rename viewer attribute in Item to 'ref_viewer'. (MyTextWidget.update_page_num): New. (MyTextWidget.update_section_num): Ditto. (MyTextWidget.update_viewer): Ditto. (MyMain.update_desc_widget): Use try/except to detect missing fields in database. (MyMain.update_page_num): New. (MyMain.update_section_num): Ditto. (MyMain.update_viewer): Ditto. * tools/vptool/vptool/vp_pack.py (Item.__init__): Update comments. Rename 'viewer' to 'ref_viewer'. Add defaults for page and section attributes. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 104 ++++++++++++++++++++++++++++----- tools/vptool/vptool/vp_pack.py | 7 ++- 2 files changed, 96 insertions(+), 15 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index f6dcf8406..f171ef3a4 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -568,9 +568,15 @@ class MyTextWidget(ttk.LabelFrame): self.page_num_var = tk.StringVar(self) page_entry = ttk.Entry(self.text1frame, textvariable=self.page_num_var, width=4) page_entry.grid(column=2, row=1, sticky=tk.W) + # Use a callaback to update state upon changes to page number field. + self.page_num_var.trace("w", self.ref_page_num_changed) + self.section_num_var= tk.StringVar(self) section_entry = ttk.Entry(self.text1frame, textvariable=self.section_num_var, width=4) section_entry.grid(column=2, row=2, sticky=tk.W) + # Use a callaback to update state upon changes to section number field. + self.section_num_var.trace("w", self.ref_section_num_changed) + view_btn = ttk.Button(self.text1frame, text="Show design doc", command=self.view_file) view_btn.grid(column=5, row=2, sticky=tk.E) self.ref_mode_var = tk.StringVar(self) @@ -834,22 +840,43 @@ class MyTextWidget(ttk.LabelFrame): self.bcancel.pack(side="left") self.pack(side, padx, pady) + def ref_page_num_changed(self, *args): + """React to change in page number stringvar.""" + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_page = self.page_num_var.get() + + def ref_section_num_changed(self, *args): + """React to change in section number stringvar.""" + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_section = self.section_num_var.get() + def view_file(self): """ View the requirement file (Design Doc) at the position specified in Requirement Location frame. """ - print(f"### Calling MyTextWidget.view_file('{self.text1.get(0.0, tk.END).rstrip()}', '#page={self.page_num_var.get()}|#nameddest=section.{self.section_num_var.get()}'" - ) - if self.ref_mode_var.get() == "page": - ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" - elif self.ref_mode_var.get() == "section": - ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" - else: - ref_in_doc = "" - command = "firefox " + \ - self.text1.get(0.0, tk.END).rstrip() + ref_in_doc + if self.viewer_var.get() == "firefox": + # Browser mode: use HREFs with suffix #=. + if self.ref_mode_var.get() == "page": + ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" + elif self.ref_mode_var.get() == "section": + ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" + else: + ref_in_doc = "" + command = [ "firefox", + "file://" + self.text1.get(0.0, tk.END).rstrip() + ref_in_doc ] + elif self.viewer_var.get() == "evince": + # PDF viewer mode: use appropriate cmdline option. + if self.ref_mode_var.get() == "page": + ref_in_doc = ["-i", f"{self.page_num_var.get().rstrip()}" ] + elif self.ref_mode_var.get() == "section": + ref_in_doc = ["-n", f"section.{self.section_num_var.get().rstrip()}"] + else: + ref_in_doc = [] + command = ["evince"] + ref_in_doc + [self.text1.get(0.0, tk.END).rstrip()] print(f"### ==> command = {command}") - os.system(command) + subprocess.Popen(command) def refmode_btn_selected(self): """ @@ -867,7 +894,7 @@ class MyTextWidget(ttk.LabelFrame): """ current_item = self.parent.item_widget.get_selection() if current_item and not self.parent.get_current_item().is_locked(): - self.parent.get_current_item().viewer = self.viewer_var.get() + self.parent.get_current_item().ref_viewer = self.viewer_var.get() def all_cores_btn_selected(self): print("### self.cores_all.get() = %d" % self.cores_all.get()) @@ -1060,6 +1087,18 @@ class MyTextWidget(ttk.LabelFrame): self.ref_mode = mode self.ref_mode_var.set(mode) + def update_page_num(self, page): + self.page_num = page + self.page_num_var.set(page) + + def update_section_num(self, section): + self.section_num = section + self.section_num_var.set(section) + + def update_viewer(self, viewer): + self.viewer = viewer + self.viewer_var.set(viewer) + def update_item_tag(self, in_text): self.text6.configure(state="normal") self.text6.delete("1.0", tk.END) @@ -1685,8 +1724,35 @@ class MyMain: self.desc_widget.text5, current_item.coverage_loc ) self.desc_widget.update_item_tag(current_item.tag) - ref_mode = current_item.ref_mode if hasattr(current_item, "ref_mode") else "page" + # Update mode of reference to location inside design doc. + # DB migration: Assume 'page' as default if the field was not present. + try: + ref_mode = current_item.ref_mode + except AttributeError: + ref_mode = "page" self.desc_widget.update_ref_mode(ref_mode) + # Update page number inside design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_page = current_item.ref_page + except AttributeError: + ref_page = "" + self.desc_widget.update_page_num(ref_page) + # Update section number inside design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_section = current_item.ref_section + except AttributeError: + ref_section = "" + self.desc_widget.update_section_num(ref_section) + # Update name of viewer app that should be used to display the design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_viewer = current_item.ref_viewer + except AttributeError: + ref_viewer = "firefox" + self.desc_widget.update_viewer(ref_viewer) + pfc = current_item.pfc self.desc_widget.update_pfc(pfc) test_type = current_item.test_type @@ -1734,6 +1800,18 @@ class MyMain: self.get_current_item().ref_mode = self.desc_widget.ref_mode_var.get() self.desc_widget.update_ref_mode(self.desc_widget.ref_mode_var.get()) + def update_page_num(self): + self.get_current_item().ref_page = self.desc_widget.page_num_var.get() + self.desc_widget.update_page_num(self.desc_widget.page_num_var.get()) + + def update_section_num(self): + self.get_current_item().ref_section = self.desc_widget.section_num_var.get() + self.desc_widget.update_section_num(self.desc_widget.section_num_var.get()) + + def update_viewer(self): + self.get_current_item().ref_viewer = self.desc_widget.viewer_var.get() + self.desc_widget.update_viewer(self.desc_widget.viewer_var.get()) + def update_pfc(self): self.get_current_item().pfc = self.desc_widget.pfc.get() self.desc_widget.update_pfc(self.desc_widget.pfc.get()) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 3360f7f27..2f6f9e7bc 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -68,7 +68,8 @@ class Item: self.tag = tag # Description of feature to be tested self.description = description - # Requirement to be verified + # Requirement to be verified (from now on, the design document...) + # FIXME: field naming needs a major rework. self.purpose = purpose # Summary of verification goals self.verif_goals = "" @@ -77,7 +78,9 @@ class Item: # Use page as the default reference mode for design docs. # This will work with all files (no reliance on named dests). self.ref_mode = "page" - self.viewer = "firefox" + self.ref_page = "" + self.ref_section = "" + self.ref_viewer = "firefox" # FIXME: Propagate default value from YAML config. self.pfc = -1 # none selected, must choose self.test_type = -1 # none selected, must choose From 63916fceea5afadcd6cac0827eb2182c5e9383b0 Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Wed, 7 Dec 2022 10:51:24 +0100 Subject: [PATCH 003/183] fix dm_pkg path Signed-off-by: Jean-Roch Coulon --- cva6/tb/core/Flist.cva6_tb | 1 + 1 file changed, 1 insertion(+) diff --git a/cva6/tb/core/Flist.cva6_tb b/cva6/tb/core/Flist.cva6_tb index 9fb590029..d366d8017 100644 --- a/cva6/tb/core/Flist.cva6_tb +++ b/cva6/tb/core/Flist.cva6_tb @@ -26,6 +26,7 @@ /////////////////////////////////////////////////////////////////////////////// // These need to be moved +${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv ${CVA6_REPO_DIR}/corev_apu/axi_mem_if/src/axi2mem.sv ${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv From b85d6adbd59ff74c97540f4ae18a2443351125b1 Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Mon, 12 Dec 2022 09:29:08 +0100 Subject: [PATCH 004/183] Use only one Flist for all configurations Signed-off-by: Jean-Roch Coulon --- cva6/sim/Makefile | 5 ++++- cva6/sim/cva6.yaml | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index ca1523ce2..bcceaee51 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -16,6 +16,9 @@ export CVA6_REPO_DIR = $(abspath $(root-dir)../../core-v-cores/cva6/) export CVA6_TB_DIR = $(root-dir)/../tb/core export CORE_V_VERIF = $(root-dir)/../.. endif +ifndef TARGET_CFG +export TARGET_CFG = $(target) +endif .DEFAULT_GOAL := help @@ -23,7 +26,7 @@ FLIST_TB := $(CVA6_TB_DIR)/Flist.cva6_tb # target takes one of the following cva6 hardware configuration: # cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32 target ?= cv64a6_imafdc_sv39 -FLIST_CORE := $(CVA6_REPO_DIR)/core/Flist.$(target) +FLIST_CORE := $(if $(gate), $(CVA6_REPO_DIR)/core/Flist.cva6_gate,$(CVA6_REPO_DIR)/core/Flist.cva6) TRACE_FAST ?= TRACE_COMPACT ?= diff --git a/cva6/sim/cva6.yaml b/cva6/sim/cva6.yaml index 2c91c7cf8..08bf29fa3 100644 --- a/cva6/sim/cva6.yaml +++ b/cva6/sim/cva6.yaml @@ -42,7 +42,7 @@ tool_path: SPIKE_PATH tb_path: TB_PATH cmd: > - make vcs-uvm target=_gate cov=${cov} variant= elf= tool_path= isscomp_opts= issrun_opts= isspostrun_opts= log= + make vcs-uvm target= gate=1 cov=${cov} variant= elf= tool_path= isscomp_opts= issrun_opts= isspostrun_opts= log= - iss: vcs-uvm path_var: RTL_PATH From fbf9275942a58ca7af34d0e336bb1b0ac5cf8f09 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 28 Nov 2022 09:18:59 +0100 Subject: [PATCH 005/183] [VPTOOP][WIP] Create a demonstrator of Design Document handling. * tools/vptool/vptool/vp_pack.py (Item.__init__): Set defaults for Design Doc references: ref mode 'page', viewer 'firefox'. * tools/vptool/vptool/vp.py (MyTextWidget.__init__): Add a grid-based area for design doc information. Include selectors for reference mode (page or section) and for document viewer (firefix or evince). Reduce size of design doc location. Fix typos. (MyTextWidget.vew_file): New. (MyTextWidget.refmode_btn_selected): Ditto. (MyTextWidget.docviewer_btn_selected): Ditto. (MyTextWidget.pack): Do not pack Requirement Location text at the MyText level. (MyTextWidget.update_ref_mode): New. (MyMain.update_desc_widget): Update ref mode state and child widget based on item state. (MyMain.update_ref_mode): New. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 88 ++++++++++++++++++++++++++++++++-- tools/vptool/vptool/vp_pack.py | 4 ++ 2 files changed, 89 insertions(+), 3 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index af214b54d..f6dcf8406 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -557,6 +557,42 @@ class MyTextWidget(ttk.LabelFrame): text=vp_config.yaml_config["gui"]["requirement_loc"]["label"], style="enabled.TLabelframe", ) + # Design doc information uses a grid layout. + # - first row is a URL of the document + # - second row contains selectors for page/section mode and value, and a 'View' button. + self.text1frame.grid(column=0, row=0, padx=20, pady=20) + url_label = ttk.Label(self.text1frame, text="Path or URL", anchor=tk.E) + url_label.grid(column=0, row=0, sticky=tk.E, padx=10, pady=10) + mode_label = ttk.Label(self.text1frame, text="Refer to...", anchor=tk.E) + mode_label.grid(column=0, row=1, sticky=tk.E, padx=10) + self.page_num_var = tk.StringVar(self) + page_entry = ttk.Entry(self.text1frame, textvariable=self.page_num_var, width=4) + page_entry.grid(column=2, row=1, sticky=tk.W) + self.section_num_var= tk.StringVar(self) + section_entry = ttk.Entry(self.text1frame, textvariable=self.section_num_var, width=4) + section_entry.grid(column=2, row=2, sticky=tk.W) + view_btn = ttk.Button(self.text1frame, text="Show design doc", command=self.view_file) + view_btn.grid(column=5, row=2, sticky=tk.E) + self.ref_mode_var = tk.StringVar(self) + ref_mode_names = ("(consecutive) page #", "section #") + ref_mode_values = ("page", "section") + row = 1 + for (name, value) in zip(ref_mode_names, ref_mode_values): + btn = ttk.Radiobutton(self.text1frame, text=name, value=value, variable=self.ref_mode_var, command=self.refmode_btn_selected) + btn.grid(column=1, row=row, sticky=tk.W) + row +=1 + # Label of the viewer selector buttons + viewer_label = ttk.Label(self.text1frame, text="Design doc viewer", anchor=tk.E) + viewer_label.grid(column=3, row=1, sticky=tk.E) + self.viewer_var = tk.StringVar(self) + viewer_names = ("Mozilla Firefox", "Evince PDF viewer") + viewer_values = ("firefox", "evince") + row = 1 + for (name, value) in zip(viewer_names, viewer_values): + btn = ttk.Radiobutton(self.text1frame, text=name, value=value, variable=self.viewer_var, command=self.docviewer_btn_selected) + btn.grid(column=4, row=row, sticky=tk.W) + row += 1 + self.text3frame = ttk.LabelFrame( self, text=vp_config.yaml_config["gui"]["verif_goals"]["label"], @@ -578,7 +614,7 @@ class MyTextWidget(ttk.LabelFrame): style="enabled.TLabelframe", ) # Selectors of verif point properties (PFC, TT, CM) and applicable cores use a layout - # different from the surrounding widgets, so we pack the in a canvas of their own. + # different from the surrounding widgets, so we pack them in a canvas of their own. self.selector_canvas = tk.Canvas(self) self.settings_frame = ttk.LabelFrame( self.selector_canvas, @@ -646,11 +682,12 @@ class MyTextWidget(ttk.LabelFrame): self.text1frame, cue_text=vp_config.yaml_config["gui"]["requirement_loc"]["cue_text"], state="disabled", - height=4, + height=1, bg=BG_COLOR, undo=True, wrap="word", ) + self.text1.grid(column=1, row=0, sticky=tk.W, columnspan=5) self.text3 = MyText( self.text3frame, cue_text=vp_config.yaml_config["gui"]["verif_goals"]["cue_text"], @@ -797,6 +834,41 @@ class MyTextWidget(ttk.LabelFrame): self.bcancel.pack(side="left") self.pack(side, padx, pady) + def view_file(self): + """ + View the requirement file (Design Doc) at the position specified in Requirement Location frame. + """ + print(f"### Calling MyTextWidget.view_file('{self.text1.get(0.0, tk.END).rstrip()}', '#page={self.page_num_var.get()}|#nameddest=section.{self.section_num_var.get()}'" + ) + if self.ref_mode_var.get() == "page": + ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" + elif self.ref_mode_var.get() == "section": + ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" + else: + ref_in_doc = "" + command = "firefox " + \ + self.text1.get(0.0, tk.END).rstrip() + ref_in_doc + print(f"### ==> command = {command}") + os.system(command) + + def refmode_btn_selected(self): + """ + Callback to handle the selection of the Design Doc reference mode. + Sets the value of the corresponding item attribute. + """ + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_mode = self.ref_mode_var.get() + + def docviewer_btn_selected(self): + """ + Callback to handle the selection of the design doc viewer. + Sets the value of the corresponding item attribute. + """ + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().viewer = self.viewer_var.get() + def all_cores_btn_selected(self): print("### self.cores_all.get() = %d" % self.cores_all.get()) if self.cores_all.get() == 1: @@ -910,7 +982,7 @@ class MyTextWidget(ttk.LabelFrame): def pack(self, side, padx, pady): self.text.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) - self.text1.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) + #self.text1.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text3.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text4.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) self.text5.pack(side="top", padx=padx, pady=pady, fill="both", expand=True) @@ -984,6 +1056,10 @@ class MyTextWidget(ttk.LabelFrame): def button_pack_forget(self): self.bframe.pack_forget() + def update_ref_mode(self, mode): + self.ref_mode = mode + self.ref_mode_var.set(mode) + def update_item_tag(self, in_text): self.text6.configure(state="normal") self.text6.delete("1.0", tk.END) @@ -1609,6 +1685,8 @@ class MyMain: self.desc_widget.text5, current_item.coverage_loc ) self.desc_widget.update_item_tag(current_item.tag) + ref_mode = current_item.ref_mode if hasattr(current_item, "ref_mode") else "page" + self.desc_widget.update_ref_mode(ref_mode) pfc = current_item.pfc self.desc_widget.update_pfc(pfc) test_type = current_item.test_type @@ -1652,6 +1730,10 @@ class MyMain: self.update_desc_widget() # reprint current item initial value self.unfreeze_all() + def update_ref_mode(self): + self.get_current_item().ref_mode = self.desc_widget.ref_mode_var.get() + self.desc_widget.update_ref_mode(self.desc_widget.ref_mode_var.get()) + def update_pfc(self): self.get_current_item().pfc = self.desc_widget.pfc.get() self.desc_widget.update_pfc(self.desc_widget.pfc.get()) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 052d0c6f3..3360f7f27 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -74,6 +74,10 @@ class Item: self.verif_goals = "" # Location of coverage data self.coverage_loc = "" + # Use page as the default reference mode for design docs. + # This will work with all files (no reliance on named dests). + self.ref_mode = "page" + self.viewer = "firefox" # FIXME: Propagate default value from YAML config. self.pfc = -1 # none selected, must choose self.test_type = -1 # none selected, must choose From b5e7c78b870145a3a4ded7937154bf863663015d Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 28 Nov 2022 20:50:53 +0100 Subject: [PATCH 006/183] [VPTOOL] Add fully functional requirement visualization widget. * tools/vptool/vptool/vp.py (MyTextWidget.__init__): Add callback trigger to page and section number fields. (MyTextWidget.ref_page_num_changed): New callback. (MyTextWidget.ref_section_num_changed): Ditto. (MyTextWidget.view_file): Do not print input args on console. Construct command line args according to viewing mode (HTML/PDF). Run command in background to allow editing while viewing the requirement doc. (MyTextWidget.viewer_btn_selected): Rename viewer attribute in Item to 'ref_viewer'. (MyTextWidget.update_page_num): New. (MyTextWidget.update_section_num): Ditto. (MyTextWidget.update_viewer): Ditto. (MyMain.update_desc_widget): Use try/except to detect missing fields in database. (MyMain.update_page_num): New. (MyMain.update_section_num): Ditto. (MyMain.update_viewer): Ditto. * tools/vptool/vptool/vp_pack.py (Item.__init__): Update comments. Rename 'viewer' to 'ref_viewer'. Add defaults for page and section attributes. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 104 ++++++++++++++++++++++++++++----- tools/vptool/vptool/vp_pack.py | 7 ++- 2 files changed, 96 insertions(+), 15 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index f6dcf8406..f171ef3a4 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -568,9 +568,15 @@ class MyTextWidget(ttk.LabelFrame): self.page_num_var = tk.StringVar(self) page_entry = ttk.Entry(self.text1frame, textvariable=self.page_num_var, width=4) page_entry.grid(column=2, row=1, sticky=tk.W) + # Use a callaback to update state upon changes to page number field. + self.page_num_var.trace("w", self.ref_page_num_changed) + self.section_num_var= tk.StringVar(self) section_entry = ttk.Entry(self.text1frame, textvariable=self.section_num_var, width=4) section_entry.grid(column=2, row=2, sticky=tk.W) + # Use a callaback to update state upon changes to section number field. + self.section_num_var.trace("w", self.ref_section_num_changed) + view_btn = ttk.Button(self.text1frame, text="Show design doc", command=self.view_file) view_btn.grid(column=5, row=2, sticky=tk.E) self.ref_mode_var = tk.StringVar(self) @@ -834,22 +840,43 @@ class MyTextWidget(ttk.LabelFrame): self.bcancel.pack(side="left") self.pack(side, padx, pady) + def ref_page_num_changed(self, *args): + """React to change in page number stringvar.""" + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_page = self.page_num_var.get() + + def ref_section_num_changed(self, *args): + """React to change in section number stringvar.""" + current_item = self.parent.item_widget.get_selection() + if current_item and not self.parent.get_current_item().is_locked(): + self.parent.get_current_item().ref_section = self.section_num_var.get() + def view_file(self): """ View the requirement file (Design Doc) at the position specified in Requirement Location frame. """ - print(f"### Calling MyTextWidget.view_file('{self.text1.get(0.0, tk.END).rstrip()}', '#page={self.page_num_var.get()}|#nameddest=section.{self.section_num_var.get()}'" - ) - if self.ref_mode_var.get() == "page": - ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" - elif self.ref_mode_var.get() == "section": - ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" - else: - ref_in_doc = "" - command = "firefox " + \ - self.text1.get(0.0, tk.END).rstrip() + ref_in_doc + if self.viewer_var.get() == "firefox": + # Browser mode: use HREFs with suffix #=. + if self.ref_mode_var.get() == "page": + ref_in_doc = f"#page={self.page_num_var.get().rstrip()}" + elif self.ref_mode_var.get() == "section": + ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" + else: + ref_in_doc = "" + command = [ "firefox", + "file://" + self.text1.get(0.0, tk.END).rstrip() + ref_in_doc ] + elif self.viewer_var.get() == "evince": + # PDF viewer mode: use appropriate cmdline option. + if self.ref_mode_var.get() == "page": + ref_in_doc = ["-i", f"{self.page_num_var.get().rstrip()}" ] + elif self.ref_mode_var.get() == "section": + ref_in_doc = ["-n", f"section.{self.section_num_var.get().rstrip()}"] + else: + ref_in_doc = [] + command = ["evince"] + ref_in_doc + [self.text1.get(0.0, tk.END).rstrip()] print(f"### ==> command = {command}") - os.system(command) + subprocess.Popen(command) def refmode_btn_selected(self): """ @@ -867,7 +894,7 @@ class MyTextWidget(ttk.LabelFrame): """ current_item = self.parent.item_widget.get_selection() if current_item and not self.parent.get_current_item().is_locked(): - self.parent.get_current_item().viewer = self.viewer_var.get() + self.parent.get_current_item().ref_viewer = self.viewer_var.get() def all_cores_btn_selected(self): print("### self.cores_all.get() = %d" % self.cores_all.get()) @@ -1060,6 +1087,18 @@ class MyTextWidget(ttk.LabelFrame): self.ref_mode = mode self.ref_mode_var.set(mode) + def update_page_num(self, page): + self.page_num = page + self.page_num_var.set(page) + + def update_section_num(self, section): + self.section_num = section + self.section_num_var.set(section) + + def update_viewer(self, viewer): + self.viewer = viewer + self.viewer_var.set(viewer) + def update_item_tag(self, in_text): self.text6.configure(state="normal") self.text6.delete("1.0", tk.END) @@ -1685,8 +1724,35 @@ class MyMain: self.desc_widget.text5, current_item.coverage_loc ) self.desc_widget.update_item_tag(current_item.tag) - ref_mode = current_item.ref_mode if hasattr(current_item, "ref_mode") else "page" + # Update mode of reference to location inside design doc. + # DB migration: Assume 'page' as default if the field was not present. + try: + ref_mode = current_item.ref_mode + except AttributeError: + ref_mode = "page" self.desc_widget.update_ref_mode(ref_mode) + # Update page number inside design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_page = current_item.ref_page + except AttributeError: + ref_page = "" + self.desc_widget.update_page_num(ref_page) + # Update section number inside design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_section = current_item.ref_section + except AttributeError: + ref_section = "" + self.desc_widget.update_section_num(ref_section) + # Update name of viewer app that should be used to display the design doc. + # DB migration: Assume empty string as default if the field was not present. + try: + ref_viewer = current_item.ref_viewer + except AttributeError: + ref_viewer = "firefox" + self.desc_widget.update_viewer(ref_viewer) + pfc = current_item.pfc self.desc_widget.update_pfc(pfc) test_type = current_item.test_type @@ -1734,6 +1800,18 @@ class MyMain: self.get_current_item().ref_mode = self.desc_widget.ref_mode_var.get() self.desc_widget.update_ref_mode(self.desc_widget.ref_mode_var.get()) + def update_page_num(self): + self.get_current_item().ref_page = self.desc_widget.page_num_var.get() + self.desc_widget.update_page_num(self.desc_widget.page_num_var.get()) + + def update_section_num(self): + self.get_current_item().ref_section = self.desc_widget.section_num_var.get() + self.desc_widget.update_section_num(self.desc_widget.section_num_var.get()) + + def update_viewer(self): + self.get_current_item().ref_viewer = self.desc_widget.viewer_var.get() + self.desc_widget.update_viewer(self.desc_widget.viewer_var.get()) + def update_pfc(self): self.get_current_item().pfc = self.desc_widget.pfc.get() self.desc_widget.update_pfc(self.desc_widget.pfc.get()) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 3360f7f27..2f6f9e7bc 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -68,7 +68,8 @@ class Item: self.tag = tag # Description of feature to be tested self.description = description - # Requirement to be verified + # Requirement to be verified (from now on, the design document...) + # FIXME: field naming needs a major rework. self.purpose = purpose # Summary of verification goals self.verif_goals = "" @@ -77,7 +78,9 @@ class Item: # Use page as the default reference mode for design docs. # This will work with all files (no reliance on named dests). self.ref_mode = "page" - self.viewer = "firefox" + self.ref_page = "" + self.ref_section = "" + self.ref_viewer = "firefox" # FIXME: Propagate default value from YAML config. self.pfc = -1 # none selected, must choose self.test_type = -1 # none selected, must choose From 97079a2136953760b3d5f282b6f3785b5fc52c50 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 19 Dec 2022 17:34:47 +0100 Subject: [PATCH 007/183] [VPTOOL] Correctly handle requirement location URLs. * tools/vptool/vptool/vp.py (MyTextWidgegt.view_file): Rename to 'view_design_doc'. Do not prepend "file://" to req't. location unless it is an absolute file name. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index f171ef3a4..bb29befc7 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -577,7 +577,7 @@ class MyTextWidget(ttk.LabelFrame): # Use a callaback to update state upon changes to section number field. self.section_num_var.trace("w", self.ref_section_num_changed) - view_btn = ttk.Button(self.text1frame, text="Show design doc", command=self.view_file) + view_btn = ttk.Button(self.text1frame, text="View design doc", command=self.view_design_doc) view_btn.grid(column=5, row=2, sticky=tk.E) self.ref_mode_var = tk.StringVar(self) ref_mode_names = ("(consecutive) page #", "section #") @@ -852,7 +852,7 @@ class MyTextWidget(ttk.LabelFrame): if current_item and not self.parent.get_current_item().is_locked(): self.parent.get_current_item().ref_section = self.section_num_var.get() - def view_file(self): + def view_design_doc(self): """ View the requirement file (Design Doc) at the position specified in Requirement Location frame. """ @@ -864,8 +864,13 @@ class MyTextWidget(ttk.LabelFrame): ref_in_doc = f"#nameddest=section.{self.section_num_var.get().rstrip()}" else: ref_in_doc = "" - command = [ "firefox", - "file://" + self.text1.get(0.0, tk.END).rstrip() + ref_in_doc ] + # Assume the location is a valid URL or an absolute path. + doc_location = self.text1.get(0.0, tk.END).rstrip() + # If no scheme (http://, file:// etc.) is given, treat it + # as an absolute file path. + if doc_location[0] == '/': + doc_location = "file://" + doc_location + command = [ "firefox", doc_location + ref_in_doc ] elif self.viewer_var.get() == "evince": # PDF viewer mode: use appropriate cmdline option. if self.ref_mode_var.get() == "page": @@ -874,6 +879,7 @@ class MyTextWidget(ttk.LabelFrame): ref_in_doc = ["-n", f"section.{self.section_num_var.get().rstrip()}"] else: ref_in_doc = [] + # The requirement location should be a valid path to a PDF file. command = ["evince"] + ref_in_doc + [self.text1.get(0.0, tk.END).rstrip()] print(f"### ==> command = {command}") subprocess.Popen(command) From 3174e11a7fe0e7018e80eea66cca0efeba3f135b Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Tue, 20 Dec 2022 16:35:11 +0100 Subject: [PATCH 008/183] [VPTOOL] Make design doc URL/path text higher to show multiline content. * tools/vptool/vptool/vp.py (MyTextWidget.__init__): Increase height of "Path or URL" text field to two lines to show potential multiline content and/or long paths. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index bb29befc7..a782de3ee 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -688,7 +688,7 @@ class MyTextWidget(ttk.LabelFrame): self.text1frame, cue_text=vp_config.yaml_config["gui"]["requirement_loc"]["cue_text"], state="disabled", - height=1, + height=2, bg=BG_COLOR, undo=True, wrap="word", From d06d20e54c6dc31729be82041f06410b456a3c49 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 30 Jan 2023 17:26:51 +0100 Subject: [PATCH 009/183] Disable A extension in CV32A60X step1 config. Adapt CVA6 BSP accordingly. * cva/sim/cva6.py (load_config): Disable A extension for cv32a60x config. * cva6/tests/custom/common/syscalls.c (syscall): Do not use synchronization primitives without A extension. * cva6/tests/custom/common/util.h (barrier): Disable functionality when no A extension is present. Signed-off-by: Zbigniew Chamski --- cva6/sim/cva6.py | 2 +- cva6/tests/custom/common/syscalls.c | 4 ++++ cva6/tests/custom/common/util.h | 2 ++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/cva6/sim/cva6.py b/cva6/sim/cva6.py index 433874468..79f441332 100644 --- a/cva6/sim/cva6.py +++ b/cva6/sim/cva6.py @@ -857,7 +857,7 @@ def load_config(args, cwd): args.isa = "rv64gc" elif args.target == "cv32a60x": args.mabi = "ilp32" - args.isa = "rv32imac" # A is needed to compile custom BSP + args.isa = "rv32imc" # Step1 configuration has no A extension. elif args.target == "cv32a6_imac_sv0": args.mabi = "ilp32" args.isa = "rv32imac" diff --git a/cva6/tests/custom/common/syscalls.c b/cva6/tests/custom/common/syscalls.c index 71cfa3300..827de9fce 100644 --- a/cva6/tests/custom/common/syscalls.c +++ b/cva6/tests/custom/common/syscalls.c @@ -22,14 +22,18 @@ static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t magic_mem[1] = arg0; magic_mem[2] = arg1; magic_mem[3] = arg2; +#ifdef __riscv_atomic // __sync_synchronize requires A extension __sync_synchronize(); +#endif tohost = (uintptr_t)magic_mem; while (fromhost == 0) ; fromhost = 0; +#ifdef __riscv_atomic // __sync_synchronize requires A extension __sync_synchronize(); +#endif return magic_mem[0]; } diff --git a/cva6/tests/custom/common/util.h b/cva6/tests/custom/common/util.h index 081cfd634..78fa62401 100644 --- a/cva6/tests/custom/common/util.h +++ b/cva6/tests/custom/common/util.h @@ -43,6 +43,7 @@ static int verifyDouble(int n, const volatile double* test, const double* verify static void __attribute__((noinline)) barrier(int ncores) { +#ifdef __riscv_atomic // __sync_* builtins require A extension static volatile int sense; static volatile int count; static __thread int threadsense; @@ -59,6 +60,7 @@ static void __attribute__((noinline)) barrier(int ncores) ; __sync_synchronize(); +#endif // __riscv_atomic } static uint64_t lfsr(uint64_t x) From ce663f01b26aac1cd491eccfc50a7a46dca21d97 Mon Sep 17 00:00:00 2001 From: Rana Adeel Ahmad Date: Tue, 31 Jan 2023 18:50:56 +0500 Subject: [PATCH 010/183] Documentation for the UVM_Verification Environment for CVA6 core. --- cva6/docs/UVM_verif_env.md | 222 +++++++++++++++++++++++ cva6/docs/images/CVA6_UVM_env.drawio.png | Bin 0 -> 37342 bytes 2 files changed, 222 insertions(+) create mode 100644 cva6/docs/UVM_verif_env.md create mode 100644 cva6/docs/images/CVA6_UVM_env.drawio.png diff --git a/cva6/docs/UVM_verif_env.md b/cva6/docs/UVM_verif_env.md new file mode 100644 index 000000000..ccd58d9c3 --- /dev/null +++ b/cva6/docs/UVM_verif_env.md @@ -0,0 +1,222 @@ + +# The CVA6 UVM Verification Environment + + +This document describes the uvm verification environment of the CVA6 core. This environment is intended to be able to verify the CVA6 core and run different test cases by the minimal modification to the environment itself. The environment is shown below: + +![alt_text](images/CVA6_UVM_env.drawio.png "image_tooltip") + +*** + +This environment consist of the following + +1. Simple two uvm agents for the uvma_clknrst_if and uvma_cvxif_intf . +2. Result checking capability is built into the environment so the test cases do not need to determine and check for the pass/fail criteria. + +The environment consists of disjoint components. When a user invokes a command to run a test case a set of scripts and makefile rules are invoked to compile the environment and tests, run the simulation and check the results. On running a particular test it generates a .bin file which then is loaded into the main memory in the tb_top at the Boot_address of the core and the instructions are then start executing. + +## uvmt_cva6_tb + +In this module we instantiate the agent interfaces and the `uvmt_cva6_dut_wrap` module. We set the interfaces for the uvma_clknrst and uvma_cvxif using the configuration database set method. In this module we get the `sim_finished` database object set in the `uvmt_cva6_base_test_c` class. To check whether the simulation passed or failed we check the `err_count` and `fatal_count` along with `sim_finished`. + +## uvmt_cva6_base_test_c + +This class extends from `uvm_test`. It randomise the `uvmt_cva6_test_cfg_c` and `uvme_cva6_cfg_c` objects. The class's build_phase, connect_phase functions handle the setup and configuration of the testbench environment, connecting it to the CVA6, and executing the test. We start the `uvme_cva6_reset_vseq_c` sequence in the reset phase on the `uvme_cva6_vsqr_c` sequencer. + +## uvme_cva6_env_c + +This class extends from the `uvm_env` class. The class's build_phase,connect_phase functions handle the setup and configuration of the `uvma_clknrst_agent_c`,`uvma_cvxif_agent_c` agents.The class's run_phase task start the `cvxif_seq` sequence on the uvma_cvxif_agent sequencer. We get the configuration and context information for the environment in this class using the get method. + +### Environment_objects + +There are two uvm_objects that are `uvme_cva6_cfg_c` and `uvme_cva6_cntxt_c`. The Objects contain configuration and context information for the environment. + +### uvme_cva6_cfg_c + +This class extends from the `uvm_object` class. The object encapsulates all parameters for creating, connecting and running CVA6 environment (`uvme_cva6_env_c`) components. This class also includes a constraint block that defines default values for some of its fields and other constraints on its fields such as, `enabled` and `is_active` fields are set to 0 and 'UVM_PASSIVE' respectively by default. `clknrst_cfg.enabled` and `clknrst_cfg.is_active` are set to 1 if `enabled` and `is_active` fields are set to 1. `clknrst_cfg.trn_log_enabled` is set to 1 if `trn_log_enabled` is set to 1. `cvxif_cfg.cov_model_enabled` is set to 1 if `cov_model_enabled` is set to 1. + + + + + + + + + + + + + + + + + + + + + + + + + + +
signal + Description +
enabled + is set to 1, the environment is enabled and the components within the environment can be instantiated, built, and connected. +
is_active + This is set to UVM_PASSIVE. +
scoreboarding_enabled + It enables the scoreboard and predictor in the environment class. +
cov_model_enabled + It enables the coverage collection for environment and cvxif_agent. +
trn_log_enabled + It enables the trace log for the clk_rst_agent +
+ +### uvme_cva6_cntxt_c + +The class uvme_cva6_cntxt_c is an object that encapsulates all state variables for CVA6 environment (`uvme_cva6_env_c`) components. It inherits from the `uvm_object` base class.It also contains two events, `sample_cfg_e` and `sample_cntxt_e`, that can be used to synchronize the sampling of configuration and context information. + +### uvme_cva6_vsqr_c + +This class extends from the `uvm_sequencer` base class. It also has two sequencer handles, "clknrst_sequencer" and "cvxif_sequencer" of the types `uvma_clknrst_sqr_c` and `uvma_cvxif_sqr_c`, respectively. This class is used to start the virtual sequence. + +### uvme_cva6_reset_vseq_c + +This class `uvme_cva6_reset_vseq_c` extends a class called `uvme_cva6_base_vseq_c`. The purpose of this sequence is to start the system clock and issue the initial reset pulse to the Device Under Test (DUT). The class has three random variables, `num_clk_before_reset`, `rst_deassert_period`, and `post_rst_wait`. These variables are used to specify the number of clock cycles between the start of the clock and the reset assert.The class has a default constructor and a virtual task called "body" which is responsible for starting the clock, waiting for a specified amount of time, and then resetting the DUT. + +## Clock & Reset Agent + + This agent controls the clock and reset signal of the CVA6 core. + +### uvma_clknrst_if + +The `uvma_clknrst_if` interface has two logic signals, `clk` and `reset_n`. The `clk` signal represents the system clock, while the `reset_n` signal is the active-low reset signal.The interface includes an initial block that contains a forever loop that generates the clock signal, based on the value of `clk_active` and `clk_period`. If `clk_active` is set to 1 and `clk_period` is 0, the function will raise a fatal error. The interface also includes three functions: set_period, which sets the value of `clk_period`; start_clk, which sets `clk_active` to 1; and stop_clk, which sets `clk_active` to 0. + + + + + + + + + + + + + + +
signal + Description +
clk + Controls the Clock fed to the design under test. +
reset_n + Control the reset state of the design under test. +
+ +### uvma_clknrst_uvm_objects + +The uvm_objects `uvma_clknrst_cfg_c` , `uvma_clknrst_cntxt_c` contain the configuration and context information of the uvma_clknrst_agent. + +### uvma_clknrst_seq_item_c + +The class represents an object created by Clock & Reset agent sequences that extend the `uvma_clknrst_seq_base_c` class. + +The class contains several randomized variables: + +* `action` is an enumerated variable of type "uvma_clknrst_seq_item_action_enum" that represents the operation to perform (e.g. start clock, stop clock, assert reset, de-assert reset). +* `initial_value` is an enumerated variable of type "uvma_clknrst_seq_item_initial_value_enum" that represents the initial value of the signals (if starting or asserting). +* `clk_period` is an unsigned 32-bit integer variable representing the period of the clock signal. +* `rst_deassert_period` is an unsigned 32-bit integer variable representing the amount of time (in picoseconds) after which to de-assert reset. +* The class also includes a constraint "default_cons" which sets the default values for `clk_period` to 0 and `rst_deassert_period` to a value defined by `uvma_clknrst_default_rst_deassert_period` + +The class has a default constructor which calls the superclass constructor. + +### uvma_clknrst_Sequence + +It consists of two main sequences: `uvma_clknrst_stop_clk_seq_c` and `uvma_clknrst_restart_clk_seq_c`. + +* The `uvma_clknrst_stop_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_STOP_CLK` and start and finish the item. + +* The `uvma_clknrst_restart_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_RESTART_CLK` and start and finish the item. + +### uvma_clknrst_drv_c + +This class `uvma_clknrst_drv_c` is used for driving the interface of the clknrst agent. It get reqs from the sequence item port and calls the `drv_req` task. The `drv_req` task drives the virtual interface's (`cntxt.vif`) signals using req's contents. And then call the write method for the analysis port to send the req transaction to the coverage model. + +### uvma_clknrst_mon_c + +This class `uvma_clknrst_mon_c` is used for monitoring the virtual interface of the Clock & Reset agent. The class extends the `uvm_monitor` class and contains objects for configuration (cfg) and context (cntxt), as well as an analysis port (ap) for transaction analysis.The run_phase() task in the `uvma_clknrst_mon_c` class is responsible for overseeing the monitoring process of the Clock and Reset virtual interface. It does this by executing the monitor_clk() and monitor_reset() tasks in parallel forks. + +### uvma_clknrst_cov_model_c + +This class `uvma_clknrst_cov_model_c` extends from the `uvm_component` base class. The overall functionality of this class is to provide the coverage model for the clknrst_agent. It contains objects for configuration, context, monitor transaction, and sequence item, as well as two analysis FIFOs for holding transactions coming from the monitor and sequence item respectively. This section is in progress. + +### uvma_clknrst_agent_c + + This class `uvma_clknrst_agent_c` extends from `uvm_agent` base class. This class encapsulates ,builds and connects all the other components for driving and monitoring a Clock & reset interface. This class gets the `cfg` , `cntxt` using configuration database get method. It creates a driver,monitor,cov_model and sequencer. This class connects the driver with a sequencer. + +## Cvxif Agent + +Cv-xif agent supports custom instructions. Upon receiving the issue request it drives the response one clock cycle after the issue request. + +### uvma_cvxif_intf + +The interface includes inputs for clock and reset_n signal, as well as two data input/output called `cvxif_req_i` and `cvxif_resp_o`. It includes a clocking block for the monitor `monitor_cb` to sample the `cvxif_req_i` and `cvxif_resp_o` signal at the rising edge of the clock. + + + + + + + + + + + + + +
Enum Variable + Description +
Cvxif_req_i + The request is send to get a response +
Cvxif_resp_o + The response is generated according to the request. +
+ +### uvma_cvxif_uvm_objects + +There are two uvm_objects `uvma_cvxif_cfg_c` and `uvma_cvxif_cntxt_c`. `uvma_cvxif_cfg_c` encapsulates all the parameters for creating ,connecting and running the `uvma_cvxif_agent_c` agent . `uvma_cvxif_cntxt_c` confine all the state variables for all the CVXIF agent components. + +### uvma_cvxif_Sequence_items + +Cvxif agent has two sequence items one `uvma_cvxif_req_item_c`and `uvma_cvxif_resp_item_c` for the request and response transaction. + +### uvma_cvxif_sqr_c + +`uvma_cvxif_sqr_c` class extends from `uvm_sequencer` base class. It is a typical sequencer. This class instantiates a FIFO to receive the `uvma_cvxif_req_item_c`. + +### uvma_cvxif_sequences + +* `uvma_cvxif_base_seq_c` class extends from `uvm_sequence` . This class simply implements a decode function that checks whether the instructions are legal or illegal. + +* `uvma_cvxif_seq_c` class extends from `uvma_cvxif_base_seq_c` class. This class gets the `uvma_cvxif_req_item_c` from the FIFO in sequencer using the p_sequencer handle. In this sequence class, we send the response according to the request item received . If we receive an instruction from the req_item that is illegal then we drive zero's on the response signals. Otherwise we drive response accordingly. + +### uvma_cvxif_drv_c + +This class `uvma_cvxif_drv_c` extends from the `uvm_driver` class. This class has several tasks that perform different actions such as generating a random ready signal, getting response_item, driving an issue response to the `VIF` , driving results in order and out of order fashion, and de-asserting signals. + +### uvma_cvxif_mon_c + +`uvma_cvxif_mon_c` class extends from the `uvm_monitor` . It monitors the virtual interface `vif`. It monitors transaction requests and responses, and sends transaction requests to `uvma_cvxif_sqr_c` and responses to the coverage model. It has several fields, including objects for configuration and context, and analysis ports for transaction requests and responses. + +### uvma_cvxif_cov_model_c + +`uvma_cvxif_cov_model_c` is derived from the `uvm_component` class. This class defines various objects and covergroups with different coverpoints, and it also uses the UVM library to sample these coverpoints and measure coverage.The main purpose of this class is to measure the functional coverage of a specific interface in the design and ensure that it has been fully tested. + +### uvma_cvxif_agent_c + +`uvma_cvxif_agent_c` class extends from `uvm_agent` class. This class represents an agent that is responsible for the test execution and communication between the virtual interface (VIF) and the testbench components. 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zi_Pg>kdiNayu;k4R<|1gLgDf@D-6XSoHVe9??B3Vl7D%c52V%SqBL@``}K#=e1M9! zPBRy^6uaIpFTsoBd5W<^1UPTz=Ih41)5Fa;AY>)qtxk?G0QkoVP%+0=Z&f{oNUiMF zGs4U-uVLR&VuoRN0FrGywM--=$?iDZ9Jk#lY+dqyn%4$6*#XQJ!9dxRH(4f^z;9nJ zVE^8bZzK^I0F12hio_=E5z6cBj)?ew~_NzC9n4E8`i z9E5PPRsf$K8xM{bxN(S_25~s=jeim@I#Iw!v>i2ydZ>-=#yE5j%8Ov(v*2)|r&TvH z;CUb?^CG6{xCt8#Y4-%`czlM2nkq@ zF4hII9$3aLC?SLy{RX3Wb{B6EjDq1Kbp2;UU>U&_8?OfG{|L+`>_Nx>>L(P@uP)9C z77gq>B}k57u+Qw^@qlZ9WZ^%%#{Z{Jgg?KUe_3e$Gj4&!0ekiXntv~UJ$*1G|H-KS zPkiD(nRZ1w03Cq2ioRME|6x@B_7h(0f1fT0`oSFI{(X-B_ve@{>}o;BU#(cWzmNIf z4E^tf!a4@Qg3hqaR?C-nbaaF=)bc5p>=m1={>=154X|$%2mWrZ7qeFw#_V^1$~}fK zY(Rn@1zR&6yjQt2Q0?0HSdd)GK$&l!(Sx5Fe~5|kusZ-$%i(ss{j(DW)1%0Gt3O8! zO{X>VZ^qld5DM6jSL>Y4`+s>ee*dqg1@`L3)!i!o-9C^7`sZtJQ$u@2k>+aU^ZtF) z)q)adg;xImpR3*mR_s3;6wK&9jQrINXa#z)zk{rW&((T*`24S3x>`>$S9W3kukpJ2 q^S?7*|JJrW`|rL3z~k$eXo>B(KUczCd4Vy4Nr}sg<-O4R_+J3)L}nuZ literal 0 HcmV?d00001 From 33a848ff6730e43e3d7c59a8d8d083b2f0ec730c Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 31 Jan 2023 14:32:46 +0100 Subject: [PATCH 011/183] cva6/sim/Makefile: Use VCS_HOME env variable Signed-off-by: Nils Wistoff --- cva6/sim/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index bcceaee51..4bd31a3e9 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -158,9 +158,9 @@ export DV_OVPM_HOME = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/imperas export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design -ALL_UVM_FLAGS = -lca -sverilog +incdir+/opt/synopsys/vcs-mx/O-2018.09-SP1-1/etc/uvm/src \ - /opt/synopsys/vcs-mx/O-2018.09-SP1-1/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \ - -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+/opt/synopsys/vcs-mx/O-2018.09-SP1-1/etc/uvm/src \ +ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ + $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \ + -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \ +incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme +incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt \ $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) From a16b62790905246686529dcc698703d71195cc8f Mon Sep 17 00:00:00 2001 From: Yannick Casamatta Date: Wed, 1 Feb 2023 21:01:51 +0100 Subject: [PATCH 012/183] Update spike log parsing Spike output have been updated in latest releases register index is now left align with space padding --- cva6/sim/cva6_spike_log_to_trace_csv.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cva6/sim/cva6_spike_log_to_trace_csv.py b/cva6/sim/cva6_spike_log_to_trace_csv.py index 057364020..486c8d975 100644 --- a/cva6/sim/cva6_spike_log_to_trace_csv.py +++ b/cva6/sim/cva6_spike_log_to_trace_csv.py @@ -28,7 +28,7 @@ from riscv_trace_csv import * from lib import * RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P\d) 0x(?P[a-f0-9]+?) " \ - "\((?P.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P[xf]\s*\d*?) 0x(?P[a-f0-9]+)") + "\((?P.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P[xf]\s*\d*?)\s*0x(?P[a-f0-9]+)") CORE_RE = re.compile( r"core\s+\d+:\s+0x(?P[a-f0-9]+?) \(0x(?P.*?)\) (?P.*?)$") From aa4f0cae20a8afe003c499808cdf6f9deea67e55 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Thu, 2 Feb 2023 10:31:43 +0100 Subject: [PATCH 013/183] ISACOV: FIX #1582 Signed-off-by: Ayoub Jalali --- lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv | 15 ++------------- lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv | 4 ++-- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv index c790c0178..2347992fb 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv @@ -333,11 +333,6 @@ function void uvma_isacov_instr_c::set_valid_flags(); return; end - if (itype == CSRI_TYPE) begin - rd_valid = 1; - return; - end - endfunction : set_valid_flags @@ -392,7 +387,7 @@ function int uvma_isacov_instr_c::get_field_imm(); if (this.itype == CIW_TYPE) begin return (dasm_rvc_addi4spn_imm(instr) >> 2); // Shift 2 because [9:2] to [7:0] end - if (this.itype == CS_TYPE) begin + if (this.itype == CL_TYPE) begin return (dasm_rvc_lw_imm(instr) >> 2); // Shift 2 because [6:2] to [4:0] end if (this.itype == CB_TYPE) begin @@ -433,13 +428,7 @@ function int uvma_isacov_instr_c::get_field_rd(); // TODO:ropeders is CA handled properly? // TODO:ropeders call dpi_dasm from here, instead of elsewhere? - if (itype inside {CA_TYPE, CB_TYPE}) begin - return rd[2:0]; - end else if (itype inside {CIW_TYPE, CL_TYPE}) begin - return rs2[2:0]; - end else begin - return rd; - end + return (itype inside {CA_TYPE, CL_TYPE, CIW_TYPE, CB_TYPE}) ? rd[2:0] : rd; endfunction : get_field_rd diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv index 912199318..d32f69e8f 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv @@ -165,8 +165,8 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL if (mon_trn.instr.ext == C_EXT) begin mon_trn.instr.rs1 = dasm_rvc_rs1(instr); mon_trn.instr.rs2 = dasm_rvc_rs2(instr); - mon_trn.instr.rd = dasm_rd(instr); - mon_trn.instr.c_rdrs1 = dasm_rd(instr); + mon_trn.instr.rd = dasm_rvc_rd(instr); + mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr); mon_trn.instr.c_rs1s = dasm_rvc_rs1s(instr); mon_trn.instr.c_rs2s = dasm_rvc_rs2s(instr); end From 2c48945b869762e9570ba4815342562a0bd87057 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Fri, 3 Feb 2023 11:32:51 +0100 Subject: [PATCH 014/183] CVXIF: Verification plans Signed-off-by: Ayoub Jalali --- cva6/docs/VerifPlans/CVXIF/VP_IP000.pck | 998 ++++++++++++++++++++ cva6/docs/VerifPlans/CVXIF/VP_IP001.pck | 418 ++++++++ cva6/docs/VerifPlans/CVXIF/VP_IP002.pck | 860 +++++++++++++++++ cva6/docs/VerifPlans/CVXIF/runme.sh | 34 + cva6/docs/VerifPlans/source/dvplan_CVXIF.md | 556 +++++++++++ cva6/docs/VerifPlans/source/index.rst | 1 + 6 files changed, 2867 insertions(+) create mode 100644 cva6/docs/VerifPlans/CVXIF/VP_IP000.pck create mode 100644 cva6/docs/VerifPlans/CVXIF/VP_IP001.pck create mode 100644 cva6/docs/VerifPlans/CVXIF/VP_IP002.pck create mode 100644 cva6/docs/VerifPlans/CVXIF/runme.sh create mode 100644 cva6/docs/VerifPlans/source/dvplan_CVXIF.md diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck new file mode 100644 index 000000000..575c69110 --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP000.pck @@ -0,0 +1,998 @@ +(VIssue Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I9 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I0 +sVwid_order +p12 +I0 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_issue_req signals stable +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F000_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F000_S000_I000 +p34 +sVdescription +p35 +VThe \u201cinstr\u201d and \u201cmode\u201d signals remain stable during an Issue request transaction. +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VCheck that \u201cmode\u201d and \u201cinstr\u201d are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process) +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I4 +sVtest_type +p49 +I3 +sVcov_method +p50 +I2 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_mode signal value +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I2 +sg8 +g67 +sg23 +VVP_CVXIF_F000_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F000_S001_I000 +p79 +sg35 +VWhen issue transaction starts, instruction and current CPU mode are provided +p80 +sg37 +g38 +sg39 +VCheck that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +a(V001 +p87 +g1 +(g29 +g3 +Ntp88 +Rp89 +(dp90 +g8 +V001 +p91 +sg23 +VVP_CVXIF_F000_S001_I001 +p92 +sg35 +VCheck \u201cmode\u201d signal values. +p93 +sg37 +g38 +sg39 +VCheck that mode take a value that the CPU supports : Privilege level (2\u2019b00 = User, 2\u2019b01 = Supervisor, 2\u2019b10 = Reserved,\u000a 2\u2019b11 = Machine). +p94 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp95 +sg15 +(lp96 +sg57 +(lp97 +sg13 +(dp98 +g60 +I0 +ssbtp99 +asg62 +(lp100 +sg57 +(lp101 +sg13 +(dp102 +sbtp103 +a(V002_rs_valid signal transition order +p104 +g1 +(g18 +g3 +Ntp105 +Rp106 +(dp107 +g22 +I1 +sg8 +g104 +sg23 +VVP_CVXIF_F000_S002 +p108 +sg25 +(dp109 +sg12 +I2 +sg15 +(lp110 +(V000 +p111 +g1 +(g29 +g3 +Ntp112 +Rp113 +(dp114 +g8 +V000 +p115 +sg23 +VVP_CVXIF_F000_S002_I000 +p116 +sg35 +VDuring a transaction, each bit of \u201crs_valid\u201d can transition from 0 to 1 but are not allowed to transition back to 0. +p117 +sg37 +g38 +sg39 +VFor issue transaction which lasts more than one cycle, check that asserted \u201crs_valid\u201d signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] \u2192 0 cannot happen) +p118 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp119 +sg15 +(lp120 +sg57 +(lp121 +sg13 +(dp122 +g60 +I0 +ssbtp123 +asg62 +(lp124 +sg57 +(lp125 +sg13 +(dp126 +sbtp127 +a(V003_rs signal value +p128 +g1 +(g18 +g3 +Ntp129 +Rp130 +(dp131 +g22 +I3 +sg8 +g128 +sg23 +VVP_CVXIF_F000_S003 +p132 +sg25 +(dp133 +sg12 +I3 +sg15 +(lp134 +(V000 +p135 +g1 +(g29 +g3 +Ntp136 +Rp137 +(dp138 +g8 +V000 +p139 +sg23 +VVP_CVXIF_F000_S003_I000 +p140 +sg35 +VIf XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3). +p141 +sg37 +g38 +sg39 +VFor every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file. +p142 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp143 +sg15 +(lp144 +sg57 +(lp145 +sg13 +(dp146 +g60 +I0 +ssbtp147 +a(V001 +p148 +g1 +(g29 +g3 +Ntp149 +Rp150 +(dp151 +g8 +V001 +p152 +sg23 +VVP_CVXIF_F000_S003_I001 +p153 +sg35 +Vrs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid. +p154 +sg37 +g38 +sg39 +VCheck that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1. +p155 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I-1 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp156 +sg15 +(lp157 +sg57 +(lp158 +sg13 +(dp159 +g60 +I0 +ssbtp160 +a(V002 +p161 +g1 +(g29 +g3 +Ntp162 +Rp163 +(dp164 +g8 +V002 +p165 +sg23 +VVP_CVXIF_F000_S003_I002 +p166 +sg35 +VIf XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal. +p167 +sg37 +g38 +sg39 +VFor every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs. +p168 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp169 +sg15 +(lp170 +sg57 +(lp171 +sg13 +(dp172 +g60 +I0 +ssbtp173 +asg62 +(lp174 +sg57 +(lp175 +sg13 +(dp176 +sbtp177 +a(V004_Default value for unaccepted instruction +p178 +g1 +(g18 +g3 +Ntp179 +Rp180 +(dp181 +g22 +I1 +sg8 +g178 +sg23 +VVP_CVXIF_F000_S004 +p182 +sg25 +(dp183 +sg12 +I4 +sg15 +(lp184 +(V000 +p185 +g1 +(g29 +g3 +Ntp186 +Rp187 +(dp188 +g8 +V000 +p189 +sg23 +VVP_CVXIF_F000_S004_I000 +p190 +sg35 +VIf accept == 0 :\u000aWriteback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0. +p191 +sg37 +g38 +sg39 +VCheck that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0. +p192 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp193 +sg15 +(lp194 +sg57 +(lp195 +sg13 +(dp196 +g60 +I0 +ssbtp197 +asg62 +(lp198 +sg57 +(lp199 +sg13 +(dp200 +sbtp201 +a(V005_Illegal Instruction causes +p202 +g1 +(g18 +g3 +Ntp203 +Rp204 +(dp205 +g22 +I1 +sg8 +g202 +sg23 +VVP_CVXIF_F000_S005 +p206 +sg25 +(dp207 +sg12 +I5 +sg15 +(lp208 +(V000 +p209 +g1 +(g29 +g3 +Ntp210 +Rp211 +(dp212 +g8 +V000 +p213 +sg23 +VVP_CVXIF_F000_S005_I000 +p214 +sg35 +VThe CPU shall cause an illegal instruction if:\u000a- an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1)\u000a- neither to be valid by the CPU nor accepted by the coprocessor (accept = 0) +p215 +sg37 +g38 +sg39 +V- CPU causes illegal instruction for instruction accepted by the core and the coprocessor.\u000a- CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU +p216 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp217 +sg15 +(lp218 +sg57 +(lp219 +sg13 +(dp220 +g60 +I0 +ssbtp221 +asg62 +(lp222 +sg57 +(lp223 +sg13 +(dp224 +sbtp225 +a(V006_issue uniquness +p226 +g1 +(g18 +g3 +Ntp227 +Rp228 +(dp229 +g22 +I1 +sg8 +g226 +sg23 +VVP_CVXIF_F000_S006 +p230 +sg25 +(dp231 +sg12 +I6 +sg15 +(lp232 +(V000 +p233 +g1 +(g29 +g3 +Ntp234 +Rp235 +(dp236 +g8 +V000 +p237 +sg23 +VVP_CVXIF_F000_S006_I000 +p238 +sg35 +VCheck for issue id validity. +p239 +sg37 +g38 +sg39 +VCheck that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed). +p240 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I3 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp241 +sg15 +(lp242 +sg57 +(lp243 +sg13 +(dp244 +g60 +I0 +ssbtp245 +asg62 +(lp246 +sg57 +(lp247 +sg13 +(dp248 +sbtp249 +a(V007_coprocessor decoding +p250 +g1 +(g18 +g3 +Ntp251 +Rp252 +(dp253 +g22 +I1 +sg8 +g250 +sg23 +VVP_CVXIF_F000_S007 +p254 +sg25 +(dp255 +sg12 +I7 +sg15 +(lp256 +(V000 +p257 +g1 +(g29 +g3 +Ntp258 +Rp259 +(dp260 +g8 +V000 +p261 +sg23 +VVP_CVXIF_F000_S007_I000 +p262 +sg35 +VAccept = 1 if: \u000a- coprocessor can handle the instruction based on decoding \u201cinstr\u201dand "mode".\u000a- \u201cissue_valid\u201d == 1 and required bit(s) of \u201crs_valid\u201d are 1. +p263 +sg37 +g38 +sg39 +VTo be checked in coprocessor. +p264 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp265 +sg15 +(lp266 +sg57 +(lp267 +sg13 +(dp268 +g60 +I0 +ssbtp269 +asg62 +(lp270 +sg57 +(lp271 +sg13 +(dp272 +sbtp273 +a(V008_Transaction definition +p274 +g1 +(g18 +g3 +Ntp275 +Rp276 +(dp277 +g22 +I1 +sg8 +g274 +sg23 +VVP_CVXIF_F000_S008 +p278 +sg25 +(dp279 +sg12 +I8 +sg15 +(lp280 +(V000 +p281 +g1 +(g29 +g3 +Ntp282 +Rp283 +(dp284 +g8 +V000 +p285 +sg23 +VVP_CVXIF_F000_S008_I000 +p286 +sg35 +V\u201cissue_resp\u201d signals and \u201cissue_req\u201d signals are accepted when \u201cissue_valid\u201d == \u201cissue_ready\u201d == 1\u000a\u201cissue_resp\u201d is valid when "valid==ready==1".\u000a\u201cissue_req\u201d is valid when "valid==1" +p287 +sg37 +g38 +sg39 +VThe definition of a transaction. \u000aNot to be verified. +p288 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp289 +sg15 +(lp290 +sg57 +(lp291 +sg13 +(dp292 +g60 +I0 +ssbtp293 +asg62 +(lp294 +sg57 +(lp295 +sg13 +(dp296 +sbtp297 +asVrfu_list_0 +p298 +(lp299 +sg62 +(lp300 +sVvptool_gitrev +p301 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p302 +sVio_fmt_gitrev +p303 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p304 +sVconfig_gitrev +p305 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p306 +sVymlcfg_gitrev +p307 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p308 +sbtp309 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck new file mode 100644 index 000000000..1a42a8fd3 --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP001.pck @@ -0,0 +1,418 @@ +(VCommit Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I4 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I1 +sVwid_order +p12 +I1 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_commit_valid pulse +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F001_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F001_S000_I000 +p34 +sVdescription +p35 +VThe \u201ccommit_valid\u201d == 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not). +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VFor every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ). +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I4 +sVtest_type +p49 +I3 +sVcov_method +p50 +I2 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_commit transaction uniquness +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I1 +sg8 +g67 +sg23 +VVP_CVXIF_F001_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F001_S001_I000 +p79 +sg35 +VThere is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted). +p80 +sg37 +g38 +sg39 +VCheck that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed). +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I1 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +asg62 +(lp87 +sg57 +(lp88 +sg13 +(dp89 +sbtp90 +a(V002_commit transaction for every issue transaction +p91 +g1 +(g18 +g3 +Ntp92 +Rp93 +(dp94 +g22 +I1 +sg8 +g91 +sg23 +VVP_CVXIF_F001_S002 +p95 +sg25 +(dp96 +sg12 +I2 +sg15 +(lp97 +(V000 +p98 +g1 +(g29 +g3 +Ntp99 +Rp100 +(dp101 +g8 +V000 +p102 +sg23 +VVP_CVXIF_F001_S002_I000 +p103 +sg35 +V- The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction.\u000a- For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_valid is 1 and commit_kill is 0) or that the instruction must be killed (commit_valid is 1 and commit_kill is 1). +p104 +sg37 +g38 +sg39 +VCheck that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction. +p105 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp106 +sg15 +(lp107 +sg57 +(lp108 +sg13 +(dp109 +g60 +I0 +ssbtp110 +asg62 +(lp111 +sg57 +(lp112 +sg13 +(dp113 +sbtp114 +a(V003_Transaction definition +p115 +g1 +(g18 +g3 +Ntp116 +Rp117 +(dp118 +g22 +I1 +sg8 +g115 +sg23 +VVP_CVXIF_F001_S003 +p119 +sg25 +(dp120 +sg12 +I3 +sg15 +(lp121 +(V000 +p122 +g1 +(g29 +g3 +Ntp123 +Rp124 +(dp125 +g8 +V000 +p126 +sg23 +VVP_CVXIF_F001_S003_I000 +p127 +sg35 +VThe signals in commit are valid when commit_valid is 1. +p128 +sg37 +g38 +sg39 +VThe definition of a transaction.\u000aNot to be verified. +p129 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I-1 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp130 +sg15 +(lp131 +sg57 +(lp132 +sg13 +(dp133 +g60 +I0 +ssbtp134 +asg62 +(lp135 +sg57 +(lp136 +sg13 +(dp137 +sbtp138 +asVrfu_list_0 +p139 +(lp140 +sg62 +(lp141 +sVvptool_gitrev +p142 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p143 +sVio_fmt_gitrev +p144 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p145 +sVconfig_gitrev +p146 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p147 +sVymlcfg_gitrev +p148 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p149 +sbtp150 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck b/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck new file mode 100644 index 000000000..7211f1b9e --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/VP_IP002.pck @@ -0,0 +1,860 @@ +(VResult Interface +p0 +ccopy_reg +_reconstructor +p1 +(cvp_pack +Ip +p2 +c__builtin__ +object +p3 +Ntp4 +Rp5 +(dp6 +Vprop_count +p7 +I8 +sVname +p8 +g0 +sVprop_list +p9 +(dp10 +sVip_num +p11 +I2 +sVwid_order +p12 +I2 +sVrfu_dict +p13 +(dp14 +sVrfu_list +p15 +(lp16 +(V000_no speculative result transaction +p17 +g1 +(cvp_pack +Prop +p18 +g3 +Ntp19 +Rp20 +(dp21 +Vitem_count +p22 +I1 +sg8 +g17 +sVtag +p23 +VVP_CVXIF_F002_S000 +p24 +sVitem_list +p25 +(dp26 +sg12 +I0 +sg15 +(lp27 +(V000 +p28 +g1 +(cvp_pack +Item +p29 +g3 +Ntp30 +Rp31 +(dp32 +g8 +V000 +p33 +sg23 +VVP_CVXIF_F002_S000_I000 +p34 +sVdescription +p35 +VA coprocessor is not allowed to perform speculative result transactions. +p36 +sVpurpose +p37 +V +p38 +sVverif_goals +p39 +VThere is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0). +p40 +sVcoverage_loc +p41 +g38 +sVref_mode +p42 +Vpage +p43 +sVref_page +p44 +g38 +sVref_section +p45 +g38 +sVref_viewer +p46 +Vfirefox +p47 +sVpfc +p48 +I11 +sVtest_type +p49 +I10 +sVcov_method +p50 +I10 +sVcores +p51 +I56 +sVcomments +p52 +g38 +sVstatus +p53 +g38 +sVsimu_target_list +p54 +(lp55 +sg15 +(lp56 +sVrfu_list_2 +p57 +(lp58 +sg13 +(dp59 +Vlock_status +p60 +I0 +ssbtp61 +asVrfu_list_1 +p62 +(lp63 +sg57 +(lp64 +sg13 +(dp65 +sbtp66 +a(V001_out of order result transaction +p67 +g1 +(g18 +g3 +Ntp68 +Rp69 +(dp70 +g22 +I1 +sg8 +g67 +sg23 +VVP_CVXIF_F002_S001 +p71 +sg25 +(dp72 +sg12 +I1 +sg15 +(lp73 +(V000 +p74 +g1 +(g29 +g3 +Ntp75 +Rp76 +(dp77 +g8 +V000 +p78 +sg23 +VVP_CVXIF_F002_S001_I000 +p79 +sg35 +VA coprocessor is allowed to provide results to the core in an out of order fashion. +p80 +sg37 +g38 +sg39 +VCheck that the CPU is able to receive the result in an out of order fashion. +p81 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp82 +sg15 +(lp83 +sg57 +(lp84 +sg13 +(dp85 +g60 +I0 +ssbtp86 +asg62 +(lp87 +sg57 +(lp88 +sg13 +(dp89 +sbtp90 +a(V002_result transaction uniquness +p91 +g1 +(g18 +g3 +Ntp92 +Rp93 +(dp94 +g22 +I1 +sg8 +g91 +sg23 +VVP_CVXIF_F002_S002 +p95 +sg25 +(dp96 +sg12 +I2 +sg15 +(lp97 +(V000 +p98 +g1 +(g29 +g3 +Ntp99 +Rp100 +(dp101 +g8 +V000 +p102 +sg23 +VVP_CVXIF_F002_S002_I000 +p103 +sg35 +VEach accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU\u2019s register file). +p104 +sg37 +g38 +sg39 +VThere is an unique result transaction for every accepted and commit instruction. +p105 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I11 +sg49 +I10 +sg50 +I10 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp106 +sg15 +(lp107 +sg57 +(lp108 +sg13 +(dp109 +g60 +I0 +ssbtp110 +asg62 +(lp111 +sg57 +(lp112 +sg13 +(dp113 +sbtp114 +a(V003_result packet stability +p115 +g1 +(g18 +g3 +Ntp116 +Rp117 +(dp118 +g22 +I1 +sg8 +g115 +sg23 +VVP_CVXIF_F002_S003 +p119 +sg25 +(dp120 +sg12 +I3 +sg15 +(lp121 +(V000 +p122 +g1 +(g29 +g3 +Ntp123 +Rp124 +(dp125 +g8 +V000 +p126 +sg23 +VVP_CVXIF_F002_S003_I000 +p127 +sg35 +VThe signals in result shall remain stable during a result transaction (except data ...) +p128 +sg37 +g38 +sg39 +VCheck that result signals (except data) are stable during result transaction (result_valid==1 jusqu'à valid==ready ==1) +p129 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp130 +sg15 +(lp131 +sg57 +(lp132 +sg13 +(dp133 +g60 +I0 +ssbtp134 +asg62 +(lp135 +sg57 +(lp136 +sg13 +(dp137 +sbtp138 +a(V004_data stability +p139 +g1 +(g18 +g3 +Ntp140 +Rp141 +(dp142 +g22 +I1 +sg8 +g139 +sg23 +VVP_CVXIF_F002_S004 +p143 +sg25 +(dp144 +sg12 +I4 +sg15 +(lp145 +(V000 +p146 +g1 +(g29 +g3 +Ntp147 +Rp148 +(dp149 +g8 +V000 +p150 +sg23 +VVP_CVXIF_F002_S004_I000 +p151 +sg35 +VData is only required to remain stable during result transactions in which "we" is not 0. +p152 +sg37 +g38 +sg39 +VCheck that "data" remains stable when we==1. +p153 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp154 +sg15 +(lp155 +sg57 +(lp156 +sg13 +(dp157 +g60 +I0 +ssbtp158 +asg62 +(lp159 +sg57 +(lp160 +sg13 +(dp161 +sbtp162 +a(V005_synchronous exception +p163 +g1 +(g18 +g3 +Ntp164 +Rp165 +(dp166 +g22 +I3 +sg8 +g163 +sg23 +VVP_CVXIF_F002_S005 +p167 +sg25 +(dp168 +sg12 +I5 +sg15 +(lp169 +(V000 +p170 +g1 +(g29 +g3 +Ntp171 +Rp172 +(dp173 +g8 +V000 +p174 +sg23 +VVP_CVXIF_F002_S005_I000 +p175 +sg35 +VThe exc is used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed. +p176 +sg37 +g38 +sg39 +VCheck that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed. +p177 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I3 +sg49 +I3 +sg50 +I1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp178 +sg15 +(lp179 +sg57 +(lp180 +sg13 +(dp181 +g60 +I0 +ssbtp182 +a(V001 +p183 +g1 +(g29 +g3 +Ntp184 +Rp185 +(dp186 +g8 +V001 +p187 +sg23 +VVP_CVXIF_F002_S005_I001 +p188 +sg35 +Vexccode provides the least significant bits of the exception code bitfield of the mcause CSR. +p189 +sg37 +g38 +sg39 +VCheck that exccode signal is the value of the mcause CSR when exc == 1. +p190 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I-1 +sg49 +I-1 +sg50 +I-1 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp191 +sg15 +(lp192 +sg57 +(lp193 +sg13 +(dp194 +g60 +I0 +ssbtp195 +a(V002 +p196 +g1 +(g29 +g3 +Ntp197 +Rp198 +(dp199 +g8 +V002 +p200 +sg23 +VVP_CVXIF_F002_S005_I002 +p201 +sg35 +V "we" shall be driven to 0 by the coprocessor for synchronous exceptions. +p202 +sg37 +g38 +sg39 +VCheck that "we" signal == 0 when exc == 1. +p203 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I-1 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp204 +sg15 +(lp205 +sg57 +(lp206 +sg13 +(dp207 +g60 +I0 +ssbtp208 +asg62 +(lp209 +sg57 +(lp210 +sg13 +(dp211 +sbtp212 +a(V006_"we" value when dualwrite +p213 +g1 +(g18 +g3 +Ntp214 +Rp215 +(dp216 +g22 +I1 +sg8 +g213 +sg23 +VVP_CVXIF_F002_S006 +p217 +sg25 +(dp218 +sg12 +I6 +sg15 +(lp219 +(V000 +p220 +g1 +(g29 +g3 +Ntp221 +Rp222 +(dp223 +g8 +V000 +p224 +sg23 +VVP_CVXIF_F002_S006_I000 +p225 +sg35 +Vwe is 2 bits wide when XLEN` = 32 and X_RFW_WIDTH = 64, and 1 bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to be 1 if we[0] is 1 as well (i.e. for dual writeback). +p226 +sg37 +g38 +sg39 +VFor dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1. +p227 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp228 +sg15 +(lp229 +sg57 +(lp230 +sg13 +(dp231 +g60 +I0 +ssbtp232 +asg62 +(lp233 +sg57 +(lp234 +sg13 +(dp235 +sbtp236 +a(V007_proper result transaction +p237 +g1 +(g18 +g3 +Ntp238 +Rp239 +(dp240 +g22 +I1 +sg8 +g237 +sg23 +VVP_CVXIF_F002_S007 +p241 +sg25 +(dp242 +sg12 +I7 +sg15 +(lp243 +(V000 +p244 +g1 +(g29 +g3 +Ntp245 +Rp246 +(dp247 +g8 +V000 +p248 +sg23 +VVP_CVXIF_F002_S007_I000 +p249 +sg35 +VResult transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1. +p250 +sg37 +g38 +sg39 +VCheck that result transaction ends properly. +p251 +sg41 +g38 +sg42 +g43 +sg44 +g38 +sg45 +g38 +sg46 +g47 +sg48 +I4 +sg49 +I3 +sg50 +I2 +sg51 +I56 +sg52 +g38 +sg53 +g38 +sg54 +(lp252 +sg15 +(lp253 +sg57 +(lp254 +sg13 +(dp255 +g60 +I0 +ssbtp256 +asg62 +(lp257 +sg57 +(lp258 +sg13 +(dp259 +sbtp260 +asVrfu_list_0 +p261 +(lp262 +sg62 +(lp263 +sVvptool_gitrev +p264 +V$Id: a782de3eec3de5ff99661fb165c09f541b4228d0 $ +p265 +sVio_fmt_gitrev +p266 +V$Id: 2f6f9e7bc800d8b831382463dc706473c6c6ad8c $ +p267 +sVconfig_gitrev +p268 +V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ +p269 +sVymlcfg_gitrev +p270 +V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ +p271 +sbtp272 +. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/CVXIF/runme.sh b/cva6/docs/VerifPlans/CVXIF/runme.sh new file mode 100644 index 000000000..f1be65625 --- /dev/null +++ b/cva6/docs/VerifPlans/CVXIF/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="CVXIF" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="CVXIF" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue diff --git a/cva6/docs/VerifPlans/source/dvplan_CVXIF.md b/cva6/docs/VerifPlans/source/dvplan_CVXIF.md new file mode 100644 index 000000000..24d31a54e --- /dev/null +++ b/cva6/docs/VerifPlans/source/dvplan_CVXIF.md @@ -0,0 +1,556 @@ +# Module: CVXIF + +## Feature: Issue Interface + +### Sub-feature: 000_issue_req signals stable + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The “instr†and “mode†signals remain stable during an Issue request transaction. +* **Verification Goals** + + Check that “mode†and “instr†are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_mode signal value + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + When issue transaction starts, instruction and current CPU mode are provided +* **Verification Goals** + + Check that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** +* **Feature Description** + + Check “mode†signal values. +* **Verification Goals** + + Check that mode take a value that the CPU supports : Privilege level (2’b00 = User, 2’b01 = Supervisor, 2’b10 = Reserved, + 2’b11 = Machine). +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_rs_valid signal transition order + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + During a transaction, each bit of “rs_valid†can transition from 0 to 1 but are not allowed to transition back to 0. +* **Verification Goals** + + For issue transaction which lasts more than one cycle, check that asserted “rs_valid†signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] → 0 cannot happen) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_rs signal value + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + If XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3). +* **Verification Goals** + + For every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** +* **Feature Description** + + rs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid. +* **Verification Goals** + + Check that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** +* **Feature Description** + + If XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal. +* **Verification Goals** + + For every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Default value for unaccepted instruction + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + If accept == 0 : + Writeback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0. +* **Verification Goals** + + Check that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_Illegal Instruction causes + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The CPU shall cause an illegal instruction if: + - an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1) + - neither to be valid by the CPU nor accepted by the coprocessor (accept = 0) +* **Verification Goals** + + - CPU causes illegal instruction for instruction accepted by the core and the coprocessor. + - CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_issue uniquness + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Check for issue id validity. +* **Verification Goals** + + Check that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed). +* **Pass/Fail Criteria:** Other +* **Test Type:** Constrained Random +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_coprocessor decoding + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Accept = 1 if: + - coprocessor can handle the instruction based on decoding “instrâ€and "mode". + - “issue_valid†== 1 and required bit(s) of “rs_valid†are 1. +* **Verification Goals** + + To be checked in coprocessor. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_Transaction definition + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + “issue_resp†signals and “issue_req†signals are accepted when “issue_valid†== “issue_ready†== 1 + “issue_resp†is valid when "valid==ready==1". + “issue_req†is valid when "valid==1" +* **Verification Goals** + + The definition of a transaction. + Not to be verified. +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Commit Interface + +### Sub-feature: 000_commit_valid pulse + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The “commit_valid†== 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not). +* **Verification Goals** + + For every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ). +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_commit transaction uniquness + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + There is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted). +* **Verification Goals** + + Check that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed). +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_commit transaction for every issue transaction + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + - The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction. + - For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_valid is 1 and commit_kill is 0) or that the instruction must be killed (commit_valid is 1 and commit_kill is 1). +* **Verification Goals** + + Check that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Transaction definition + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The signals in commit are valid when commit_valid is 1. +* **Verification Goals** + + The definition of a transaction. + Not to be verified. +* **Pass/Fail Criteria:** Other +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Result Interface + +### Sub-feature: 000_no speculative result transaction + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + A coprocessor is not allowed to perform speculative result transactions. +* **Verification Goals** + + There is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0). +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_out of order result transaction + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + A coprocessor is allowed to provide results to the core in an out of order fashion. +* **Verification Goals** + + Check that the CPU is able to receive the result in an out of order fashion. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_result transaction uniquness + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Each accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU’s register file). +* **Verification Goals** + + There is an unique result transaction for every accepted and commit instruction. +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_result packet stability + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The signals in result shall remain stable during a result transaction (except data ...) +* **Verification Goals** + + Check that result signals (except data) are stable during result transaction (result_valid==1 jusqu'Ă  valid==ready ==1) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_data stability + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Data is only required to remain stable during result transactions in which "we" is not 0. +* **Verification Goals** + + Check that "data" remains stable when we==1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_synchronous exception + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + The exc is used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed. +* **Verification Goals** + + Check that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** +* **Feature Description** + + exccode provides the least significant bits of the exception code bitfield of the mcause CSR. +* **Verification Goals** + + Check that exccode signal is the value of the mcause CSR when exc == 1. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** +* **Feature Description** + +  "we" shall be driven to 0 by the coprocessor for synchronous exceptions. +* **Verification Goals** + + Check that "we" signal == 0 when exc == 1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_"we" value when dualwrite + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + we is 2 bits wide when XLEN` = 32 and X_RFW_WIDTH = 64, and 1 bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to be 1 if we[0] is 1 as well (i.e. for dual writeback). +* **Verification Goals** + + For dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_proper result transaction + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Result transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1. +* **Verification Goals** + + Check that result transaction ends properly. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/cva6/docs/VerifPlans/source/index.rst b/cva6/docs/VerifPlans/source/index.rst index 4ef40bc02..cca28ad84 100644 --- a/cva6/docs/VerifPlans/source/index.rst +++ b/cva6/docs/VerifPlans/source/index.rst @@ -25,4 +25,5 @@ CV32A6-step1 Design Verification Plan dvplan_intro dvplan_FRONTEND dvplan_ISA + dvplan_CVXIF From abc4fafcadde66607e7aca935a6bd86d561ef8ae Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:53:35 +0530 Subject: [PATCH 015/183] Added riscv-arch tests in smoke-tests.sh --- cva6/regress/smoke-tests.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cva6/regress/smoke-tests.sh b/cva6/regress/smoke-tests.sh index 1e69c8e1f..fe2770212 100644 --- a/cva6/regress/smoke-tests.sh +++ b/cva6/regress/smoke-tests.sh @@ -18,6 +18,8 @@ source ./cva6/regress/install-cva6.sh source ./cva6/regress/install-riscv-dv.sh source ./cva6/regress/install-riscv-compliance.sh source ./cva6/regress/install-riscv-tests.sh +source ./cva6/regress/install-riscv-isa-sim.sh +source ./cva6/regress/install-riscv-arch-test.sh if ! [ -n "$DV_SIMULATORS" ]; then DV_SIMULATORS=vcs-testharness,spike @@ -27,6 +29,8 @@ cd cva6/sim/ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" From dd4cd4e7c28fd608713af32ffa983c08e5cd4c8a Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:54:49 +0530 Subject: [PATCH 016/183] Updated riscv-isa-sim.patch in install-riscv-sim.sh --- cva6/regress/install-riscv-isa-sim.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cva6/regress/install-riscv-isa-sim.sh b/cva6/regress/install-riscv-isa-sim.sh index a8fd15007..795dce32b 100644 --- a/cva6/regress/install-riscv-isa-sim.sh +++ b/cva6/regress/install-riscv-isa-sim.sh @@ -11,14 +11,19 @@ if ! [ -n "$RISCV_ISA_SIM" ]; then RISCV_ISA_SIM="https://github.com/riscv-software-src/riscv-isa-sim.git" RISCV_ISA_SIM_BRANCH="master" RISCV_ISA_SIM_HASH="b9fc8e4e9087a6064dfcc627efabbe3fd4bdc309" + RISCV_ISA_SIM_PATCH="../../../cva6/regress/riscv-isa-sim.patch" fi echo $RISCV_ISA_SIM echo $RISCV_ISA_SIM_BRANCH echo $RISCV_ISA_SIM_HASH +echo $RISCV_ISA_SIM_PATCH if ! [ -d cva6/tests/riscv-isa-sim ]; then git clone $RISCV_ISA_SIM -b $RISCV_ISA_SIM_BRANCH cva6/tests/riscv-isa-sim cd cva6/tests/riscv-isa-sim; git checkout $RISCV_ISA_SIM_HASH; + if [ -f "$RISCV_ISA_SIM_PATCH" ]; then + git apply $RISCV_ISA_SIM_PATCH + fi cd - fi From 19013024974ada92972160cc85b6c330aa85c9db Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:55:58 +0530 Subject: [PATCH 017/183] Added riscv-isa-sim.patch file used to control riscv-arch-test simulation --- cva6/regress/riscv-isa-sim.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 cva6/regress/riscv-isa-sim.patch diff --git a/cva6/regress/riscv-isa-sim.patch b/cva6/regress/riscv-isa-sim.patch new file mode 100644 index 000000000..26cc20c6b --- /dev/null +++ b/cva6/regress/riscv-isa-sim.patch @@ -0,0 +1,15 @@ +diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h +index e968e43a..7628af51 100644 +--- a/arch_test_target/spike/model_test.h ++++ b/arch_test_target/spike/model_test.h +@@ -23,6 +23,7 @@ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t1; \ ++ ecall + self_loop: j self_loop; + + #define RVMODEL_BOOT +-- +2.39.0 + From 8473f7f52906cb9144fa0ef66a3aeb5827b6f4cd Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:57:08 +0530 Subject: [PATCH 018/183] Added testlist file for riscv-arch-test suite --- ...st_riscv-arch-test-cv64a6_imafdc_sv39.yaml | 1022 +++++++++-------- 1 file changed, 531 insertions(+), 491 deletions(-) diff --git a/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml index 38d8b06ae..f2dc87e8c 100644 --- a/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml +++ b/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml @@ -32,705 +32,745 @@ #- import: /target/rv64imc/testlist.yaml -- test: rv64im-add-01 +##I +- test: rv64i_m-add-01 iterations: 1 path_var: TESTS_PATH - path_root: ROOT_PROJECT gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/add-01.S -- test: rv64im-addi-01 +- test: rv64i_m-addi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S -- test: rv64im-addiw-01 +- test: rv64i_m-addiw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addiw-01.S -- test: rv64im-addw-01 +- test: rv64i_m-addw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S -- test: rv64im-addw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S - -- test: rv64im-and-01 +- test: rv64i_m-and-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/and-01.S -- test: rv64im-andi-01 +- test: rv64i_m-andi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/andi-01.S -- test: rv64im-auipc-01 +- test: rv64i_m-auipc-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/auipc-01.S -- test: rv64im-beq-01 +- test: rv64i_m-beq-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/beq-01.S -- test: rv64im-bge-01 +- test: rv64i_m-bge-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bge-01.S -- test: rv64im-bgeu-01 +- test: rv64i_m-bgeu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bgeu-01.S -- test: rv64im-blt-01 +- test: rv64i_m-blt-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/blt-01.S -- test: rv64im-bltu-01 - iterations: 0 +- test: rv64i_m-bltu-01 + iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bltu-01.S -- test: rv64im-bne-01 +- test: rv64i_m-bne-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bne-01.S -- test: rv64im-fence-01 +- test: rv64i_m-fence-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/fence-01.S -- test: rv64im-jal-01 +- test: rv64i_m-jal-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jal-01.S -- test: rv64im-jalr-01 +- test: rv64i_m-jalr-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jalr-01.S -- test: rv64im-lb-align-01 +- test: rv64i_m-lb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S -- test: rv64im-lbu-align-01 +- test: rv64i_m-lbu-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lbu-align-01.S -- test: rv64im-ld-align-01 +- test: rv64i_m-ld-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S -- test: rv64im-lh-align-01 +- test: rv64i_m-lh-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lh-align-01.S -- test: rv64im-lhu-align-01 +- test: rv64i_m-lhu-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lhu-align-01.S -- test: rv64im-lui-01 +- test: rv64i_m-lui iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S -- test: rv64im-lw-align-01 +- test: rv64i_m-lw-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S -- test: rv64im-lwu-align-01 +- test: rv64i_m-lb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lwu-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S -- test: rv64im-or-01 +- test: rv64i_m-or iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/or-01.S - -- test: rv64im-ori-01 + +- test: rv64i_m-ori iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ori-01.S - -- test: rv64im-sb-align-01 + +- test: rv64i_m-sb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sb-align-01.S - -- test: rv64im-sd-align-01 + +- test: rv64i_m-sd-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S - -- test: rv64im-sh-align-01 + +- test: rv64i_m-sh-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sh-align-01.S - -- test: rv64im-sll-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sll-01.S - -- test: rv64im-slli-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slli-01.S - -- test: rv64im-slliw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slliw-01.S - -- test: rv64im-sllw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sllw-01.S - -- test: rv64im-slt-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slt-01.S - -- test: rv64im-slti-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slti-01.S - -- test: rv64im-sltiu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltiu-01.S - -- test: rv64im-sltu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltu-01.S - -- test: rv64im-sra-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sra-01.S - -- test: rv64im-srai-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srai-01.S - -- test: rv64im-sraiw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraiw-01.S - -- test: rv64im-sraw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraw-01.S - -- test: rv64im-srl-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srl-01.S - -- test: rv64im-srli-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srli-01.S - -- test: rv64im-srliw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srliw-01.S - -- test: rv64im-srlw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srlw-01.S - -- test: rv64im-sub-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sub-01.S - -- test: rv64im-subw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/subw-01.S - -- test: rv64im-sw-align-01 + +- test: rv64i_m-sw-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S - -- test: rv64im-xor-01 + +- test: rv64i_m-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sll-01.S + +- test: rv64i_m-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slli-01.S + +- test: rv64i_m-slliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slliw-01.S + +- test: rv64i_m-sllw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sllw-01.S + +- test: rv64i_m-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slt-01.S + +- test: rv64i_m-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slti-01.S + +- test: rv64i_m-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltiu-01.S + +- test: rv64i_m-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltu-01.S + +- test: rv64i_m-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sra-01.S + +- test: rv64i_m-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srai-01.S + +- test: rv64i_m-sraiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraiw-01.S + +- test: rv64i_m-sraw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraw-01.S + +- test: rv64i_m-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srl-01.S + +- test: rv64i_m-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srli-01.S + +- test: rv64i_m-srliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srliw-01.S + +- test: rv64i_m-srlw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srlw-01.S + +- test: rv64i_m-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sub-01.S + +- test: rv64i_m-subw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/subw-01.S + +- test: rv64i_m-xor iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xor-01.S - -- test: rv64im-xori-01 + +- test: rv64i_m-xori iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xori-01.S -- test: rv64im-cadd-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S - -- test: rv64im-caddi4spn-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S - -- test: rv64im-caddi16sp-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S - -- test: rv64im-caddi-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S - -- test: rv64im-caddiw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S - -- test: rv64im-caddw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S - -- test: rv64im-cand-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S - -- test: rv64im-candi-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S - -- test: rv64im-cbeqz-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S - -- test: rv64im-cbnez-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S - -- test: rv64im-cebreak-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S - -- test: rv64im-cj-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S - -- test: rv64im-cjalr-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S - -- test: rv64im-cjr-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S - -- test: rv64im-cld-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S - -- test: rv64im-cldsp-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S - -- test: rv64im-cli-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S - -- test: rv64im-clui-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S - -- test: rv64im-clw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S - -- test: rv64im-clwsp-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S - -- test: rv64im-cmv-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S - -- test: rv64im-cnop-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S - -- test: rv64im-cor-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S - -- test: rv64im-csd-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S - -- test: rv64im-csdsp-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S - -- test: rv64im-cslli-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S - -- test: rv64im-csrai-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S - -- test: rv64im-csrli-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S - -- test: rv64im-csub-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S - -- test: rv64im-csubw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S - -- test: rv64im-csw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S - -- test: rv64im-cswsp-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S - -- test: rv64im-cxor-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S - -- test: rv64im-div-01 + #M +- test: rv64i_m-div-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S - -- test: rv64im-divu-01 + +- test: rv64i_m-divu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S - -- test: rv64im-divuw-01 + +- test: rv64i_m-divuw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S - -- test: rv64im-divw-01 + +- test: rv64i_m-divw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divw-01.S - -- test: rv64im-mul-01 + +- test: rv64i_m-mul-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mul-01.S - -- test: rv64im-mulh-01 + +- test: rv64i_m-mulh-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulh-01.S - -- test: rv64im-mulhsu-01 + +- test: rv64i_m-mulhsu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S - -- test: rv64im-mulhu-01 + +- test: rv64i_m-mulhu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhu-01.S - -- test: rv64im-mulw-01 + +- test: rv64i_m-mulw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulw-01.S - -- test: rv64im-rem-01 + +- test: rv64i_m-rem-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/rem-01.S - -- test: rv64im-remu-01 + +- test: rv64i_m-remu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remu-01.S - -- test: rv64im-remuw-01 + +- test: rv64i_m-remuw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remuw-01.S - -- test: rv64im-remw-01 + +- test: rv64i_m-remw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remw-01.S -- test: rv64im-ebreak + #C +- test: rv64i_m-cadd-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ebreak.S - -- test: rv64im-ecall - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ecall.S - -- test: rv64im-misalign1-jalr-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign1-jalr-01.S - -- test: rv64im-misalign2-jalr-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign2-jalr-01.S - -- test: rv64im-misalign-beq-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-beq-01.S - -- test: rv64im-misalign-bge-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bge-01.S - -- test: rv64im-misalign-bgeu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bgeu-01.S - -- test: rv64im-misalign-blt-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-blt-01.S - -- test: rv64im-misalign-bltu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bltu-01.S - -- test: rv64im-misalign-bne-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bne-01.S - -- test: rv64im-misalign-jal-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-jal-01.S - -- test: rv64im-misalign-ld-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-ld-01.S - -- test: rv64im-misalign-lh-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lh-01.S - -- test: rv64im-misalign-lhu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lhu-01.S - -- test: rv64im-misalign-lw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lw-01.S - -- test: rv64im-misalign-lwu-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lwu-01.S - -- test: rv64im-misalign-sd-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sd-01.S - -- test: rv64im-misalign-sh-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sh-01.S - -- test: rv64im-misalign-sw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sw-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S -- test: rv64im-Fencei +- test: rv64i_m-caddi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S \ No newline at end of file + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S + +- test: rv64i_m-caddi16sp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S + +- test: rv64i_m-caddi4spn-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S + +- test: rv64i_m-caddiw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S + +- test: rv64i_m-caddw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S + +- test: rv64i_m-cand-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S + +- test: rv64i_m-candi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S + +- test: rv64i_m-cbeqz-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S + +- test: rv64i_m-cbnez-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S + +- test: rv64i_m-cebreak-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S + +- test: rv64i_m-cj-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S + +- test: rv64i_m-cjalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S + +- test: rv64i_m-cjr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S + +- test: rv64i_m-cld-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S + +- test: rv64i_m-cldsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S + +- test: rv64i_m-cli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S + +- test: rv64i_m-clui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S + +- test: rv64i_m-clw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S + +- test: rv64i_m-clwsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S + +- test: rv64i_m-cmv-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S + +- test: rv64i_m-cnop-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S + +- test: rv64i_m-cor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S + +- test: rv64i_m-csd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S + +- test: rv64i_m-csdsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S + +- test: rv64i_m-cslli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S + +- test: rv64i_m-csrai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S + +- test: rv64i_m-csrli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S + +- test: rv64i_m-csub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S + +- test: rv64i_m-csubw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S + +- test: rv64i_m-csw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S + +- test: rv64i_m-cswsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S + +- test: rv64i_m-cxor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S + +#D +- test: rv64i_m-fcvt.d.l_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b25-01.S + +- test: rv64i_m-fcvt.d.l_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b26-01.S + +- test: rv64i_m-fcvt.d.lu_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b25-01.S + +- test: rv64i_m-fcvt.d.lu_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b26-01.S + +- test: rv64i_m-fcvt.l.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b1-01.S + +- test: rv64i_m-fcvt.l.d_b22-01.S + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b22-01.S + +- test: rv64i_m-fcvt.l.d_b23-01.S + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b23-01.S + +- test: rv64i_m-fcvt.l.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b24-01.S + +- test: rv64i_m-fcvt.l.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b27-01.S + +- test: rv64i_m-fcvt.l.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b28-01.S + +- test: rv64i_m-fcvt.l.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b29-01.S + +- test: rv64i_m-fcvt.lu.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b1-01.S + +- test: rv64i_m-fcvt.lu.d_b22-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b22-01.S + +- test: rv64i_m-fcvt.lu.d_b23-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b23-01.S + +- test: rv64i_m-fcvt.lu.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b24-01.S + +- test: rv64i_m-fcvt.lu.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b27-01.S + +- test: rv64i_m-fcvt.lu.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b28-01.S + +- test: rv64i_m-fcvt.lu.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b29-01.S + +- test: rv64i_m-fmv.d.x_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b25-01.S + +- test: rv64i_m-fmv.d.x_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b26-01.S + +- test: rv64i_m-fmv.x.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b1-01.S + +- test: rv64i_m-fmv.x.d_b22-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b22-01.S + +- test: rv64i_m-fmv.x.d_b23-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b23-01.S + +- test: rv64i_m-fmv.x.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b24-01.S + +- test: rv64i_m-fmv.x.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b27-01.S + +- test: rv64i_m-fmv.x.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b28-01.S + +- test: rv64i_m-fmv.x.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b29-01.S + From 5ae8ba8ed19f5ea9cbad480cddd6e6f4d25b746e Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:57:58 +0530 Subject: [PATCH 019/183] Added testlist file for riscv-arch-test suite --- .../testlist_riscv-arch-test-cv32a60x.yaml | 472 ++++++++++++++++++ 1 file changed, 472 insertions(+) create mode 100644 cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml diff --git a/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml b/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml new file mode 100644 index 000000000..cc6801383 --- /dev/null +++ b/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml @@ -0,0 +1,472 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- +## C +- test: rv32im-cadd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S + +- test: rv32im-caddi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S + +- test: rv32im-caddi16sp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S + +- test: rv32im-caddi4spn-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S + +- test: rv32im-cand-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S + +- test: rv32im-candi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S + +- test: rv32im-cbeqz-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S + +- test: rv32im-cbnez-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S + +- test: rv32im-cebreak-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S + +- test: rv32im-cj-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S + +- test: rv32im-cjal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S + +- test: rv32im-cjalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S + +- test: rv32im-cjr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S + +- test: rv32im-cli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S + +- test: rv32im-clui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S + +- test: rv32im-clw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S + +- test: rv32im-clwsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S + +- test: rv32im-cmv-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S + +- test: rv32im-cnop-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S + +- test: rv32im-cor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S + +- test: rv32im-cslli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S + +- test: rv32im-csrai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S + +- test: rv32im-csrli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S + +- test: rv32im-csub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S + +- test: rv32im-csw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S + +- test: rv32im-cswsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S + +- test: rv32im-cxor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S + + # I +- test: rv32im-add-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S + +- test: rv32im-addi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S + +- test: rv32im-and-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S + +- test: rv32im-andi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S + +- test: rv32im-auipc-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S + +- test: rv32im-beq-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S + +- test: rv32im-bge-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S + +- test: rv32im-bgeu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S + +- test: rv32im-blt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S + +- test: rv32im-bltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S + +- test: rv32im-bne-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S + +- test: rv32im-fence-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S + +- test: rv32im-jal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S + +- test: rv32im-jalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S + +- test: rv32im-lb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S + +- test: rv32im-lbu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S + +- test: rv32im-lh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S + +- test: rv32im-lhu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S + +- test: rv32im-lui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S + +- test: rv32im-lw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S + +- test: rv32im-or-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S + +- test: rv32im-ori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S + +- test: rv32im-sb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S + +- test: rv32im-sh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S + +- test: rv32im-sll-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S + +- test: rv32im-slli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S + +- test: rv32im-slt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S + +- test: rv32im-slti-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S + +- test: rv32im-sltiu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S + +- test: rv32im-sltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S + +- test: rv32im-sra-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S + +- test: rv32im-srai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S + +- test: rv32im-srl-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S + +- test: rv32im-srli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S + +- test: rv32im-sub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S + +- test: rv32im-sw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S + +- test: rv32im-xor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S + +- test: rv32im-xori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S + + # M +- test: rv32im-div-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S + +- test: rv32im-divu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S + +- test: rv32im-mul-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S + +- test: rv32im-mulh-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S + +- test: rv32im-mulhsu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S + +- test: rv32im-mulhu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S + +- test: rv32im-rem-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S + +- test: rv32im-remu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S + From 32e525662eac519ead6aa81c5928e565c59d889d Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Mon, 6 Feb 2023 08:35:31 +0100 Subject: [PATCH 020/183] Gather the 32 bit tests together --- cva6/regress/smoke-tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cva6/regress/smoke-tests.sh b/cva6/regress/smoke-tests.sh index fe2770212..78dfd8677 100644 --- a/cva6/regress/smoke-tests.sh +++ b/cva6/regress/smoke-tests.sh @@ -30,7 +30,6 @@ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.ya python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld -python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" @@ -38,6 +37,7 @@ make -C ../../core-v-cores/cva6 clean make clean_all python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld make -C ../../core-v-cores/cva6 clean make clean_all From 0b317e17043b4301a9ef377ccc3e7aa7d71e432e Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Mon, 6 Feb 2023 17:27:30 +0530 Subject: [PATCH 021/183] Updated cva6.yml by adding pub_riscv-arch-test task --- .gitlab-ci/cva6.yml | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/.gitlab-ci/cva6.yml b/.gitlab-ci/cva6.yml index b9442f7d2..5dbfcd100 100644 --- a/.gitlab-ci/cva6.yml +++ b/.gitlab-ci/cva6.yml @@ -158,6 +158,33 @@ pub_smoke: paths: - artifacts/reports/*.yml +pub_riscv_arch_test: + stage: two + extends: + - .template_job_short_ci + needs: + - job: pub_smoke + artifacts: false + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - source cva6/regress/dv-riscv-arch-test.sh + - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" + pub_hwconfig: stage: two extends: From 73a2d30243f0ac796cedebdbf2297aa75d5d05af Mon Sep 17 00:00:00 2001 From: Rana Adeel Ahmad Date: Mon, 6 Feb 2023 18:02:50 +0500 Subject: [PATCH 022/183] Documentation for the UVM_Verification Environment for CVA6 core. --- cva6/docs/UVM_verif_env.md | 2 +- cva6/docs/images/CVA6_UVM_env.drawio.png | Bin 37342 -> 0 bytes cva6/docs/images/CVA6_env.drawio.drawio.png | Bin 0 -> 154591 bytes 3 files changed, 1 insertion(+), 1 deletion(-) delete mode 100644 cva6/docs/images/CVA6_UVM_env.drawio.png create mode 100644 cva6/docs/images/CVA6_env.drawio.drawio.png diff --git a/cva6/docs/UVM_verif_env.md b/cva6/docs/UVM_verif_env.md index ccd58d9c3..cbd638e45 100644 --- a/cva6/docs/UVM_verif_env.md +++ b/cva6/docs/UVM_verif_env.md @@ -6,7 +6,7 @@ This document describes the uvm verification environment of the CVA6 core. This environment is intended to be able to verify the CVA6 core and run different test cases by the minimal modification to the environment itself. The environment is shown below: -![alt_text](images/CVA6_UVM_env.drawio.png "image_tooltip") +![alt_text](images/CVA6_env.drawio.drawio.png "image_tooltip") *** diff --git a/cva6/docs/images/CVA6_UVM_env.drawio.png b/cva6/docs/images/CVA6_UVM_env.drawio.png deleted file mode 100644 index 151107b7a83a6f7256bd8390c77d50d6c70dd071..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37342 zcmd431yCJbw)$#u>DUA3Q=Pei*7^0|%fD9NI1UVSkn-N%O;1^W| z7$e{V(uPm;2P|;7!s_|~-?4246>ViL^lcrqto6VQ%q`6HsBLtt_4Leb3@vOy5Ut!` zU_@Y|0=z#QlMa_WY$LDTo*#2n44Nl5KA*iQton+4md0;hC$;(8MrTROz>nWPjGtwb zpQWfh!H<;0-iB6jYZ3hSwipz<*kP8$VHr8>FOOjF2&pg&hW zE40-~{}z>fB%QqA4L+KME+J#PkDx?WPb3)(8lOg&vY{XUdVjjQ%oA za=;xmgPe8aq91MJm(DBjJA!}4wx;$8)2@VwV0qZ`0}^gN-KBMwIy%Kz&y@b zJvw8kRc@wA-Me$SFY`?ZG7Ae$Dh3*hV`$U@mfT5b(uXovhs+pUxI~H!gWYhg%MP>)3#qK;+FR=VUY+wjMd;gg>tNCrQ&i+ z9%pY&Ue|^xhm%$nCuR)ywEawOz|=Nv<`MjpOnTF9-X!dx+Wh2ssxIakBK%-mD*0aH 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a/lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_mon.sv b/lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_mon.sv index 5e9d0ebe3..f950dd86f 100644 --- a/lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_mon.sv +++ b/lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_mon.sv @@ -1,3 +1,5 @@ + + // Copyright 2021 Thales DIS design services SAS // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); From 0243117f2395c9999aaf942ae8b6d5a2a077dca4 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Thu, 9 Feb 2023 17:48:13 +0100 Subject: [PATCH 024/183] Fix typo related to TESTS_REPO --- .gitlab-ci/setup-ci-example/core-v-verif-cv32.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml b/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml index 30538e931..a43b7c60b 100644 --- a/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml +++ b/.gitlab-ci/setup-ci-example/core-v-verif-cv32.yml @@ -15,8 +15,8 @@ variables: COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437 COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch TESTS_REPO: https://github.com/riscv/riscv-tests.git - TEST_BRANCH: master - TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec + TESTS_BRANCH: master + TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec DV_REPO: https://github.com/google/riscv-dv.git DV_BRANCH: master NUM_JOBS: 24 From f454ea40b05cad91aa9342c2cf439802282d911e Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Thu, 9 Feb 2023 17:48:56 +0100 Subject: [PATCH 025/183] fix typo related to TESTS_REPO --- .gitlab-ci/setup-ci-example/core-v-verif-cva6.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml index ab5d5f98e..a0553c582 100644 --- a/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml +++ b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml @@ -16,8 +16,8 @@ variables: COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437 COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch TESTS_REPO: https://github.com/riscv/riscv-tests.git - TEST_BRANCH: master - TEST_HASH: f92842f91644092960ac7946a61ec2895e543cec + TESTS_BRANCH: master + TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec DV_REPO: https://github.com/google/riscv-dv.git DV_BRANCH: master NUM_JOBS: 24 From 0e16c6a0e201e1a491f092c510cf348ad728454a Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 6 Feb 2023 16:02:04 +0100 Subject: [PATCH 026/183] [VPTOOL] Use Ruamel Yaml to handle Yaml I/O. Set up infra for Yaml output. * tools/vptool/vptool/vp.py (toplevel): Import Ruamel Yaml instead of the PyYaml flavor. Add skeleton of support for *existing* DVplan object classes. (MyMain.save_db): Update the Git SHA1 signatures on all IPs, not only on those currently unlocked (all IPs are manipulated by the current VPTOOL version, whether saved or not.) Update Pickle protocol version to v4 (default in Python 3.6+). Add stubs/comments for Yaml output. (MyMain.load_db_quiet): Add stubs/comments for Yaml input. (MyMain.lock_ip): Use Pickle protocol v4. (MyMain.lock_all_ip): Ditto. (MyMain.save_personalization): Ditto. (toplevel): Use Ruamel Yaml engine to load configuration file using the safe loader. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 71 ++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 19 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index a782de3ee..a4a1e7098 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -20,18 +20,25 @@ from inspect import ismethod import pickle from collections import OrderedDict +# Use Ruamel YAML support +from ruamel.yaml import YAML, yaml_object +# global db_yaml_engine +# db_yaml_engine = YAML(typ='rt') + # import cPickle as pickle # Configuration (env + Python + Yaml) is imported indirectly via vp_pack. from vp_pack import * + +# db_yaml_engine.register_class(Item) +# db_yaml_engine.register_class(Prop) +# db_yaml_engine.register_class(Ip) + import os, sys, pwd, glob, subprocess from optparse import OptionParser, Option from PIL import Image, ImageTk import shutil import hashlib -# PyYAML import: Use C backend (libyaml) if available. -from yaml import load, dump - try: from yaml import CLoader as Loader, CDumper as Dumper except ImportError: @@ -1953,16 +1960,16 @@ class MyMain: save_dir = os.path.dirname(vp_config.SAVED_DB_LOCATION) saved_ip_str = "" for ip_elt in pickle_ip_list: + # Sign the IP with the current SHA1 of VPTOOL. + ip_elt[1].vptool_gitrev = self.vptool_gitrev + ip_elt[1].io_fmt_gitrev = vp_config.io_fmt_gitrev + ip_elt[1].config_gitrev = vp_config.config_gitrev + ip_elt[1].ymlcfg_gitrev = vp_config.yaml_config[ + "yaml_cfg_gitrev" + ] # Save individual IPs only if locked by user. if self.is_locked_by_user(current_ip_name=ip_elt[1].name): saved_ip_str += "\n " + ip_elt[1].name - # Sign the IP with the current SHA1 of VPTOOL. - ip_elt[1].vptool_gitrev = self.vptool_gitrev - ip_elt[1].io_fmt_gitrev = vp_config.io_fmt_gitrev - ip_elt[1].config_gitrev = vp_config.config_gitrev - ip_elt[1].ymlcfg_gitrev = vp_config.yaml_config[ - "yaml_cfg_gitrev" - ] with open( save_dir + "/VP_IP" @@ -1970,7 +1977,21 @@ class MyMain: + ".pck", "wb", ) as output: - pickle.dump(ip_elt, output, 0) + pickle.dump(ip_elt, output, 4) + # TODO: Add translation of pickle_ip_list to new-gen + # types *HERE*, after emitting Pickle. + # Emit the Yaml output from the fixed structures, + # skipping pickled ones. + # Write yaml output + #with open( + # save_dir + # + "/VP_IP" + # + str(ip_elt[1].ip_num).zfill(3) + # + ".yml", + # "wb", + #) as output: + # db_yaml_engine.dump(ip_elt[1], output) + if saved_ip_str: tkinter.messagebox.showinfo( "Info", @@ -1987,10 +2008,11 @@ class MyMain: % vp_config.yaml_config["gui"]["ip"]["label"].lower(), ) else: + # ZC FIXME Add support for Yaml in non-split-save mode. with open(vp_config.SAVED_DB_LOCATION, "wb") as output: - pickle.dump(len(pickle_ip_list), output, 0) + pickle.dump(len(pickle_ip_list), output, 4) for ip_elt in pickle_ip_list: - pickle.dump(ip_elt, output, 0) + pickle.dump(ip_elt, output, 4) self.prep_db_import() # update_ip_widget() self.update_all_item_target_list() @@ -2058,6 +2080,9 @@ class MyMain: # print("---INFO: Loading "+filename) with open(filename, "rb") as input: pickle_ip_list.append(pickle.load(input)) + #for filename in glob.glob(dir_to_load + "/VP_IP*yml"): + # with open(filename, "rb") as input: + # pickle_ip_list.append(db_yaml_engine.load(input)) if pickle_ip_list: # Find the lowest ip_num that can be used for newly created IPs. # It has to be higher than the highest existing ip_num. @@ -2065,6 +2090,7 @@ class MyMain: ip_num_next = 1 + max( [ (lambda e: e if isinstance(e, int) else int(e, base=10))( + #elt.ip_num # Yaml !!omap mode: list of objects elt[1].ip_num ) for elt in pickle_ip_list @@ -2083,6 +2109,12 @@ class MyMain: for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict + # Yaml mode: !!omap produced a list of elts + #for ip_elt in pickle_ip_list: + # self.ip_list[ip_elt.name] = ip_elt + # # Seems pickle doesn't restore class attribute. Done manually here for IP + # self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next + # Pickle mode: list of objects is a list of mappings for ip_key, ip_elt in pickle_ip_list: self.ip_list[ip_key] = ip_elt # Seems pickle doesn't restore class attribute. Done manually here for IP @@ -2145,7 +2177,7 @@ class MyMain: LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 0) + pickle.dump(LOCKED_IP_DICT, output, 4) self.update_ip_widget() except Exception as e: print( @@ -2168,7 +2200,7 @@ class MyMain: LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 0) + pickle.dump(LOCKED_IP_DICT, output, 4) self.update_ip_widget() except Exception as e: print( @@ -2247,9 +2279,9 @@ class MyMain: if os.path.exists(sys.argv[0]): preference_file = os.path.dirname(sys.argv[0]) + "/" + PERSO_FILE with open(preference_file, "wb") as output: - pickle.dump(BG_COLOR, output, 0) - pickle.dump(EDITOR, output, 0) - pickle.dump(self.verif_menu.enable_image_panel.get(), output, 0) + pickle.dump(BG_COLOR, output, 4) + pickle.dump(EDITOR, output, 4) + pickle.dump(self.verif_menu.enable_image_panel.get(), output, 4) def change_gui_color(self): global BG_COLOR @@ -2455,7 +2487,8 @@ def __generate_option_parser(): # Load YAML configuration if available. try: with open(os.path.join(os.path.dirname(__file__), YAML_CONFIG_FILE), "r") as f: - vp_config.init_yaml_config(load(f, Loader=Loader)) + config_yaml_engine = YAML(typ='safe') + vp_config.init_yaml_config(config_yaml_engine.load(f)) # print("YAML config = \n" + dump(vp_config.yaml_config, Dumper=Dumper)) except Exception as e: print( From 64c0fe5b249794ef41042e1805bb27905ef24a45 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Tue, 7 Feb 2023 12:31:44 +0100 Subject: [PATCH 027/183] [VPTOOL] Add transcoding of legacy structures. Output new structs as Yaml. * tools/vptool/vptool/vp.py (db_yaml_engine): New global object. Register VerifItem, Subfeature and Feature as Yaml-supported classes. (MyMain.save_db): Dump new-style data structures as Yaml for all Ip objects. (MyMain.load_db_quiet): Update Yaml-relaed comments. * tools/vptool/vptool/vp_pack.py (toplevel): Import OrderedDict. (VerifItem): New class. (Item.to_VerifItem): Add translation method legacy->new for verif items. (Subfeature): New class. (Prop.to_Subfeature): Add translation method legacy->new for subfeatures. (Feature): New class. (Ip.to_Feature): Add translation method legacy->new for features. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 28 ++--- tools/vptool/vptool/vp_pack.py | 202 +++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+), 14 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index a4a1e7098..900ed0905 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -22,16 +22,16 @@ from collections import OrderedDict # Use Ruamel YAML support from ruamel.yaml import YAML, yaml_object -# global db_yaml_engine -# db_yaml_engine = YAML(typ='rt') +global db_yaml_engine +db_yaml_engine = YAML(typ='rt') # import cPickle as pickle # Configuration (env + Python + Yaml) is imported indirectly via vp_pack. from vp_pack import * -# db_yaml_engine.register_class(Item) -# db_yaml_engine.register_class(Prop) -# db_yaml_engine.register_class(Ip) +db_yaml_engine.register_class(VerifItem) +db_yaml_engine.register_class(Subfeature) +db_yaml_engine.register_class(Feature) import os, sys, pwd, glob, subprocess from optparse import OptionParser, Option @@ -1983,14 +1983,14 @@ class MyMain: # Emit the Yaml output from the fixed structures, # skipping pickled ones. # Write yaml output - #with open( - # save_dir - # + "/VP_IP" - # + str(ip_elt[1].ip_num).zfill(3) - # + ".yml", - # "wb", - #) as output: - # db_yaml_engine.dump(ip_elt[1], output) + with open( + save_dir + + "/VP_IP" + + str(ip_elt[1].ip_num).zfill(3) + + "_new_types.yml", + "wb", + ) as output: + db_yaml_engine.dump(ip_elt[1].to_Feature(), output) if saved_ip_str: tkinter.messagebox.showinfo( @@ -2109,7 +2109,7 @@ class MyMain: for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict - # Yaml mode: !!omap produced a list of elts + # Yaml mode: !!omap yields a list of elts when loaded. #for ip_elt in pickle_ip_list: # self.ip_list[ip_elt.name] = ip_elt # # Seems pickle doesn't restore class attribute. Done manually here for IP diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 2f6f9e7bc..afcf27b5e 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -10,6 +10,7 @@ import sys, os from datetime import datetime +from collections import OrderedDict import re # Load the configuration associated with the current platform @@ -47,6 +48,61 @@ def normalize_tag(l): ##################################### ##### Class Definition + +class VerifItem: + """ + A Verification Item captures a specific aspect of a design that + can be individually verified. + Verification Items are intended to be instantiated in a Subfeature + class which groups Verification Items related to a given property of + the design, e.g. to one instruction of an Instruction Set. + """ + # Class variable: Names of Python attributes of a Verification Item that + # can be free-form strings and have default cue strings defined. + attr_names = [ + "description", + "reqt_doc", # Note the 'd' in '_doc'... + "verif_goals", + "coverage_loc", + "comments" + ] + # Class variable: Matching names in Yaml-based GUI configuration + gui_fields = [ + "feature_descr", + "requirement_loc", + "verif_goals", + "coverage_loc", + "comments", + ] + + def __init__(self, name=0, tag="", description=""): + # Identifier of the Item, used in display lists. + self.name = name + # Unique tag of the Verificataion Item (never to be reused). + self.tag = tag + # Description of the property to be verified. + self.description = description + # Document containing the corresponding requirement + self.reqt_doc = "" + # Pointers into the document + self.ref_mode = "page" + self.ref_page = "" + self.ref_section = "" + self.ref_viewer = "firefox" + # Goals of verification + self.verif_goals = "" + # Pointer to coverage data + self.coverage_loc = "" + # Pass/fail criteria + self.pfc = -1 # None selected, must choose + # Test type + self.test_type = -1 # None selected, must choose + # Coverage method + self.cov_method = -1 # None selected, must choose + # Applicable cores + self.cores = -1 # By default, a new Verif Item is applicable to all cores. + self.comments = "" + class Item: """ An item defines a specific case to test depending on its parent property @@ -95,6 +151,27 @@ class Item: self.rfu_dict = {} # used as lock. will be updated with class update self.rfu_dict["lock_status"] = 0 + def to_VerifItem(self): + """ + Convert an Item to a VerifItem. Keep only the information that's needed. + """ + result = VerifItem(self.name, self.tag, self.description) + result.reqt_doc = self.purpose + # These attributes may be missing on objects coming from older VPTOOL versions. + for attr in ["ref_mode", "ref_page", "ref_section", "ref_viewer"]: + if hasattr(self, attr): + setattr(result, attr, getattr(self, attr)) + else: + setattr(result, attr, "") + result.verif_goals = self.verif_goals + result.pfc = self.pfc + result.test_type = self.test_type + result.cov_method = self.cov_method + result.cores = self.cores + result.coverage_loc = self.coverage_loc + result.comments = self.comments + return result + def attrval2str(self, attr): if attr == "cores" and "cores" in vp_config.yaml_config: # 'cores' are at toplevel of the Yaml config and the attr value is a bitmap. @@ -198,6 +275,43 @@ class Item: self.tag = normalize_tag(self.tag) +class Subfeature: + """ + A Subfeature is a subset of a major design feature that is characterized + by a distinctive property. Therefore, the verification items related to + that property are closely related and are grouped together into a list + associated with the Subfeature. + """ + def __init__(self, name="", tag=""): + # Name of the subfeature + self.name = name + # Tag of the subfeature: Must be unique across all subfeatures. + self.tag = tag + # Index of the next item to be added (MUST INCREASE ON EVERY ADDITION!) + self.next_elt_id = 0 + # List of Verification Items in this feature: an OrderedDict. + self.items = OrderedDict() + + def __str__(self): + return format("### Sub-feature: %s\n\n" % (self.name)) + + def add_item(self, tag, description=""): # adds a Verification Item to subfeature + new_item = VerifItem( + str(self.next_elt_id).zfill(3), + tag=tag + "_I" + str(self.next_elt_id).zfill(3), + description=description, + ) + self.items[str(self.next_elt_id).zfill(3)] = new_item + self.next_elt_id += 1 + # Return a ref to the newly created item. + return new_item + + def del_item(self, index): # remove a verification item from the subfeature + del self.items[index] + + def get_item_names(self): + return [item.name for item in self.items.values()] + class Prop: """ A Property defines a specific behaviour or an IP section, to be tested/verified @@ -219,6 +333,24 @@ class Prop: self.rfu_list_2 = [] self.rfu_dict = {} + def to_Subfeature(self): + """ + Convert a legacy Prop to a Subfeature, transfer only the fields that are required. + """ + result = Subfeature(self.name, self.tag) + # 'next_elt_id' needs extra care as 'item_count' assumes a contiguous + # numbering of Items in Prop and will be inconsistent if items are removed. + # Computing the max of item IDs is not reliable either in case the last + # item was removed. + result.next_elt_id = self.item_count + max_item_id = max([int(elt[1].name) for elt in (self.item_list if self.item_list else self.rfu_list)]) + if max_item_id >= self.item_count: + raise ValueError((self.item_count, max_item_id)) + result.next_elt_id = 1 + max_item_id + translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] + result.items = OrderedDict(translated_items) + return result + def __str__(self): return format("### Sub-feature: %s\n\n" % (self.name)) @@ -315,6 +447,64 @@ class Prop: for item in list(self.item_list.values()): item.lock() +class Feature: + """ + A Feature is a major group of design properties, for example + a class of instructions or an operation mode of an interface. + """ + # Class variable: highest Feature ID seen so far. + _highest_id = -1 + + def __init__(self, name="", id=0): + # Index of next subfeature to add (MUST ALWAYS GROW upon adding subfeatures!) + self.next_elt_id = 0 + # Name of the Feature + self.name = name + # Numerical ID of the Feature: Use the highest known value PLUS ONE + # unless explicitly given (e.g., when converting Ip objects). + if id != 0: + if id > self.__class__._highest_id: + self.__class__._highest_id = id + self.id = id + else: + raise ValueError((id, self.__class__._highest_id)) + else: + self.__class__._highest_id += 1 + self.id = self.__class__._highest_id + # Index of the Feature (for display ordering) + #self.index = index + # List of subfeatures + self.subfeatures = OrderedDict() + + def __str__(self): + return format("## Feature: %s\n\n" % (self.name)) + + def add_subfeature(self, name, tag=""): + """ + Add a subfeature of the current feature. + """ + if name in self.subfeatures.keys(): + print("Subfeature '%s' already exists in Feature '%s'!" % (name, self.name)) + feedback = 0 + else: + name = remove_non_ascii(name) + subfeature_name = str(self.next_elt_id).zfill(3) + "_" + str(name) + self.next_elt_id += 1 + self.subfeatures[name] = Subfeature( + subfeature_name, + tag="VP_" + + vp_config.PROJECT_IDENT + + "_F" + + str(self.ip_num).zfill(3) + + "_S" + + str(self.prop_count).zfill(3), + ) + feedback = self.subfeatures[subfeature_name].tag + self._count += 1 + return (feedback, subfeature_name) + + def del_subfeature(self, name): + del self.subfeatures[str(name)] class Ip: """ @@ -341,6 +531,18 @@ class Ip: self.rfu_list_0 = [] self.rfu_list_1 = [] + def to_Feature(self): + """ + Convert an Ip to a Feature. + """ + result = Feature(self.name, self.ip_num) + # Next_elf_it needs extra care as it is derived from the length of the list + # of Properties / Subfeatures. + result.next_elt_id = self.prop_count + translated_subfeatures = [[elt[0], elt[1].to_Subfeature()] for elt in (self.prop_list if self.prop_list else self.rfu_list)] + result.subfeatures = OrderedDict(translated_subfeatures) + return result + def __str__(self): return format("## Feature: %s\n\n" % (self.name)) From 364fd25fd40fdfb10cc337792d65d0749612369c Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Tue, 7 Feb 2023 17:30:47 +0100 Subject: [PATCH 028/183] [VPTOOL] Save Git SHA1s in Yaml data. Add Yaml->legacy translation path. * tools/vptool/vptool/vp_pack.py (VerifItem.__init__): Reorder attribs to better match GUI layout. Update comments. (VerifItem.to_Item): New. (Item.to_VerifItem): Factorize identical attribute assignment. (Subfeature.__init__): Add 'display_order' attrib. (Subfeature.to_Prop): New. (Prop.to_Subfeature): Propagage 'wid_order' attrib as 'display_order'. (Feature.__init__): Add 'display_order' and VPTOOL Git SHA1 attribs. (Feature.to_Ip): New. (Ip.__init__): Add VPTOOL Git SHA1 attribs. (Ip.to_Feature): Copy Git SHA1 attribs. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp_pack.py | 72 ++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 13 deletions(-) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index afcf27b5e..d9d5324a1 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -82,17 +82,15 @@ class VerifItem: self.tag = tag # Description of the property to be verified. self.description = description - # Document containing the corresponding requirement + # Document containing the corresponding requirement or design spec. self.reqt_doc = "" - # Pointers into the document + # Viewing information for the requirement/design document. self.ref_mode = "page" self.ref_page = "" self.ref_section = "" self.ref_viewer = "firefox" # Goals of verification self.verif_goals = "" - # Pointer to coverage data - self.coverage_loc = "" # Pass/fail criteria self.pfc = -1 # None selected, must choose # Test type @@ -101,8 +99,24 @@ class VerifItem: self.cov_method = -1 # None selected, must choose # Applicable cores self.cores = -1 # By default, a new Verif Item is applicable to all cores. + # Pointer to coverage data + self.coverage_loc = "" + # User comments for the verification item self.comments = "" + def to_Item(self): + """ + Convert a VerifItem to a legacy-style Item object. + """ + result = Item(self.name, self.tag, self.description, self.reqt_doc) + # These attributes are a 1-to-1 match. + for attr in [ + "ref_mode", "ref_page", "ref_section", "ref_viewer", "verif_goals", + "pfc", "test_type", "cov_method", "cores", "coverage_loc", "comments", + ]: + setattr(result, attr, getattr(self, attr)) + return result + class Item: """ An item defines a specific case to test depending on its parent property @@ -163,13 +177,12 @@ class Item: setattr(result, attr, getattr(self, attr)) else: setattr(result, attr, "") - result.verif_goals = self.verif_goals - result.pfc = self.pfc - result.test_type = self.test_type - result.cov_method = self.cov_method - result.cores = self.cores - result.coverage_loc = self.coverage_loc - result.comments = self.comments + # The following attributes were already mandatory in older RISC-V VPTOOL versions. + for attr in [ + "verif_goals", + "pfc", "test_type", "cov_method", "cores", "coverage_loc", "comments", + ]: + setattr(result, attr, getattr(self, attr)) return result def attrval2str(self, attr): @@ -289,6 +302,8 @@ class Subfeature: self.tag = tag # Index of the next item to be added (MUST INCREASE ON EVERY ADDITION!) self.next_elt_id = 0 + # Display order of the Subfeature + self.display_order = 0 # List of Verification Items in this feature: an OrderedDict. self.items = OrderedDict() @@ -312,6 +327,14 @@ class Subfeature: def get_item_names(self): return [item.name for item in self.items.values()] + def to_Prop(self): + """ + Convert a Subfeature into legacy-stype Prop object. + """ + result = Prop(self.name, self.tag, self.display_order) + result.list_of_items = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + return result + class Prop: """ A Property defines a specific behaviour or an IP section, to be tested/verified @@ -347,6 +370,7 @@ class Prop: if max_item_id >= self.item_count: raise ValueError((self.item_count, max_item_id)) result.next_elt_id = 1 + max_item_id + result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] result.items = OrderedDict(translated_items) return result @@ -471,10 +495,14 @@ class Feature: else: self.__class__._highest_id += 1 self.id = self.__class__._highest_id - # Index of the Feature (for display ordering) - #self.index = index + # Display order of the Feature + self.display_order = self.id # List of subfeatures self.subfeatures = OrderedDict() + self.vptool_gitrev = '' + self.io_fmt_gitrev = '' + self.config_gitrev = '' + self.ymlcfg_gitrev = '' def __str__(self): return format("## Feature: %s\n\n" % (self.name)) @@ -506,6 +534,17 @@ class Feature: def del_subfeature(self, name): del self.subfeatures[str(name)] + def to_Ip(self): + """ + Convert a Feature to a legacy-stype Ip. + """ + result = Ip(self.name) + result.wid_order = self.display_order + result.prop_list = [[elt[0], elt[1].toSubfeature()] for elt in self.subfeatures.items()] + for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: + setattr(result, attr, getattr(self, attr)) + return result + class Ip: """ An IP defines a bloc instantiated at chip top level, or more generally, a design specification chapter @@ -530,6 +569,10 @@ class Ip: self.rfu_list = [] self.rfu_list_0 = [] self.rfu_list_1 = [] + self.vptool_gitrev = '' + self.io_fmt_gitrev = '' + self.config_gitrev = '' + self.ymlcfg_gitrev = '' def to_Feature(self): """ @@ -539,8 +582,11 @@ class Ip: # Next_elf_it needs extra care as it is derived from the length of the list # of Properties / Subfeatures. result.next_elt_id = self.prop_count + result.display_order = self.wid_order translated_subfeatures = [[elt[0], elt[1].to_Subfeature()] for elt in (self.prop_list if self.prop_list else self.rfu_list)] result.subfeatures = OrderedDict(translated_subfeatures) + for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: + setattr(result, attr, getattr(self, attr)) return result def __str__(self): From 7858054ea7c275cca342d6068f4b227f6fbdd855 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 7 Dec 2022 14:52:06 +0100 Subject: [PATCH 029/183] axi_agent: first version of AXI4 passive agent Signed-off-by: Alae Eddine Ez zejjari --- .../uvma_axi/src/comps/uvma_axi_agent.sv | 75 +++++++++++++ .../uvma_axi_ar_agent/uvma_axi_ar_agent.sv | 35 ++++++ .../uvma_axi_ar_agent/uvma_axi_ar_mon.sv | 88 +++++++++++++++ .../uvma_axi_aw_agent/uvma_axi_aw_agent.sv | 37 +++++++ .../uvma_axi_aw_agent/uvma_axi_aw_mon.sv | 100 +++++++++++++++++ .../uvma_axi_b_agent/uvma_axi_b_agent.sv | 38 +++++++ .../comps/uvma_axi_b_agent/uvma_axi_b_mon.sv | 78 +++++++++++++ .../uvma_axi_r_agent/uvma_axi_r_agent.sv | 37 +++++++ .../comps/uvma_axi_r_agent/uvma_axi_r_mon.sv | 103 ++++++++++++++++++ .../uvma_axi_w_agent/uvma_axi_w_agent.sv | 37 +++++++ .../comps/uvma_axi_w_agent/uvma_axi_w_mon.sv | 79 ++++++++++++++ .../uvma_axi/src/obj/uvma_axi_cntxt.sv | 42 +++++++ .../uvma_axi/src/seq/uvma_axi_ar_item.sv | 47 ++++++++ .../uvma_axi/src/seq/uvma_axi_aw_item.sv | 57 ++++++++++ .../uvma_axi/src/seq/uvma_axi_b_item.sv | 40 +++++++ .../uvma_axi/src/seq/uvma_axi_r_item.sv | 42 +++++++ .../uvma_axi/src/seq/uvma_axi_w_item.sv | 40 +++++++ lib/uvm_agents/uvma_axi/src/uvma_axi_intf.sv | 102 +++++++++++++++++ .../uvma_axi/src/uvma_axi_macros.sv | 26 +++++ .../uvma_axi/src/uvma_axi_pkg.flist | 24 ++++ lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv | 65 +++++++++++ lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv | 21 ++++ 22 files changed, 1213 insertions(+) create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv create mode 100644 lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_item.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_item.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_intf.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_macros.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.flist create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv new file mode 100644 index 000000000..6722f2424 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv @@ -0,0 +1,75 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 (top) agent ****/ + +`ifndef __UVMA_AXI_AGENT_SV__ +`define __UVMA_AXI_AGENT_SV__ + +class uvma_axi_agent_c extends uvm_agent; + + `uvm_component_utils(uvma_axi_agent_c) + + uvma_axi_aw_agent_c aw_agent; + uvma_axi_w_agent_c w_agent; + uvma_axi_b_agent_c b_agent; + uvma_axi_ar_agent_c ar_agent; + uvma_axi_r_agent_c r_agent; + + uvma_axi_cntxt_c cntxt; + + function new(string name = "uvma_axi_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + get_and_set_cntxt(); + retrieve_vif (); + create_components(); + + endfunction : build_phase + + function void get_and_set_cntxt(); + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_info("CNTXT", "Context handle is null; creating", UVM_DEBUG) + cntxt = uvma_axi_cntxt_c::type_id::create("cntxt"); + end + uvm_config_db#(uvma_axi_cntxt_c)::set(this, "*", "cntxt", cntxt); + + endfunction : get_and_set_cntxt + + function void retrieve_vif(); + + if (!uvm_config_db#(virtual uvma_axi_intf)::get(this, "", "axi_vif", cntxt.axi_vi)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.axi_vi))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.axi_vi)), UVM_DEBUG) + end + + endfunction : retrieve_vif + + function void create_components(); + + this.aw_agent = uvma_axi_aw_agent_c :: type_id :: create("aw_agent", this); + this.w_agent = uvma_axi_w_agent_c :: type_id :: create("w_agent", this); + this.b_agent = uvma_axi_b_agent_c :: type_id :: create("b_agent", this); + this.ar_agent = uvma_axi_ar_agent_c :: type_id :: create("ar_agent", this); + this.r_agent = uvma_axi_r_agent_c :: type_id :: create("r_agent", this); + + endfunction : create_components + +endclass : uvma_axi_agent_c + +`endif //__UVMA_AXI_AGENT_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv new file mode 100644 index 000000000..41b056864 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv @@ -0,0 +1,35 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 agent for Read Address****/ + +`ifndef __UVMA_AXI_AR_AGENT_SV__ +`define __UVMA_AXI_AR_AGENT_SV__ + +class uvma_axi_ar_agent_c extends uvm_agent; + + uvma_axi_ar_mon_c monitor; + + `uvm_component_utils_begin(uvma_axi_ar_agent_c) + `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_component_utils_end + + function new(string name = "uvma_axi_ar_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + this.monitor = uvma_axi_ar_mon_c::type_id::create("monitor", this); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv new file mode 100644 index 000000000..42af17013 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv @@ -0,0 +1,88 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + + +`ifndef __UVMA_AXI_AR_MON_SV__ +`define __UVMA_AXI_AR_MON_SV__ + +class uvma_axi_ar_mon_c extends uvm_monitor; + + `uvm_component_utils(uvma_axi_ar_mon_c) + + uvma_axi_ar_item_c ar_item; + uvm_analysis_port#(uvma_axi_ar_item_c) uvma_ar_mon_port; + uvma_axi_cntxt_c cntxt; + + // Handles to virtual interface modport + virtual uvma_axi_intf.passive passive_mp; + + function new(string name = "uvma_axi_ar_mon_c", uvm_component parent); + super.new(name, parent); + this.uvma_ar_mon_port = new("uvma_ar_mon_port", this); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("build_phase", "monitor cntxt class failed") + end + + passive_mp = cntxt.axi_vi.passive; + + ar_item = uvma_axi_ar_item_c::type_id::create("ar_item", this); + + endfunction + + task run_phase(uvm_phase phase); + + super.run_phase(phase); + monitor_ar_items(); + + endtask: run_phase + + //Process for request from AR channel + task monitor_ar_items(); + + forever begin + if(this.passive_mp.psv_axi_cb.ar_valid) begin + // collect AR signals + `uvm_info(get_type_name(), $sformatf("read address, collect AR signals and send item"), UVM_HIGH) + this.ar_item.ar_id = passive_mp.psv_axi_cb.ar_id; + this.ar_item.ar_addr = passive_mp.psv_axi_cb.ar_addr; + this.ar_item.ar_len = passive_mp.psv_axi_cb.ar_len; + this.ar_item.ar_size = passive_mp.psv_axi_cb.ar_size; + this.ar_item.ar_burst = passive_mp.psv_axi_cb.ar_burst; + this.ar_item.ar_user = passive_mp.psv_axi_cb.ar_user; + this.ar_item.ar_valid = passive_mp.psv_axi_cb.ar_valid; + this.ar_item.ar_ready = passive_mp.psv_axi_cb.ar_ready; + this.ar_item.ar_lock = passive_mp.psv_axi_cb.ar_lock; + end else begin + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.ar_item.ar_id = 0; + this.ar_item.ar_addr = 0; + this.ar_item.ar_len = 0; + this.ar_item.ar_size = 0; + this.ar_item.ar_burst = 0; + this.ar_item.ar_user = 0; + this.ar_item.ar_valid = 0; + this.ar_item.ar_ready = 0; + this.ar_item.ar_lock = 0; + end + end + this.uvma_ar_mon_port.write(this.ar_item); + @(passive_mp.psv_axi_cb); + end + endtask: monitor_ar_items + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv new file mode 100644 index 000000000..a7a904d04 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv @@ -0,0 +1,37 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 agent for write address****/ + +`ifndef __UVMA_AXI_AW_AGENT_SV__ +`define __UVMA_AXI_AW_AGENT_SV__ + +class uvma_axi_aw_agent_c extends uvm_agent; + + uvma_axi_aw_mon_c monitor; + + `uvm_component_utils_begin(uvma_axi_aw_agent_c) + `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_component_utils_end + + function new(string name = "uvma_axi_aw_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + this.monitor = uvma_axi_aw_mon_c::type_id::create("monitor", this); + + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv new file mode 100644 index 000000000..eaef23da1 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv @@ -0,0 +1,100 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + + +`ifndef __UVMA_AXI_AW_MON_SV__ +`define __UVMA_AXI_AW_MON_SV__ + +class uvma_axi_aw_mon_c extends uvm_monitor; + + `uvm_component_utils(uvma_axi_aw_mon_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_aw_item_c aw_item; + + uvm_analysis_port #(uvma_axi_aw_item_c) uvma_aw_mon_port; + + // Handles to virtual interface modport + virtual uvma_axi_intf.passive passive_mp; + + function new(string name = "uvma_axi_aw_mon_c", uvm_component parent); + super.new(name, parent); + this.uvma_aw_mon_port = new("uvma_aw_mon_port", this); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("build_phase", "monitor cntxt class failed") + end + + passive_mp = cntxt.axi_vi.passive; + + this.aw_item = uvma_axi_aw_item_c::type_id::create("aw_item", this); + + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + this.monitor_aw_items(); + endtask: run_phase + + // Process for request from AW channel + task monitor_aw_items(); + + forever begin + if(passive_mp.psv_axi_cb.aw_valid) begin + // collect AW signals + `uvm_info(get_type_name(), $sformatf("write address, collect AW signals and send item"), UVM_HIGH) + this.aw_item.aw_id = passive_mp.psv_axi_cb.aw_id; + this.aw_item.aw_addr = passive_mp.psv_axi_cb.aw_addr; + this.aw_item.aw_len = passive_mp.psv_axi_cb.aw_len; + this.aw_item.aw_size = passive_mp.psv_axi_cb.aw_size; + this.aw_item.aw_burst = passive_mp.psv_axi_cb.aw_burst; + this.aw_item.aw_valid = passive_mp.psv_axi_cb.aw_valid; + this.aw_item.aw_ready = passive_mp.psv_axi_cb.aw_ready; + this.aw_item.aw_cache = passive_mp.psv_axi_cb.aw_cache; + this.aw_item.aw_user = passive_mp.psv_axi_cb.aw_user; + this.aw_item.aw_lock = passive_mp.psv_axi_cb.aw_lock; + this.aw_item.aw_prot = passive_mp.psv_axi_cb.aw_prot; + this.aw_item.aw_qos = passive_mp.psv_axi_cb.aw_qos; + this.aw_item.aw_region= passive_mp.psv_axi_cb.aw_region; + this.aw_item.aw_atop = passive_mp.psv_axi_cb.aw_atop; + end else begin + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.aw_item.aw_id = 0; + this.aw_item.aw_addr = 0; + this.aw_item.aw_len = 0; + this.aw_item.aw_size = 0; + this.aw_item.aw_burst = 0; + this.aw_item.aw_valid = 0; + this.aw_item.aw_ready = 0; + this.aw_item.aw_cache = 0; + this.aw_item.aw_user = 0; + this.aw_item.aw_lock = 0; + this.aw_item.aw_prot = 0; + this.aw_item.aw_qos = 0; + this.aw_item.aw_region= 0; + this.aw_item.aw_atop = 0; + end + end + this.uvma_aw_mon_port.write(this.aw_item); + @(passive_mp.psv_axi_cb); + end + + endtask: monitor_aw_items + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv new file mode 100644 index 000000000..3dde7702f --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv @@ -0,0 +1,38 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 agent for Write response ****/ + +`ifndef __UVMA_AXI_B_AGENT_SV__ +`define __UVMA_AXI_B_AGENT_SV__ + +class uvma_axi_b_agent_c extends uvm_agent; + + uvma_axi_b_mon_c monitor; + + `uvm_component_utils_begin(uvma_axi_b_agent_c) + `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_component_utils_end + + function new(string name = "uvma_axi_b_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + + this.monitor = uvma_axi_b_mon_c::type_id::create("monitor", this); + + endfunction + +endclass : uvma_axi_b_agent_c + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv new file mode 100644 index 000000000..12062c6e3 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv @@ -0,0 +1,78 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 B channel monitor ****/ + +`ifndef __UVMA_AXI_B_MON_SV__ +`define __UVMA_AXI_B_MON_SV__ + +class uvma_axi_b_mon_c extends uvm_monitor; + + `uvm_component_utils(uvma_axi_b_mon_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_b_item_c b_item; + + uvm_analysis_port #(uvma_axi_b_item_c) uvma_b_mon_port; + + // Handles to virtual interface modport + virtual uvma_axi_intf.passive passive_mp; + + extern function new(string name = "uvma_axi_b_mon_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task monitor_b_items(); +endclass:uvma_axi_b_mon_c + +function uvma_axi_b_mon_c::new(string name = "uvma_axi_b_mon_c", uvm_component parent); + super.new(name, parent); + this.uvma_b_mon_port = new("uvma_b_mon_port", this); +endfunction + +function void uvma_axi_b_mon_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("build_phase", "monitor cntxt class failed") + end + + passive_mp = cntxt.axi_vi.passive; + + this.b_item = uvma_axi_b_item_c::type_id::create("b_item", this); + +endfunction:build_phase + +task uvma_axi_b_mon_c::run_phase(uvm_phase phase); + super.run_phase(phase); + this.monitor_b_items(); +endtask: run_phase + +task uvma_axi_b_mon_c::monitor_b_items(); + + forever begin + + // collect b signals + `uvm_info(get_type_name(), $sformatf("response, collect resp signals from interface"), UVM_LOW) + this.b_item.b_id = passive_mp.psv_axi_cb.b_id; + this.b_item.b_resp = passive_mp.psv_axi_cb.b_resp; + this.b_item.b_user = passive_mp.psv_axi_cb.b_user; + this.b_item.b_valid = passive_mp.psv_axi_cb.b_valid; + this.b_item.b_ready = passive_mp.psv_axi_cb.b_ready; + this.uvma_b_mon_port.write(b_item); + @(passive_mp.psv_axi_cb); + + end + +endtask: monitor_b_items + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv new file mode 100644 index 000000000..e0651e5d9 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv @@ -0,0 +1,37 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 agent for read ****/ + +`ifndef __UVMA_AXI_R_AGENT_SV__ +`define __UVMA_AXI_R_AGENT_SV__ + +class uvma_axi_r_agent_c extends uvm_agent; + + uvma_axi_r_mon_c monitor; + + `uvm_component_utils_begin(uvma_axi_r_agent_c) + `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_component_utils_end + + function new(string name = "uvma_axi_r_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + monitor = uvma_axi_r_mon_c::type_id::create("monitor", this); + + endfunction + +endclass : uvma_axi_r_agent_c + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv new file mode 100644 index 000000000..4d14c2766 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv @@ -0,0 +1,103 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 monitor for R channel ****/ + +`ifndef __UVMA_AXI_R_MON_SV__ +`define __UVMA_AXI_R_MON_SV__ + +class uvma_axi_r_mon_c extends uvm_monitor; + + `uvm_component_utils(uvma_axi_r_mon_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_r_item_c r_item; + + uvm_analysis_port #(uvma_axi_r_item_c) uvma_r_mon_port; + + // Handles to virtual interface modport + virtual uvma_axi_intf.passive passive_mp; + + extern function new(string name = "uvma_axi_r_mon_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task monitor_r_items(); + extern task observe_reset(); + +endclass:uvma_axi_r_mon_c + +function uvma_axi_r_mon_c::new(string name = "uvma_axi_r_mon_c", uvm_component parent); + + super.new(name, parent); + uvma_r_mon_port = new("uvma_r_mon_port", this); + +endfunction + +function void uvma_axi_r_mon_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("build_phase", "monitor cntxt class failed") + end + + passive_mp = cntxt.axi_vi.passive; + + this.r_item = uvma_axi_r_item_c::type_id::create("r_item", this); + +endfunction + +task uvma_axi_r_mon_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + fork + this.observe_reset(); + this.monitor_r_items(); + join_none + +endtask: run_phase + +task uvma_axi_r_mon_c::monitor_r_items(); + forever begin + + // collect R signals + `uvm_info(get_type_name(), $sformatf("read data, collect resp signals from interface"), UVM_HIGH) + this.r_item.r_id = passive_mp.psv_axi_cb.r_id; + this.r_item.r_data = passive_mp.psv_axi_cb.r_data; + this.r_item.r_resp = passive_mp.psv_axi_cb.r_resp; + this.r_item.r_last = passive_mp.psv_axi_cb.r_last; + this.r_item.r_user = passive_mp.psv_axi_cb.r_user; + this.r_item.r_valid = passive_mp.psv_axi_cb.r_valid; + this.r_item.r_ready = passive_mp.psv_axi_cb.r_ready; + + this.uvma_r_mon_port.write(r_item); + @(passive_mp.psv_axi_cb); + + end + +endtask: monitor_r_items + +task uvma_axi_r_mon_c::observe_reset(); + + forever begin + + wait (cntxt.axi_vi.rst_n === 0); + cntxt.reset_state = UVMA_AXI_RESET_STATE_IN_RESET; + `uvm_info(get_type_name(), $sformatf("RESET_STATE_IN_RESET"), UVM_LOW) + wait (cntxt.axi_vi.rst_n === 1); + cntxt.reset_state = UVMA_AXI_RESET_STATE_POST_RESET; + `uvm_info(get_type_name(), $sformatf("RESET_STATE_POST_RESET"), UVM_LOW) + + end + +endtask : observe_reset + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv new file mode 100644 index 000000000..9ba854017 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv @@ -0,0 +1,37 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 W channel agent ****/ + +`ifndef __UVMA_AXI_W_AGENT_SV__ +`define __UVMA_AXI_W_AGENT_SV__ + +class uvma_axi_w_agent_c extends uvm_agent; + + uvma_axi_w_mon_c monitor; + + `uvm_component_utils_begin(uvma_axi_w_agent_c) + `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_component_utils_end + + function new(string name = "uvma_axi_w_agent_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + this.monitor = uvma_axi_w_mon_c::type_id::create("monitor", this); + + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv new file mode 100644 index 000000000..eb1fb3c4c --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv @@ -0,0 +1,79 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 W channel monitor ****/ + +`ifndef __UVMA_AXI_W_MON_SV__ +`define __UVMA_AXI_W_MON_SV__ + +class uvma_axi_w_mon_c extends uvm_monitor; + + `uvm_component_utils(uvma_axi_w_mon_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_w_item_c w_item; + + uvm_analysis_port #(uvma_axi_w_item_c) uvma_w_mon_port; + + // Handles to virtual interface modport + virtual uvma_axi_intf.passive passive_mp; + + extern function new(string name = "uvma_axi_w_mon_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task monitor_w_items(); + +endclass:uvma_axi_w_mon_c + +function uvma_axi_w_mon_c::new(string name = "uvma_axi_w_mon_c", uvm_component parent); + + super.new(name, parent); + uvma_w_mon_port = new("uvma_w_mon_port", this); + +endfunction + +function void uvma_axi_w_mon_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("build_phase", "monitor cntxt class failed") + end + + passive_mp = cntxt.axi_vi.passive; + + w_item = uvma_axi_w_item_c::type_id::create("w_item", this); + +endfunction + +task uvma_axi_w_mon_c::run_phase(uvm_phase phase); + super.run_phase(phase); + monitor_w_items(); +endtask: run_phase + +// Process for request from W channel +task uvma_axi_w_mon_c::monitor_w_items(); + forever begin + `uvm_info(get_type_name(), $sformatf("write data, monitor DUT response and send data"), UVM_HIGH) + w_item.w_strb = passive_mp.psv_axi_cb.w_strb; + w_item.w_data = passive_mp.psv_axi_cb.w_data; + w_item.w_last = passive_mp.psv_axi_cb.w_last; + w_item.w_user = passive_mp.psv_axi_cb.w_user; + w_item.w_valid = passive_mp.psv_axi_cb.w_valid; + w_item.w_ready = passive_mp.psv_axi_cb.w_ready; + this.uvma_w_mon_port.write(this.w_item); + @(passive_mp.psv_axi_cb); + end + +endtask: monitor_w_items + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv new file mode 100644 index 000000000..b11bbbb04 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv @@ -0,0 +1,42 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +`ifndef __UVMA_AXI_CNTXT_SV__ +`define __UVMA_AXI_CNTXT_SV__ + +/** + * Object encapsulating all state variables for all AXI agent + * (uvma_axi_agent_c) components. + */ +class uvma_axi_cntxt_c extends uvm_object; + + // Handle to agent interface + virtual uvma_axi_intf axi_vi; + + uvma_axi_reset_state_enum reset_state = UVMA_AXI_RESET_STATE_PRE_RESET; + + `uvm_object_utils_begin(uvma_axi_cntxt_c) + `uvm_field_enum(uvma_axi_reset_state_enum, reset_state, UVM_DEFAULT) + `uvm_object_utils_end + /** + * Builds events. + */ + extern function new(string name = "uvma_axi_cntxt"); + +endclass : uvma_axi_cntxt_c + + +function uvma_axi_cntxt_c::new(string name = "uvma_axi_cntxt"); + + super.new(name); + +endfunction : new + +`endif // __UVMA_AXI_CNTXT_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv new file mode 100644 index 000000000..e4a2baec8 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv @@ -0,0 +1,47 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 sequence item : Read Address channel ****/ + + +`ifndef __UVMA_AXI_AR_ITEM_SV__ +`define __UVMA_AXI_AR_ITEM_SV__ + +class uvma_axi_ar_item_c extends uvm_sequence_item; + + rand logic [AXI_ID_WIDTH-1:0] ar_id; + rand logic [AXI_ADDR_WIDTH-1:0] ar_addr; + rand logic [7:0] ar_len; + rand logic [2:0] ar_size; + rand logic [1:0] ar_burst; + rand logic [1:0] ar_user; + rand logic ar_valid; + rand logic ar_ready; + rand logic ar_lock; + + `uvm_object_utils_begin(uvma_axi_ar_item_c) + `uvm_field_int(ar_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_addr, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_len, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_size, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_burst, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_user, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_lock, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + function new(string name = "uvma_axi_ar_item_c"); + super.new(name); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv new file mode 100644 index 000000000..a6b757bdc --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv @@ -0,0 +1,57 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 sequence item : Write address channel ****/ + +`ifndef __UVMA_AXI_AW_ITEM_SV__ +`define __UVMA_AXI_AW_ITEM_SV__ + + +class uvma_axi_aw_item_c extends uvm_sequence_item; + + rand logic [AXI_ID_WIDTH-1:0] aw_id; + rand logic [AXI_ADDR_WIDTH-1:0] aw_addr; + rand logic [AXI_USER_WIDTH-1:0] aw_user; + rand logic [7:0] aw_len; + rand logic [2:0] aw_size; + rand logic [1:0] aw_burst; + rand logic aw_valid; + rand logic aw_ready; + rand logic [3:0] aw_cache; + rand logic aw_lock; + rand logic [2:0] aw_prot; + rand logic [3:0] aw_qos; + rand logic [3:0] aw_region; + rand logic [5:0] aw_atop; + + `uvm_object_utils_begin(uvma_axi_aw_item_c) + `uvm_field_int(aw_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_addr, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_len, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_size, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_burst, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_cache, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_user, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_lock, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_prot, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_qos, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_region, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_atop, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + function new(string name = "uvma_axi_aw_item_c"); + super.new(name); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_item.sv new file mode 100644 index 000000000..06f54578a --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_item.sv @@ -0,0 +1,40 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 sequence item : Write response channel ****/ + +`ifndef __UVMA_AXI_B_ITEM_SV__ +`define __UVMA_AXI_B_ITEM_SV__ + +class uvma_axi_b_item_c extends uvm_sequence_item; + + rand logic [AXI_ID_WIDTH-1:0] b_id; + rand logic [1:0] b_resp; + rand logic [1:0] b_user; + rand logic b_valid; + rand logic b_ready; + + `uvm_object_param_utils_begin(uvma_axi_b_item_c) + `uvm_field_int(b_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_resp, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_user, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + function new(string name = "uvma_axi_b_item_c"); + super.new(name); + endfunction + +endclass + +`endif + + diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_item.sv new file mode 100644 index 000000000..091e44155 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_item.sv @@ -0,0 +1,42 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 sequence item : Read data channel ****/ + +`ifndef __UVMA_AXI_R_ITEM_SV__ +`define __UVMA_AXI_R_ITEM_SV__ + +class uvma_axi_r_item_c extends uvm_sequence_item; + + rand logic [AXI_ID_WIDTH-1:0] r_id; + rand logic [AXI_ADDR_WIDTH-1:0] r_data; + rand logic [1:0] r_resp; + rand logic r_last; + rand logic r_user; + rand logic r_valid; + logic r_ready; + + `uvm_object_utils_begin(uvma_axi_r_item_c) + `uvm_field_int(r_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_data, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_resp, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_last, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_user, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + function new(string name = "uvma_axi_r_item_c"); + super.new(name); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv new file mode 100644 index 000000000..76e23da1d --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv @@ -0,0 +1,40 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 sequence item : Write data channel****/ + +`ifndef __UVMA_AXI_W_ITEM_SV__ +`define __UVMA_AXI_W_ITEM_SV__ + +class uvma_axi_w_item_c extends uvm_sequence_item; + + rand logic [AXI_DATA_WIDTH/8-1:0] w_strb; + rand logic [AXI_DATA_WIDTH-1:0] w_data; + rand logic w_last; + rand logic w_user; + rand logic w_valid; + rand logic w_ready; + + `uvm_object_param_utils_begin(uvma_axi_w_item_c) + `uvm_field_int(w_strb, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_data, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_last, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_user, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + function new(string name = "uvma_axi_w_item_c"); + super.new(name); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_intf.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_intf.sv new file mode 100644 index 000000000..9c72e4a4d --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_intf.sv @@ -0,0 +1,102 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 interface with parametrized : ****/ + +interface uvma_axi_intf #( + parameter AXI_ADDR_WIDTH = `UVMA_AXI_ADDR_MAX_WIDTH, + parameter AXI_DATA_WIDTH = `UVMA_AXI_DATA_MAX_WIDTH, + parameter AXI_USER_WIDTH = `UVMA_AXI_USER_MAX_WIDTH, + parameter AXI_ID_WIDTH = `UVMA_AXI_ID_MAX_WIDTH +) (input bit clk, bit rst_n); + + // AXI4 signals + // Write Address channel + logic [AXI_ID_WIDTH-1:0] aw_id; + logic [AXI_ADDR_WIDTH-1:0] aw_addr; + logic [AXI_USER_WIDTH-1:0] aw_user; + logic [7:0] aw_len; + logic [2:0] aw_size; + logic [1:0] aw_burst; + logic aw_lock; + logic [3:0] aw_cache; + logic [2:0] aw_prot; + logic [3:0] aw_qos; + logic [3:0] aw_region; + logic aw_valid; + logic aw_ready; + logic [5:0] aw_atop; + + //write data channel + logic [AXI_DATA_WIDTH-1:0] w_data; + logic [AXI_DATA_WIDTH/8-1:0] w_strb; + logic [AXI_USER_WIDTH-1:0] w_user; + logic w_last; + logic w_valid; + logic w_ready; + + // write response channel + logic [AXI_ID_WIDTH-1:0] b_id; + logic [AXI_USER_WIDTH-1:0] b_user; + logic [1:0] b_resp; + logic b_valid; + logic b_ready; + + // read address channel + logic [AXI_ID_WIDTH-1:0] ar_id; + logic [AXI_ADDR_WIDTH-1:0] ar_addr; + logic [AXI_USER_WIDTH-1:0] ar_user; + logic [7:0] ar_len; + logic [2:0] ar_size; + logic [1:0] ar_burst; + logic ar_lock; + logic [3:0] ar_cache; + logic [2:0] ar_prot; + logic [3:0] ar_qos; + logic [3:0] ar_region; + logic ar_valid; + logic ar_ready; + + //read data channel + logic [AXI_ID_WIDTH-1:0] r_id; + logic [AXI_DATA_WIDTH-1:0] r_data; + logic [AXI_USER_WIDTH-1:0] r_user; + logic [1:0] r_resp; + logic r_last; + logic r_valid; + logic r_ready; + + + + clocking slv_axi_cb @(posedge clk or rst_n); + output ar_ready, + r_id, r_data, r_resp, r_last, r_valid, r_user, + aw_ready, + w_ready, + b_id, b_resp, b_user, b_valid; + input ar_id, ar_addr, ar_user, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_valid, + r_ready, + aw_id, aw_addr, aw_user, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_valid, aw_atop, + w_data, w_strb, w_last, w_user, w_valid, + b_ready; + endclocking: slv_axi_cb + + clocking psv_axi_cb @(posedge clk or rst_n); + input ar_id, ar_addr, ar_user, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_valid, ar_ready, + r_ready, r_id, r_data, r_resp, r_user, r_last, r_valid, + aw_id, aw_addr, aw_user, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_valid, aw_atop, aw_ready, + w_data, w_strb, w_last, w_user, w_valid, w_ready, + b_id, b_resp, b_user, b_valid, b_ready; + endclocking: psv_axi_cb + + modport slave (clocking slv_axi_cb); + modport passive (clocking psv_axi_cb); + +endinterface : uvma_axi_intf diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_macros.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_macros.sv new file mode 100644 index 000000000..d4f12190f --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_macros.sv @@ -0,0 +1,26 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +`ifndef __UVMA_AXI_MACROS_SV__ +`define __UVMA_AXI_MACROS_SV__ + + parameter Nr_Slaves = 2; // actually masters, but slaves on the crossbar + parameter Id_Width = 4; // 4 is recommended by AXI standard, so lets stick to it, do not change + parameter Id_Width_Slave = Id_Width + $clog2(Nr_Slaves); + + `define UVMA_AXI_ADDR_MAX_WIDTH 64 + `define UVMA_AXI_DATA_MAX_WIDTH 64 + `define UVMA_AXI_USER_MAX_WIDTH 1 + `define UVMA_AXI_ID_MAX_WIDTH Id_Width_Slave + `define UVMA_AXI_STRB_MAX_WIDTH 8 + + `define per_instance_fcov `ifndef DSIM option.per_instance = 1; `endif + +`endif // __UVMA_AXI_MACROS_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.flist b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.flist new file mode 100644 index 000000000..ed8dae1fd --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.flist @@ -0,0 +1,24 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// Directories ++incdir+${DV_UVMA_AXI_PATH} ++incdir+${DV_UVMA_AXI_PATH}/src ++incdir+${DV_UVMA_AXI_PATH}/src/obj ++incdir+${DV_UVMA_AXI_PATH}/src/seq ++incdir+${DV_UVMA_AXI_PATH}/src/comps ++incdir+${DV_UVMA_AXI_PATH}/src/comps/uvma_axi_aw_agent ++incdir+${DV_UVMA_AXI_PATH}/src/comps/uvma_axi_w_agent ++incdir+${DV_UVMA_AXI_PATH}/src/comps/uvma_axi_b_agent ++incdir+${DV_UVMA_AXI_PATH}/src/comps/uvma_axi_ar_agent ++incdir+${DV_UVMA_AXI_PATH}/src/comps/uvma_axi_r_agent + +// Files +${DV_UVMA_AXI_PATH}/src/uvma_axi_pkg.sv diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv new file mode 100644 index 000000000..ddcd92d1d --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv @@ -0,0 +1,65 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/***** AXI4 slave agent package *****/ + +`ifndef __UVMA_AXI_PKG_SV__ +`define __UVMA_AXI_PKG_SV__ + +// Pre-processor macros +`include "uvm_macros.svh" +`include "uvma_axi_macros.sv" + + +// Interfaces / Modules / Checkers +`include "uvma_axi_intf.sv" + +package uvma_axi_pkg; + + import uvm_pkg::*; + + localparam NrSlaves = 2; // actually masters, but slaves on the crossbar + localparam IdWidth = 4; // 4 is recommended by AXI standard, so lets stick to it, do not change + localparam IdWidthSlave = IdWidth + $clog2(NrSlaves); + parameter AXI_ADDR_WIDTH = `UVMA_AXI_ADDR_MAX_WIDTH; + parameter AXI_DATA_WIDTH = `UVMA_AXI_DATA_MAX_WIDTH; + parameter AXI_USER_WIDTH = `UVMA_AXI_USER_MAX_WIDTH; + parameter AXI_ID_WIDTH = IdWidthSlave; + parameter NUM_WORDS = 2**24; + + `include "uvma_axi_tdefs.sv" + + // Objects + `include "uvma_axi_cntxt.sv" + + `include "uvma_axi_aw_item.sv" + `include "uvma_axi_w_item.sv" + `include "uvma_axi_b_item.sv" + `include "uvma_axi_ar_item.sv" + `include "uvma_axi_r_item.sv" + + `include "uvma_axi_aw_mon.sv" + `include "uvma_axi_w_mon.sv" + `include "uvma_axi_b_mon.sv" + `include "uvma_axi_ar_mon.sv" + `include "uvma_axi_r_mon.sv" + + + `include "uvma_axi_aw_agent.sv" + `include "uvma_axi_w_agent.sv" + `include "uvma_axi_b_agent.sv" + `include "uvma_axi_ar_agent.sv" + `include "uvma_axi_r_agent.sv" + + `include "uvma_axi_agent.sv" + +endpackage : uvma_axi_pkg + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv new file mode 100644 index 000000000..0b996ce01 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv @@ -0,0 +1,21 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +`ifndef __UVMA_AXI_TDEFS_SV__ +`define __UVMA_AXI_TDEFS_SV__ + + + typedef enum { + UVMA_AXI_RESET_STATE_PRE_RESET, + UVMA_AXI_RESET_STATE_IN_RESET, + UVMA_AXI_RESET_STATE_POST_RESET + } uvma_axi_reset_state_enum; + +`endif // __UVMA_AXI_TDEFS_SV__ From 64513851d017736c2ba3832bd90159308a6c7f4b Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 7 Dec 2022 15:15:42 +0100 Subject: [PATCH 030/183] axi_agent: connect AXI passive agent to cva6 Signed-off-by: Alae Eddine Ez zejjari --- cva6/env/uvme/uvme_cva6_cntxt.sv | 3 ++ cva6/env/uvme/uvme_cva6_env.sv | 3 ++ cva6/env/uvme/uvme_cva6_pkg.sv | 1 + cva6/sim/Makefile | 1 + cva6/tb/uvmt/cva6_tb_wrapper.sv | 53 +++++++++++++++++++++++++++++- cva6/tb/uvmt/uvmt_cva6.flist | 1 + cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv | 4 +++ cva6/tb/uvmt/uvmt_cva6_tb.sv | 6 ++++ 8 files changed, 71 insertions(+), 1 deletion(-) diff --git a/cva6/env/uvme/uvme_cva6_cntxt.sv b/cva6/env/uvme/uvme_cva6_cntxt.sv index 3434ef38a..7973f1869 100644 --- a/cva6/env/uvme/uvme_cva6_cntxt.sv +++ b/cva6/env/uvme/uvme_cva6_cntxt.sv @@ -30,6 +30,7 @@ class uvme_cva6_cntxt_c extends uvm_object; // Agent context handles uvma_clknrst_cntxt_c clknrst_cntxt; uvma_cvxif_cntxt_c cvxif_cntxt; + uvma_axi_cntxt_c axi_cntxt; // Events uvm_event sample_cfg_e; @@ -38,6 +39,7 @@ class uvme_cva6_cntxt_c extends uvm_object; `uvm_object_utils_begin(uvme_cva6_cntxt_c) `uvm_field_object(clknrst_cntxt, UVM_DEFAULT) + `uvm_field_object(axi_cntxt, UVM_DEFAULT) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) `uvm_object_utils_end @@ -56,6 +58,7 @@ function uvme_cva6_cntxt_c::new(string name="uvme_cva6_cntxt"); super.new(name); clknrst_cntxt = uvma_clknrst_cntxt_c::type_id::create("clknrst_cntxt"); + axi_cntxt = uvma_axi_cntxt_c::type_id::create("axi_cntxt"); sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); diff --git a/cva6/env/uvme/uvme_cva6_env.sv b/cva6/env/uvme/uvme_cva6_env.sv index 08b86f20a..ed22eba52 100644 --- a/cva6/env/uvme/uvme_cva6_env.sv +++ b/cva6/env/uvme/uvme_cva6_env.sv @@ -41,6 +41,7 @@ class uvme_cva6_env_c extends uvm_env; // Agents uvma_clknrst_agent_c clknrst_agent; uvma_cvxif_agent_c cvxif_agent; + uvma_axi_agent_c axi_agent; @@ -209,6 +210,7 @@ function void uvme_cva6_env_c::assign_cntxt(); uvm_config_db#(uvme_cva6_cntxt_c)::set(this, "*", "cntxt", cntxt); uvm_config_db#(uvma_clknrst_cntxt_c)::set(this, "clknrst_agent", "cntxt", cntxt.clknrst_cntxt); + uvm_config_db#(uvma_axi_cntxt_c)::set(this, "axi_agent", "cntxt", cntxt.axi_cntxt); endfunction: assign_cntxt @@ -217,6 +219,7 @@ function void uvme_cva6_env_c::create_agents(); clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); cvxif_agent = uvma_cvxif_agent_c::type_id::create("cvxif_agent", this); + axi_agent = uvma_axi_agent_c::type_id::create("axi_agent", this); endfunction: create_agents diff --git a/cva6/env/uvme/uvme_cva6_pkg.sv b/cva6/env/uvme/uvme_cva6_pkg.sv index bde6e08f1..ea93a206e 100644 --- a/cva6/env/uvme/uvme_cva6_pkg.sv +++ b/cva6/env/uvme/uvme_cva6_pkg.sv @@ -43,6 +43,7 @@ package uvme_cva6_pkg; import uvml_trn_pkg ::*; import uvma_clknrst_pkg::*; import uvma_cvxif_pkg::*; + import uvma_axi_pkg::*; // Constants / Structs / Enums `include "uvme_cva6_constants.sv" diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index bcceaee51..bb8bd4231 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -140,6 +140,7 @@ export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst export DV_UVMA_CVXIF_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_cvxif +export DV_UVMA_AXI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_axi export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug export DV_UVMA_OBI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi diff --git a/cva6/tb/uvmt/cva6_tb_wrapper.sv b/cva6/tb/uvmt/cva6_tb_wrapper.sv index 7debb4571..f1d740430 100644 --- a/cva6/tb/uvmt/cva6_tb_wrapper.sv +++ b/cva6/tb/uvmt/cva6_tb_wrapper.sv @@ -46,7 +46,8 @@ module cva6_tb_wrapper #( output wire tb_exit_o, output ariane_rvfi_pkg::rvfi_port_t rvfi_o, input cvxif_pkg::cvxif_resp_t cvxif_resp, - output cvxif_pkg::cvxif_req_t cvxif_req + output cvxif_pkg::cvxif_req_t cvxif_req, + uvma_axi_intf axi_slave ); ariane_axi::req_t axi_ariane_req; @@ -156,6 +157,56 @@ module cva6_tb_wrapper #( .rdata_o ( rdata ) ); + // AW Channel + assign axi_slave.aw_valid = cva6_axi_bus.aw_valid; + assign axi_slave.aw_ready = cva6_axi_bus.aw_ready; + assign axi_slave.aw_id = cva6_axi_bus.aw_id; + assign axi_slave.aw_addr = cva6_axi_bus.aw_addr; + assign axi_slave.aw_len = cva6_axi_bus.aw_len; + assign axi_slave.aw_size = cva6_axi_bus.aw_size; + assign axi_slave.aw_burst = cva6_axi_bus.aw_burst; + assign axi_slave.aw_lock = cva6_axi_bus.aw_lock; + assign axi_slave.aw_cache = cva6_axi_bus.aw_cache; + assign axi_slave.aw_prot = cva6_axi_bus.aw_prot; + assign axi_slave.aw_qos = cva6_axi_bus.aw_qos; + assign axi_slave.aw_region = cva6_axi_bus.aw_region; + assign axi_slave.aw_user = cva6_axi_bus.aw_user; + assign axi_slave.aw_atop = cva6_axi_bus.aw_atop; + // W Channel + assign axi_slave.w_valid = cva6_axi_bus.w_valid; + assign axi_slave.w_ready = cva6_axi_bus.w_ready; + assign axi_slave.w_data = cva6_axi_bus.w_data; + assign axi_slave.w_strb = cva6_axi_bus.w_strb; + assign axi_slave.w_last = cva6_axi_bus.w_last; + assign axi_slave.w_user = cva6_axi_bus.w_user; + // B Channel + assign axi_slave.b_valid = cva6_axi_bus.b_valid; + assign axi_slave.b_ready = cva6_axi_bus.b_ready; + assign axi_slave.b_id = cva6_axi_bus.b_id; + assign axi_slave.b_resp = cva6_axi_bus.b_resp; + assign axi_slave.b_user = cva6_axi_bus.b_user; + // AR Channel + assign axi_slave.ar_valid = cva6_axi_bus.ar_valid; + assign axi_slave.ar_ready = cva6_axi_bus.ar_ready; + assign axi_slave.ar_id = cva6_axi_bus.ar_id; + assign axi_slave.ar_addr = cva6_axi_bus.ar_addr; + assign axi_slave.ar_len = cva6_axi_bus.ar_len; + assign axi_slave.ar_size = cva6_axi_bus.ar_size; + assign axi_slave.ar_burst = cva6_axi_bus.ar_burst; + assign axi_slave.ar_lock = cva6_axi_bus.ar_lock; + assign axi_slave.ar_cache = cva6_axi_bus.ar_cache; + assign axi_slave.ar_prot = cva6_axi_bus.ar_prot; + assign axi_slave.ar_qos = cva6_axi_bus.ar_qos; + assign axi_slave.ar_region = cva6_axi_bus.ar_region; + assign axi_slave.ar_user = cva6_axi_bus.ar_user; + // R Channel + assign axi_slave.r_valid = cva6_axi_bus.r_valid; + assign axi_slave.r_ready = cva6_axi_bus.r_ready; + assign axi_slave.r_id = cva6_axi_bus.r_id; + assign axi_slave.r_data = cva6_axi_bus.r_data; + assign axi_slave.r_resp = cva6_axi_bus.r_resp; + assign axi_slave.r_last = cva6_axi_bus.r_last; + assign axi_slave.r_user = cva6_axi_bus.r_user; initial begin automatic logic [7:0][7:0] mem_row; longint address; diff --git a/cva6/tb/uvmt/uvmt_cva6.flist b/cva6/tb/uvmt/uvmt_cva6.flist index 49cf15562..d70c0ab92 100644 --- a/cva6/tb/uvmt/uvmt_cva6.flist +++ b/cva6/tb/uvmt/uvmt_cva6.flist @@ -23,6 +23,7 @@ // Agents -f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist -f ${DV_UVMA_CVXIF_PATH}/src/uvma_cvxif_pkg.flist +-f ${DV_UVMA_AXI_PATH}/src/uvma_axi_pkg.flist // Environments -f ${CVA6_UVME_PATH}/uvme_cva6_pkg.flist diff --git a/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv b/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv index ebbd213e5..973c8e7db 100644 --- a/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv +++ b/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -24,10 +24,13 @@ module uvmt_cva6_dut_wrap # ( parameter int unsigned AXI_USER_WIDTH = 1, ( uvma_clknrst_if clknrst_if, uvma_cvxif_intf cvxif_if, + uvma_axi_intf axi_if, output wire tb_exit_o, output ariane_rvfi_pkg::rvfi_port_t rvfi_o ); + + cva6_tb_wrapper #( .AXI_USER_WIDTH (AXI_USER_WIDTH), .AXI_USER_EN (AXI_USER_EN), @@ -40,6 +43,7 @@ module uvmt_cva6_dut_wrap # ( parameter int unsigned AXI_USER_WIDTH = 1, .rst_ni ( clknrst_if.reset_n ), .cvxif_resp ( cvxif_if.cvxif_resp_o ), .cvxif_req ( cvxif_if.cvxif_req_i ), + .axi_slave ( axi_if ), .tb_exit_o ( tb_exit_o ), .rvfi_o ( rvfi_o ) ); diff --git a/cva6/tb/uvmt/uvmt_cva6_tb.sv b/cva6/tb/uvmt/uvmt_cva6_tb.sv index 9f402ac9b..8fedee7c1 100644 --- a/cva6/tb/uvmt/uvmt_cva6_tb.sv +++ b/cva6/tb/uvmt/uvmt_cva6_tb.sv @@ -47,6 +47,10 @@ module uvmt_cva6_tb; .clk(clknrst_if.clk), .reset_n(clknrst_if.reset_n) ); // cvxif from the cvxif agent + uvma_axi_intf axi_if( + .clk(clknrst_if.clk), + .rst_n(clknrst_if.reset_n) + ); //bind assertion module for cvxif interface bind uvmt_cva6_dut_wrap @@ -72,6 +76,7 @@ module uvmt_cva6_tb; ) cva6_dut_wrap ( .clknrst_if(clknrst_if), .cvxif_if (cvxif_if), + .axi_if (axi_if), .tb_exit_o(), .rvfi_o(rvfi_if.rvfi_o) ); @@ -88,6 +93,7 @@ module uvmt_cva6_tb; // Add interfaces handles to uvm_config_db uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if)); uvm_config_db#(virtual uvma_cvxif_intf )::set(.cntxt(null), .inst_name("*.env.cvxif_agent"), .field_name("vif"), .value(cvxif_if) ); + uvm_config_db#(virtual uvma_axi_intf )::set(.cntxt(null), .inst_name("*"), .field_name("axi_vif"), .value(axi_if)); uvm_config_db#(virtual uvmt_rvfi_if )::set(.cntxt(null), .inst_name("*"), .field_name("rvfi_vif"), .value(rvfi_if)); // DUT and ENV parameters From f9e7cfcdbeefd70d60584a3f5847185e4cd94b41 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Thu, 9 Feb 2023 10:19:17 +0100 Subject: [PATCH 031/183] VPTOOL: Revert Pickle output to protocol 0. Add stable roundtrip Yaml I/O. * tooos/vptool/vptool/vp.py (MyMain.save_db): Revert to human-readable version of Pickle protocol. Change default Yaml files to 'VP_IPnnn.yml'. (MyMain.load_db_quiet): Add arg 'use_yaml_input' to switch between Pickle and Yaml input. Change default Yaml files to 'VP_IPnnn.yml'. Process input according to chosen input mode (Pickle/Yaml). (MyMain.lock_all_ip): Revert to human-readable version of Pickle protocol. (MyMain.create_gui): Add arg 'use_yaml_input' to select load mode. (toplevel): Add '-y'/'--yaml' option to cmdline options. Pass choice to GUI creation. * tools/vptool/vptool/vp_pack.py (Subfeature.to_Prop): Set item_count. Populate rfu_list. Fix name of list of items. (Prop.to_Subfeature): Add debug message (commented out). Accept item count as is. (Feature._highest_id): Rename to '_feature_count'. Start from 0, not -1. (Feature.__init__): Set default value of 'id' arg to "" and check for default ID accordingly, so 0 becomes a valid non-default ID. (Feature.to_Ip): Map id to ip_num. Correctly populate the rfu_list and the prop_list attributes. (Ip.__init__): Check for default index by comparing against default value instead of checking for falseness. Add debug message (commented out). (Ip.to_Feature): Add comment. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 78 ++++++++++++++++++++-------------- tools/vptool/vptool/vp_pack.py | 37 ++++++++-------- 2 files changed, 64 insertions(+), 51 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index 900ed0905..755afe774 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -1977,7 +1977,7 @@ class MyMain: + ".pck", "wb", ) as output: - pickle.dump(ip_elt, output, 4) + pickle.dump(ip_elt, output, 0) # TODO: Add translation of pickle_ip_list to new-gen # types *HERE*, after emitting Pickle. # Emit the Yaml output from the fixed structures, @@ -1987,7 +1987,7 @@ class MyMain: save_dir + "/VP_IP" + str(ip_elt[1].ip_num).zfill(3) - + "_new_types.yml", + + ".yml", "wb", ) as output: db_yaml_engine.dump(ip_elt[1].to_Feature(), output) @@ -2010,9 +2010,9 @@ class MyMain: else: # ZC FIXME Add support for Yaml in non-split-save mode. with open(vp_config.SAVED_DB_LOCATION, "wb") as output: - pickle.dump(len(pickle_ip_list), output, 4) + pickle.dump(len(pickle_ip_list), output, 0) for ip_elt in pickle_ip_list: - pickle.dump(ip_elt, output, 4) + pickle.dump(ip_elt, output, 0) self.prep_db_import() # update_ip_widget() self.update_all_item_target_list() @@ -2057,7 +2057,7 @@ class MyMain: tkinter.messagebox.showwarning("Warning", "No DB Loaded!") return need_to_load - def load_db_quiet(self): + def load_db_quiet(self, use_yaml_input=False): pickle_ip_list = [] ip_num_next = 0 if self.split_save: @@ -2073,16 +2073,18 @@ class MyMain: else "" ) + ")", - os.path.join(dir_to_load, "VP_IP*.pck"), + os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].pck"), ) ) - for filename in glob.glob(dir_to_load + "/VP_IP*pck"): - # print("---INFO: Loading "+filename) - with open(filename, "rb") as input: - pickle_ip_list.append(pickle.load(input)) - #for filename in glob.glob(dir_to_load + "/VP_IP*yml"): - # with open(filename, "rb") as input: - # pickle_ip_list.append(db_yaml_engine.load(input)) + if not use_yaml_input: + for filename in glob.glob(dir_to_load + "/VP_IP*pck"): + # print("---INFO: Loading "+filename) + with open(filename, "rb") as input: + pickle_ip_list.append(pickle.load(input)) + else: + for filename in glob.glob(dir_to_load + "/VP_IP[0-9][0-9][0-9].yml"): + with open(filename, "rb") as input: + pickle_ip_list.append(db_yaml_engine.load(input)) if pickle_ip_list: # Find the lowest ip_num that can be used for newly created IPs. # It has to be higher than the highest existing ip_num. @@ -2090,8 +2092,8 @@ class MyMain: ip_num_next = 1 + max( [ (lambda e: e if isinstance(e, int) else int(e, base=10))( - #elt.ip_num # Yaml !!omap mode: list of objects - elt[1].ip_num + elt.id if use_yaml_input # Yaml !!omap mode: list of objects + else elt[1].ip_num ) for elt in pickle_ip_list ] @@ -2109,16 +2111,18 @@ class MyMain: for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict - # Yaml mode: !!omap yields a list of elts when loaded. - #for ip_elt in pickle_ip_list: - # self.ip_list[ip_elt.name] = ip_elt - # # Seems pickle doesn't restore class attribute. Done manually here for IP - # self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next - # Pickle mode: list of objects is a list of mappings - for ip_key, ip_elt in pickle_ip_list: - self.ip_list[ip_key] = ip_elt - # Seems pickle doesn't restore class attribute. Done manually here for IP - self.ip_list[ip_key].__class__._ip_count = ip_num_next + if use_yaml_input: + # Yaml mode: !!omap yields a list of elts when loaded. + for ip_elt in pickle_ip_list: + self.ip_list[ip_elt.name] = ip_elt.to_Ip() + # Seems pickle doesn't restore class attribute. Done manually here for IP + self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next + else: + # Pickle mode: list of objects is a list of mappings as 2-elt lists + for ip_key, ip_elt in pickle_ip_list: + self.ip_list[ip_key] = ip_elt + # Seems pickle doesn't restore class attribute. Done manually here for IP + self.ip_list[ip_key].__class__._ip_count = ip_num_next self.prep_db_import() self.update_all_item_target_list() self.db_git_rev = self.get_db_gitrev() @@ -2177,7 +2181,7 @@ class MyMain: LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 4) + pickle.dump(LOCKED_IP_DICT, output, 0) self.update_ip_widget() except Exception as e: print( @@ -2200,7 +2204,7 @@ class MyMain: LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 4) + pickle.dump(LOCKED_IP_DICT, output, 0) self.update_ip_widget() except Exception as e: print( @@ -2279,9 +2283,9 @@ class MyMain: if os.path.exists(sys.argv[0]): preference_file = os.path.dirname(sys.argv[0]) + "/" + PERSO_FILE with open(preference_file, "wb") as output: - pickle.dump(BG_COLOR, output, 4) - pickle.dump(EDITOR, output, 4) - pickle.dump(self.verif_menu.enable_image_panel.get(), output, 4) + pickle.dump(BG_COLOR, output, 0) + pickle.dump(EDITOR, output, 0) + pickle.dump(self.verif_menu.enable_image_panel.get(), output, 0) def change_gui_color(self): global BG_COLOR @@ -2342,7 +2346,7 @@ class MyMain: ##### DB INTERACTIION FUNCTIONS ##### Main GUI Creation - def create_gui(self, theme): + def create_gui(self, theme, use_yaml_input): self.personalization() # TOP Widget @@ -2450,7 +2454,7 @@ class MyMain: self.desc_widget.text1.bind("", self.im_up_des_ctrl_lock) self.desc_widget.text.bind("", self.im_up_des_tip_disp) self.item_widget.wlist.bind("<>", self.im_up_item) - self.load_db_quiet() + self.load_db_quiet(use_yaml_input) self.load_lock_ip() self.update_ip_widget() self.top.bind("", self.main_exit_handler) @@ -2481,6 +2485,14 @@ def __generate_option_parser(): help="Select a GUI theme for this session", default=vp_config.yaml_config["gui"]["theme"], ) + parser.add_option( + "-y", + "--yaml", + action="store_true", + dest="use_yaml_input", + help="Read database in Yaml format", + default=False, + ) return parser @@ -2507,4 +2519,4 @@ if os.path.exists(os.path.realpath(options.dataBase)): SAVED_DB_LOCATION = os.path.realpath(options.dataBase) print(SAVED_DB_LOCATION) -top_gui.create_gui(options.theme) +top_gui.create_gui(options.theme, options.use_yaml_input) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index d9d5324a1..baf6c35c3 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -332,7 +332,9 @@ class Subfeature: Convert a Subfeature into legacy-stype Prop object. """ result = Prop(self.name, self.tag, self.display_order) - result.list_of_items = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + result.item_count = self.next_elt_id + result.rfu_list = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + result.item_list = dict(result.rfu_list) return result class Prop: @@ -365,11 +367,8 @@ class Prop: # numbering of Items in Prop and will be inconsistent if items are removed. # Computing the max of item IDs is not reliable either in case the last # item was removed. + 3print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) result.next_elt_id = self.item_count - max_item_id = max([int(elt[1].name) for elt in (self.item_list if self.item_list else self.rfu_list)]) - if max_item_id >= self.item_count: - raise ValueError((self.item_count, max_item_id)) - result.next_elt_id = 1 + max_item_id result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] result.items = OrderedDict(translated_items) @@ -477,24 +476,20 @@ class Feature: a class of instructions or an operation mode of an interface. """ # Class variable: highest Feature ID seen so far. - _highest_id = -1 + _feature_count = 0 - def __init__(self, name="", id=0): + def __init__(self, name="", id=""): # Index of next subfeature to add (MUST ALWAYS GROW upon adding subfeatures!) self.next_elt_id = 0 # Name of the Feature self.name = name # Numerical ID of the Feature: Use the highest known value PLUS ONE # unless explicitly given (e.g., when converting Ip objects). - if id != 0: - if id > self.__class__._highest_id: - self.__class__._highest_id = id - self.id = id - else: - raise ValueError((id, self.__class__._highest_id)) + if id != "": + self.id = int(id) else: - self.__class__._highest_id += 1 - self.id = self.__class__._highest_id + self.id = self.__class__._feature_count + self.__class__._feature_count += 1 # Display order of the Feature self.display_order = self.id # List of subfeatures @@ -538,9 +533,13 @@ class Feature: """ Convert a Feature to a legacy-stype Ip. """ - result = Ip(self.name) + # Map Feature.id to Ip.ip_num. + #print("### Feature.to_Ip(name='%s', id='%d')" % (self.name, self.id)) + result = Ip(self.name, self.id) + result.prop_count = self.next_elt_id result.wid_order = self.display_order - result.prop_list = [[elt[0], elt[1].toSubfeature()] for elt in self.subfeatures.items()] + result.rfu_list = [[elt[0], elt[1].to_Prop()] for elt in self.subfeatures.items()] + result.prop_list = dict(result.rfu_list) for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: setattr(result, attr, getattr(self, attr)) return result @@ -558,10 +557,11 @@ class Ip: self.prop_count = 0 # determine how many prop have been created for a given IP self.name = name self.prop_list = {} - if index: + if index != "": self.ip_num = index ## Store number creation else: self.ip_num = self.__class__._ip_count + #print("### Created Ip(name='%s', index='%d')" % (self.name, self.ip_num)) self.__class__._ip_count += 1 self.wid_order = self.ip_num # rfu for future dev @@ -578,6 +578,7 @@ class Ip: """ Convert an Ip to a Feature. """ + # Map Ip.ip_num to Feature.id. result = Feature(self.name, self.ip_num) # Next_elf_it needs extra care as it is derived from the length of the list # of Properties / Subfeatures. From 16bf162879eb5590480bf9ed06db7c6c54b03e0d Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Thu, 9 Feb 2023 12:40:27 +0100 Subject: [PATCH 032/183] VPTOOL HOTFIX: Fix breaker typo. * tools/vptool/vptool/vp_pack.py (Prop.to_Subfeature): Fix typo commenting out the diagnostic message. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp_pack.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index baf6c35c3..7ee5d6880 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -367,7 +367,7 @@ class Prop: # numbering of Items in Prop and will be inconsistent if items are removed. # Computing the max of item IDs is not reliable either in case the last # item was removed. - 3print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) + #print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) result.next_elt_id = self.item_count result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] From 3e2b547217f320e5997f9a8a6b6927c737df5e51 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 10:23:40 +0100 Subject: [PATCH 033/183] VPTOOL: Switch to Yaml storage. Prepare to switch DVplans to Yaml form. * cva6/docs/VerifPlans/FRONTEND/runme.sh: Pass cmdline options to VPTOOL. * cva6/docs/VerifPlans/ISA_RV32/runme.sh: Ditto. * tools/vptool/vptool/vp.py (MyMain.save_db): Save databases as Yaml. (MyMain.load_db_quiet): By default, load DB from the Yaml files. Use "yml" extension in window title when using Yaml DB files. (__generate_option_parser): Add option to select Pickle input. Set defaults to Yaml for both Yaml and Pickle format option. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/FRONTEND/runme.sh | 2 +- cva6/docs/VerifPlans/ISA_RV32/runme.sh | 2 +- tools/vptool/vptool/vp.py | 38 ++++++++++++++++---------- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/cva6/docs/VerifPlans/FRONTEND/runme.sh b/cva6/docs/VerifPlans/FRONTEND/runme.sh index 3a79359e9..fb0023f98 100644 --- a/cva6/docs/VerifPlans/FRONTEND/runme.sh +++ b/cva6/docs/VerifPlans/FRONTEND/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index 8cc952c8a..b301c7850 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index 755afe774..03047594b 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -1968,20 +1968,21 @@ class MyMain: "yaml_cfg_gitrev" ] # Save individual IPs only if locked by user. - if self.is_locked_by_user(current_ip_name=ip_elt[1].name): - saved_ip_str += "\n " + ip_elt[1].name - with open( - save_dir - + "/VP_IP" - + str(ip_elt[1].ip_num).zfill(3) - + ".pck", - "wb", - ) as output: - pickle.dump(ip_elt, output, 0) + #if self.is_locked_by_user(current_ip_name=ip_elt[1].name): + # saved_ip_str += "\n " + ip_elt[1].name + # with open( + # save_dir + # + "/VP_IP" + # + str(ip_elt[1].ip_num).zfill(3) + # + ".pck", + # "wb", + # ) as output: + # pickle.dump(ip_elt, output, 0) # TODO: Add translation of pickle_ip_list to new-gen # types *HERE*, after emitting Pickle. # Emit the Yaml output from the fixed structures, # skipping pickled ones. + saved_ip_str += "\n " + ip_elt[1].name # Write yaml output with open( save_dir @@ -2057,7 +2058,7 @@ class MyMain: tkinter.messagebox.showwarning("Warning", "No DB Loaded!") return need_to_load - def load_db_quiet(self, use_yaml_input=False): + def load_db_quiet(self, use_yaml_input=True): pickle_ip_list = [] ip_num_next = 0 if self.split_save: @@ -2073,11 +2074,11 @@ class MyMain: else "" ) + ")", - os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].pck"), + os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].%s" % ("yml" if use_yaml_input else "pck")), ) ) if not use_yaml_input: - for filename in glob.glob(dir_to_load + "/VP_IP*pck"): + for filename in glob.glob(dir_to_load + "/VP_IP[0-9][0-9][0-9].pck"): # print("---INFO: Loading "+filename) with open(filename, "rb") as input: pickle_ip_list.append(pickle.load(input)) @@ -2491,8 +2492,17 @@ def __generate_option_parser(): action="store_true", dest="use_yaml_input", help="Read database in Yaml format", - default=False, + default=True, ) + parser.add_option( + "-p", + "--pickle", + action="store_false", + dest="use_yaml_input", + help="Read database in Pickle format", + default=True, + ) + return parser From c34e480faf5ff39e1017f3fe0bdb06cb280e5eb5 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 11:29:24 +0100 Subject: [PATCH 034/183] DV plans: Switch FRONTEND DV plan to Yaml format. * cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml: New. * cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck: Delete. * cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck: Ditto. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck | 1198 -------------------- cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml | 422 +++++++ cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck | 384 ------- cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml | 104 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck | 508 --------- cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml | 152 +++ cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck | 384 ------- cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml | 104 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck | 232 ---- cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml | 66 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck | 308 ----- cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml | 80 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck | 59 - cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml | 10 + cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck | 376 ------ cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml | 114 ++ 16 files changed, 1052 insertions(+), 3449 deletions(-) delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck deleted file mode 100644 index a5d1c4861..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck +++ /dev/null @@ -1,1198 +0,0 @@ -(VPC generation stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_BTB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I6 -sg8 -g17 -sVtag -p23 -VVP_IP003_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F003_S001_I000 -p34 -sVdescription -p35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p38 -sVverif_goals -p39 -VExecute a JALR instruction with a valid address in BTB which is not a misprediction. Check that instruction queue is not flushed. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I4 -sVtest_type -p44 -I0 -sVcov_method -p45 -I1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F003_S001_I001 -p62 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p63 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p64 -sg39 -VExecute a JALR instruction with a valid address in BTB which is a misprediction. -p65 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_FRONTEND_F003_S001_I002 -p76 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB.\u000a\u000aElse JALR is not considered as a control flow instruction, which will generate a mispredict. -p77 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p78 -sg39 -VExecute test with JALR instructions. Functional cov: JALR is executed and BTB output is not valid. -p79 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V002_BHT -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I4 -sg8 -g90 -sg23 -VVP_IP003_P002 -p94 -sg25 -(dp95 -sg12 -I2 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_FRONTEND_F003_S002_I000 -p102 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p103 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p104 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is not a misprediction. Check that instruction queue is not flushed. -p105 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -Vlock_status -p110 -I0 -ssbtp111 -a(V001 -p112 -g1 -(g29 -g3 -Ntp113 -Rp114 -(dp115 -g8 -V001 -p116 -sg23 -VVP_FRONTEND_F003_S002_I001 -p117 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p118 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p119 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is a misprediction. -p120 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp121 -sg15 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -Vlock_status -p125 -I0 -ssbtp126 -a(V002 -p127 -g1 -(g29 -g3 -Ntp128 -Rp129 -(dp130 -g8 -V002 -p131 -sg23 -VVP_FRONTEND_F003_S002_I002 -p132 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p133 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p134 -sg39 -VExecute test with BRANCH instructions. Functional cov: a BRANCH is executed, BTB output is not valid and the branch is taken. -p135 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp136 -sg15 -(lp137 -sg52 -(lp138 -sg13 -(dp139 -g125 -I0 -ssbtp140 -asg85 -(lp141 -sg52 -(lp142 -sg13 -(dp143 -sbtp144 -a(V003_RAS -p145 -g1 -(g18 -g3 -Ntp146 -Rp147 -(dp148 -g22 -I4 -sg8 -g145 -sg23 -VVP_IP003_P003 -p149 -sg25 -(dp150 -sg12 -I3 -sg15 -(lp151 -(V000 -p152 -g1 -(g29 -g3 -Ntp153 -Rp154 -(dp155 -g8 -V000 -p156 -sg23 -VVP_FRONTEND_F003_S003_I000 -p157 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p158 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p159 -sg39 -VExecute a RET instruction with a valid address in RAS. Check that instruction queue is not flushed. -p160 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp161 -sg15 -(lp162 -sg52 -(lp163 -sg13 -(dp164 -g125 -I0 -ssbtp165 -a(V001 -p166 -g1 -(g29 -g3 -Ntp167 -Rp168 -(dp169 -g8 -V001 -p170 -sg23 -VVP_FRONTEND_F003_S003_I001 -p171 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p172 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p173 -sg39 -VExecute a RET instruction with a valid address in RAS which is a misprediction. -p174 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp175 -sg15 -(lp176 -sg52 -(lp177 -sg13 -(dp178 -g125 -I0 -ssbtp179 -a(V002 -p180 -g1 -(g29 -g3 -Ntp181 -Rp182 -(dp183 -g8 -V002 -p184 -sg23 -VVP_FRONTEND_F003_S003_I002 -p185 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p186 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p187 -sg39 -VExecute test with RET instructions. Functional cov: RET is executed and RAS output is not valid. -p188 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp189 -sg15 -(lp190 -sg52 -(lp191 -sg13 -(dp192 -g125 -I0 -ssbtp193 -asg85 -(lp194 -sg52 -(lp195 -sg13 -(dp196 -sbtp197 -a(V004_Return from environment call -p198 -g1 -(g18 -g3 -Ntp199 -Rp200 -(dp201 -g22 -I2 -sg8 -g198 -sg23 -VVP_IP003_P004 -p202 -sg25 -(dp203 -sg12 -I4 -sg15 -(lp204 -(V000 -p205 -g1 -(g29 -g3 -Ntp206 -Rp207 -(dp208 -g8 -V000 -p209 -sg23 -VVP_FRONTEND_F003_S004_I000 -p210 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p211 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p212 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call.\u000a\u000a* Check by assertion that when machine return occurs the mepc address is fetched.\u000a* Functional cov: execute a machine return. -p213 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp214 -sg15 -(lp215 -sg52 -(lp216 -sg13 -(dp217 -g125 -I0 -ssbtp218 -a(V001 -p219 -g1 -(g29 -g3 -Ntp220 -Rp221 -(dp222 -g8 -V001 -p223 -sg23 -VVP_FRONTEND_F003_S004_I001 -p224 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p225 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p226 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call.\u000a\u000a* Check by assertion that when supervisor return occurs the sepc address is fetched.\u000a* Functional cov: execute a supervisor return. -p227 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I24 -sg47 -g42 -sg48 -g42 -sg49 -(lp228 -sg15 -(lp229 -sg52 -(lp230 -sg13 -(dp231 -g125 -I0 -ssbtp232 -asg85 -(lp233 -sg52 -(lp234 -sg13 -(dp235 -sbtp236 -a(V005_Exception/Interrupt -p237 -g1 -(g18 -g3 -Ntp238 -Rp239 -(dp240 -g22 -I2 -sg8 -g237 -sg23 -VVP_IP003_P005 -p241 -sg25 -(dp242 -sg12 -I5 -sg15 -(lp243 -(V000 -p244 -g1 -(g29 -g3 -Ntp245 -Rp246 -(dp247 -g8 -V000 -p248 -sg23 -VVP_FRONTEND_F003_S005_I000 -p249 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p250 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p251 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in machine mode and generates a machine exception by UVM. Check by assertion that when machine exception occurs the machine address is fetched. Functional cov: exception occurs in machine mode. -p252 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp253 -sg15 -(lp254 -sg52 -(lp255 -sg13 -(dp256 -g125 -I0 -ssbtp257 -a(V001 -p258 -g1 -(g29 -g3 -Ntp259 -Rp260 -(dp261 -g8 -V001 -p262 -sg23 -VVP_FRONTEND_F003_S005_I001 -p263 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p264 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p265 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in supervisor mode and generates a supervisor exception by UVM. Check by assertion that when supervisor exception occurs the supervisor address is fetched. functional cov: exception occurs in supervisor mode. -p266 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp267 -sg15 -(lp268 -sg52 -(lp269 -sg13 -(dp270 -g125 -I0 -ssbtp271 -asg85 -(lp272 -sg52 -(lp273 -sg13 -(dp274 -sbtp275 -a(V006_Pipeline flush -p276 -g1 -(g18 -g3 -Ntp277 -Rp278 -(dp279 -g22 -I2 -sg8 -g276 -sg23 -VVP_IP003_P006 -p280 -sg25 -(dp281 -sg12 -I6 -sg15 -(lp282 -(V000 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V000 -p287 -sg23 -VVP_FRONTEND_F003_S006_I000 -p288 -sg35 -VFRONTEND starts fetching from the next instruction again in order to take the up-dated information into account -p289 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Pipeline flush -p290 -sg39 -V[no need to verify this point] -p291 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp292 -sg15 -(lp293 -sg52 -(lp294 -sg13 -(dp295 -g125 -I0 -ssbtp296 -asg85 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -sbtp300 -a(V007_Debug -p301 -g1 -(g18 -g3 -Ntp302 -Rp303 -(dp304 -g22 -I1 -sg8 -g301 -sg23 -VVP_IP003_P007 -p305 -sg25 -(dp306 -sg12 -I7 -sg15 -(lp307 -(V000 -p308 -g1 -(g29 -g3 -Ntp309 -Rp310 -(dp311 -g8 -V000 -p312 -sg23 -VVP_FRONTEND_F003_S007_I000 -p313 -sg35 -VThe debug jump is requested by CSR. The address to be jumped into is HW coded. -p314 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Debug -p315 -sg39 -VUVM generates a debug request to jump into debug handler. Check by assertion that the HW coded debug address is fetched. Functional cov: debug mode occurs -p316 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp317 -sg15 -(lp318 -sg52 -(lp319 -sg13 -(dp320 -g125 -I0 -ssbtp321 -asg85 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -sbtp325 -a(V008_Address mapping change -p326 -g1 -(g18 -g3 -Ntp327 -Rp328 -(dp329 -g22 -I1 -sg8 -g326 -sg23 -VVP_IP003_P008 -p330 -sg25 -(dp331 -sg12 -I8 -sg15 -(lp332 -(V000 -p333 -g1 -(g29 -g3 -Ntp334 -Rp335 -(dp336 -g8 -V000 -p337 -sg23 -VVP_FRONTEND_F003_S008_I000 -p338 -sg35 -VAll program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline and TLBs -p339 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p340 -sg39 -VExecute a address mapping change, then execute a fence.vm instruction, and continue the execution. -p341 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp342 -sg15 -(lp343 -sg52 -(lp344 -sg13 -(dp345 -g125 -I0 -ssbtp346 -asg85 -(lp347 -sg52 -(lp348 -sg13 -(dp349 -sbtp350 -a(V009_Pc gen priority -p351 -g1 -(g18 -g3 -Ntp352 -Rp353 -(dp354 -g22 -I3 -sg8 -g351 -sg23 -VVP_IP003_P009 -p355 -sg25 -(dp356 -sg12 -I9 -sg15 -(lp357 -(V000 -p358 -g1 -(g29 -g3 -Ntp359 -Rp360 -(dp361 -g8 -V000 -p362 -sg23 -VVP_FRONTEND_F003_S009_I000 -p363 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p364 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p365 -sg39 -VUse arc_test executing return from env call and generate Exceptions by UVM during reset, Branch predict, default, mispredict, replay and return from env call. Functional cov: monitor the 6 events -p366 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp367 -sg15 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -g125 -I0 -ssbtp371 -a(V002 -p372 -g1 -(g29 -g3 -Ntp373 -Rp374 -(dp375 -g8 -V002 -p376 -sg23 -VVP_FRONTEND_F003_S009_I002 -p377 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p378 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p379 -sg39 -V[other cases to be elaborated] -p380 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp381 -sg15 -(lp382 -sg52 -(lp383 -sg13 -(dp384 -g125 -I0 -ssbtp385 -asg85 -(lp386 -sg52 -(lp387 -sg13 -(dp388 -sbtp389 -asVrfu_list_0 -p390 -(lp391 -sg85 -(lp392 -sVvptool_gitrev -p393 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p394 -sVio_fmt_gitrev -p395 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p396 -sVconfig_gitrev -p397 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p398 -sVymlcfg_gitrev -p399 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p400 -sbtp401 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml new file mode 100644 index 000000000..83439bc39 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml @@ -0,0 +1,422 @@ +!Feature +next_elt_id: 10 +name: PC generation stage +id: 3 +display_order: 3 +subfeatures: !!omap +- 001_BTB: !Subfeature + name: 001_BTB + tag: VP_IP003_P001 + next_elt_id: 6 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S001_I000 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S001_I001 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S001_I002 + description: "If instruction is a JALR and BTB (Branch Target Buffer) returns\ + \ a valid address, next PC is predicted by BTB.\n\nElse JALR is not considered\ + \ as a control flow instruction, which will generate a mispredict." + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with JALR instructions. Functional cov: JALR is + executed and BTB output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 002_BHT: !Subfeature + name: 002_BHT + tag: VP_IP003_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S002_I000 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S002_I001 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S002_I002 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with BRANCH instructions. Functional cov: a BRANCH + is executed, BTB output is not valid and the branch is taken.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 003_RAS: !Subfeature + name: 003_RAS + tag: VP_IP003_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S003_I000 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS. Check + that instruction queue is not flushed. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S003_I001 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS which is + a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S003_I002 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with RET instructions. Functional cov: RET is executed + and RAS output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 004_Return from environment call: !Subfeature + name: 004_Return from environment call + tag: VP_IP003_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S004_I000 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a arc_test returning from machine env call.\n\n* Check by assertion\ + \ that when machine return occurs the mepc address is fetched.\n* Functional\ + \ cov: execute a machine return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S004_I001 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a returning from supervisor env call.\n\n* Check by assertion that\ + \ when supervisor return occurs the sepc address is fetched.\n* Functional\ + \ cov: execute a supervisor return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 24 + coverage_loc: '' + comments: '' +- 005_Exception/Interrupt: !Subfeature + name: 005_Exception/Interrupt + tag: VP_IP003_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S005_I000 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in machine mode and generates + a machine exception by UVM. Check by assertion that when machine exception + occurs the machine address is fetched. Functional cov: exception occurs + in machine mode.' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S005_I001 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in supervisor mode and generates + a supervisor exception by UVM. Check by assertion that when supervisor exception + occurs the supervisor address is fetched. functional cov: exception occurs + in supervisor mode.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' +- 006_Pipeline flush: !Subfeature + name: 006_Pipeline flush + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S006_I000 + description: FRONTEND starts fetching from the next instruction again in order + to take the up-dated information into account + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Pipeline flush + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[no need to verify this point]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +- 007_Debug: !Subfeature + name: 007_Debug + tag: VP_IP003_P007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S007_I000 + description: The debug jump is requested by CSR. The address to be jumped + into is HW coded. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Debug + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'UVM generates a debug request to jump into debug handler. Check + by assertion that the HW coded debug address is fetched. Functional cov: + debug mode occurs' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 32 + coverage_loc: '' + comments: '' +- 008_Address mapping change: !Subfeature + name: 008_Address mapping change + tag: VP_IP003_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S008_I000 + description: All program counters are logical addressed. If the logical to + physical mapping changes a fence.vm instruction should used to flush the + pipeline and TLBs + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a address mapping change, then execute a fence.vm instruction, + and continue the execution. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 009_Pc gen priority: !Subfeature + name: 009_Pc gen priority + tag: VP_IP003_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S009_I000 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Use arc_test executing return from env call and generate Exceptions + by UVM during reset, Branch predict, default, mispredict, replay and return + from env call. Functional cov: monitor the 6 events' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S009_I002 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[other cases to be elaborated]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck deleted file mode 100644 index 7af6e80e4..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VBTB -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F004_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BTB -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP004_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F004_S001_I000 -p74 -sg35 -VThe information is stored in a 8 entry table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p76 -sg39 -VConfirm that the best configuration for BTB entry number is 8 by monitoring the Coremark performance and silicon footprint, the configuration without BTB is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP004_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F004_S002_I000 -p99 -sg35 -VWhen a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p101 -sg39 -VWhen a mis predict occurs caused by JALR, check that info is stored in BTB -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP004_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F004_S003_I000 -p124 -sg35 -VThe BTB is not updated if processor is in debug mode. -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml new file mode 100644 index 000000000..9b39ea709 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: BTB +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP004_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S001_I000 + description: The information is stored in a 8 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BTB entry number is 8 + by monitoring the Coremark performance and silicon footprint, the configuration + without BTB is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP004_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S002_I000 + description: When a unconditional jumps to a register (JALR instruction) is + mispredicted by the EXECUTE, the relative information is stored into the + BTB, that is to say the JALR PC and the target address. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by JALR, check that info is + stored in BTB + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_debug is not intrusive: !Subfeature + name: 003_debug is not intrusive + tag: VP_IP004_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S003_I000 + description: The BTB is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck deleted file mode 100644 index 56b70c2b1..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck +++ /dev/null @@ -1,508 +0,0 @@ -(VBHT -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F005_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BHT -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V002_table update -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP005_P002 -p66 -sg25 -(dp67 -sg12 -I2 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F005_S002_I000 -p74 -sg35 -VWhen a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p76 -sg39 -VWhen a mis predict occurs caused by BRANCH, check that info is stored in BHT -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V003_saturation -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I2 -sg8 -g87 -sg23 -VVP_IP005_P003 -p91 -sg25 -(dp92 -sg12 -I3 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F005_S003_I000 -p99 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p101 -sg39 -VExecute a serie of taken and not taken branch to check the saturation mechanism -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I-1 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -a(V001 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V001 -p112 -sg23 -VVP_FRONTEND_F005_S003_I001 -p113 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p114 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p115 -sg39 -VVerify the saturation mechnism is optimal. Modify the saturation mechanism by removing/adding one stage, and check the Coremark performance evolution -p116 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -asg57 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -sbtp125 -a(V004_Table depth -p126 -g1 -(g18 -g3 -Ntp127 -Rp128 -(dp129 -g22 -I1 -sg8 -g126 -sg23 -VVP_IP005_P004 -p130 -sg25 -(dp131 -sg12 -I4 -sg15 -(lp132 -(V000 -p133 -g1 -(g29 -g3 -Ntp134 -Rp135 -(dp136 -g8 -V000 -p137 -sg23 -VVP_FRONTEND_F005_S004_I000 -p138 -sg35 -VThe information is stored in a 1024 entry table. -p139 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p140 -sg39 -VConfirm that the best configuration for BHT entry number is 1024 by monitoring the Coremark performance and silicon footprint, the configuration without BHT is to be challenged too. -p141 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp142 -sg15 -(lp143 -sg52 -(lp144 -sg13 -(dp145 -g55 -I0 -ssbtp146 -asg57 -(lp147 -sg52 -(lp148 -sg13 -(dp149 -sbtp150 -a(V005_Debug is not intrusive -p151 -g1 -(g18 -g3 -Ntp152 -Rp153 -(dp154 -g22 -I1 -sg8 -g151 -sg23 -VVP_IP005_P005 -p155 -sg25 -(dp156 -sg12 -I5 -sg15 -(lp157 -(V000 -p158 -g1 -(g29 -g3 -Ntp159 -Rp160 -(dp161 -g8 -V000 -p162 -sg23 -VVP_FRONTEND_F005_S005_I000 -p163 -sg35 -VThe BHT is not updated if processor is in debug mode. -p164 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p165 -sg39 -VExecute a debug session, check that the table content is not modified -p166 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp167 -sg15 -(lp168 -sg52 -(lp169 -sg13 -(dp170 -g55 -I0 -ssbtp171 -asg57 -(lp172 -sg52 -(lp173 -sg13 -(dp174 -sbtp175 -asVrfu_list_0 -p176 -(lp177 -sg57 -(lp178 -sVvptool_gitrev -p179 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p180 -sVio_fmt_gitrev -p181 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p182 -sVconfig_gitrev -p183 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p184 -sVymlcfg_gitrev -p185 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p186 -sbtp187 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml new file mode 100644 index 000000000..df4babd4d --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml @@ -0,0 +1,152 @@ +!Feature +next_elt_id: 6 +name: BHT +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP005_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 002_table update: !Subfeature + name: 002_table update + tag: VP_IP005_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S002_I000 + description: When a branch instruction is resolved by the EXECUTE, the relative + information is stored in the Branch History Table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by BRANCH, check that info is + stored in BHT + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_saturation: !Subfeature + name: 003_saturation + tag: VP_IP005_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S003_I000 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a serie of taken and not taken branch to check the saturation + mechanism + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F005_S003_I001 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Verify the saturation mechnism is optimal. Modify the saturation + mechanism by removing/adding one stage, and check the Coremark performance + evolution + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 004_Table depth: !Subfeature + name: 004_Table depth + tag: VP_IP005_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S004_I000 + description: The information is stored in a 1024 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BHT entry number is 1024 + by monitoring the Coremark performance and silicon footprint, the configuration + without BHT is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 005_Debug is not intrusive: !Subfeature + name: 005_Debug is not intrusive + tag: VP_IP005_P005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S005_I000 + description: The BHT is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck deleted file mode 100644 index 2fdde8008..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VRAS -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F006_S000_I000 -p34 -sVdescription -p35 -VThe RAS is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/RAS -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP006_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F006_S001_I000 -p74 -sg35 -VThe RAS FIFO depth is 2. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p76 -sg39 -VConfirm that the best configuration for RAS entry number is 2 by monitoring the Coremark performance and silicon footprint, the configuration without RAS is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP006_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F006_S002_I000 -p99 -sg35 -VWhen an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p101 -sg39 -VWhen a JAL instruction is executed, check that info is stored in RAS -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_Debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP006_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F006_S003_I000 -p124 -sg35 -VNo dedicated specification -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml new file mode 100644 index 000000000..76b06d498 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: RAS +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S000_I000 + description: The RAS is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP006_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S001_I000 + description: The RAS FIFO depth is 2. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for RAS entry number is 2 + by monitoring the Coremark performance and silicon footprint, the configuration + without RAS is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP006_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S002_I000 + description: When an unconditional jumps to a known target address (JAL instruction) + is consummed by the instr_queue, the next pc after the JAL instruction and + the return address are stored into a FIFO. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a JAL instruction is executed, check that info is stored + in RAS + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_Debug is not intrusive: !Subfeature + name: 003_Debug is not intrusive + tag: VP_IP006_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S003_I000 + description: No dedicated specification + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck deleted file mode 100644 index 92ea00422..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck +++ /dev/null @@ -1,232 +0,0 @@ -(VInstr_realign -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C extension -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F007_S000_I000 -p34 -sVdescription -p35 -VThe 32-bit aligned block coming from the CACHE sub-system enters the instr_realign module. This module extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign module provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign module before being provided in the next cycles. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p38 -sVverif_goals -p39 -VExecute program compiled with C extension. Cover the case when 2 instructions are fetched in the same cache block and when an instruction is interleaved with two cache block\u000a\u000a[NO NEED TO VERIFY THIS CASE] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Flush -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP007_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F007_S001_I000 -p74 -sg35 -VIn case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p76 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -asVrfu_list_0 -p87 -(lp88 -sg57 -(lp89 -sVvptool_gitrev -p90 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p91 -sVio_fmt_gitrev -p92 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p93 -sVconfig_gitrev -p94 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p95 -sVymlcfg_gitrev -p96 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p97 -sbtp98 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml new file mode 100644 index 000000000..365f818e3 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml @@ -0,0 +1,66 @@ +!Feature +next_elt_id: 2 +name: Instr_realign +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_C extension: !Subfeature + name: 000_C extension + tag: VP_IP007_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S000_I000 + description: The 32-bit aligned block coming from the CACHE sub-system enters + the instr_realign module. This module extracts the instructions from the + 32-bit blocks, up to two instructions because it is possible to fetch two + instructions when C extension is used. If the instructions are not compressed, + it is possible that the instruction is not aligned on the block size but + rather interleaved with two cache blocks. In that case, two cache accesses + are needed. The instr_realign module provides at maximum one instruction + per cycle. Not complete instruction is stored in instr_realign module before + being provided in the next cycles. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Execute program compiled with C extension. Cover the case when\ + \ 2 instructions are fetched in the same cache block and when an instruction\ + \ is interleaved with two cache block\n\n[NO NEED TO VERIFY THIS CASE]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_Flush: !Subfeature + name: 001_Flush + tag: VP_IP007_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S001_I000 + description: In case of mispredict, flush, replay or branch predict, the instr_realign + is re-initialized, the internal register storing the instruction alignment + state is reset. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck deleted file mode 100644 index dc4ea8eef..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck +++ /dev/null @@ -1,308 +0,0 @@ -(VInstr_queue -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FIFO depth -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F008_S000_I000 -p34 -sVdescription -p35 -VThe instruction queue contains max 4 instructions. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p38 -sVverif_goals -p39 -VConfirm that the best configuration for instruction queue entry number is 4 by monitoring the Coremark performance and silicon footprint -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I11 -sVtest_type -p44 -I10 -sVcov_method -p45 -I10 -sVcores -p46 -I8 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Page fault exception -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP008_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F008_S001_I000 -p74 -sg35 -VIn instruction queue, exception can only correspond to page-fault exception. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p76 -sg39 -VExecute following exception and check that only page-fault can be stored in instruction queue: bus errors, invalid accesses or instruction page faults. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Flush -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP008_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F008_S002_I000 -p99 -sg35 -VThe instruction queue can be flushed by CONTROLLER. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p101 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -asVrfu_list_0 -p112 -(lp113 -sg57 -(lp114 -sVvptool_gitrev -p115 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p116 -sVio_fmt_gitrev -p117 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p118 -sVconfig_gitrev -p119 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p120 -sVymlcfg_gitrev -p121 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p122 -sbtp123 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml new file mode 100644 index 000000000..0559c2d9d --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml @@ -0,0 +1,80 @@ +!Feature +next_elt_id: 3 +name: Instr_queue +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_FIFO depth: !Subfeature + name: 000_FIFO depth + tag: VP_IP008_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S000_I000 + description: The instruction queue contains max 4 instructions. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for instruction queue entry + number is 4 by monitoring the Coremark performance and silicon footprint + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +- 001_Page fault exception: !Subfeature + name: 001_Page fault exception + tag: VP_IP008_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S001_I000 + description: In instruction queue, exception can only correspond to page-fault + exception. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute following exception and check that only page-fault can + be stored in instruction queue: bus errors, invalid accesses or instruction + page faults.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Flush: !Subfeature + name: 002_Flush + tag: VP_IP008_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S002_I000 + description: The instruction queue can be flushed by CONTROLLER. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck deleted file mode 100644 index ac1287a8b..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck +++ /dev/null @@ -1,59 +0,0 @@ -(VInstr_scan -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I0 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -sVrfu_list_0 -p17 -(lp18 -sVrfu_list_1 -p19 -(lp20 -sVvptool_gitrev -p21 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p22 -sVio_fmt_gitrev -p23 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p24 -sVconfig_gitrev -p25 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p26 -sVymlcfg_gitrev -p27 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p28 -sbtp29 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml new file mode 100644 index 000000000..6ec7a33b7 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml @@ -0,0 +1,10 @@ +!Feature +next_elt_id: 0 +name: Instr_scan +id: 9 +display_order: 9 +subfeatures: !!omap [] +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck deleted file mode 100644 index db23b5ab5..000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck +++ /dev/null @@ -1,376 +0,0 @@ -(VFetch stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_MMU translation -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP010_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F010_S001_I000 -p34 -sVdescription -p35 -VThe Fetch stage asks the MMU to translate the requested address. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/Fetch stage -p38 -sVverif_goals -p39 -VExecute a program with virtual PC -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F010_S001_I001 -p62 -sg35 -VThe Fetch stage asks the MMU to translate the requested address. -p63 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p64 -sg39 -VCheck the translation does not impact execution time by executing Coremark in pphysical and virtual modes. -p65 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V002_Exceptions -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I4 -sg8 -g76 -sg23 -VVP_IP010_P002 -p80 -sg25 -(dp81 -sg12 -I2 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_FRONTEND_F010_S002_I000 -p88 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p89 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p90 -sg39 -VGenerate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs. -p91 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V002 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V002 -p101 -sg23 -VVP_FRONTEND_F010_S002_I002 -p102 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p103 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p104 -sg39 -VGenerate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs. -p105 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V003 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V003 -p115 -sg23 -VVP_FRONTEND_F010_S002_I003 -p116 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p117 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p118 -sg39 -VGenerate an instruction page faults and check that the exception is triggered -p119 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg71 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -asVrfu_list_0 -p129 -(lp130 -sg71 -(lp131 -sVvptool_gitrev -p132 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p133 -sVio_fmt_gitrev -p134 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p135 -sVconfig_gitrev -p136 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p137 -sVymlcfg_gitrev -p138 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p139 -sbtp140 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml new file mode 100644 index 000000000..fe95149ac --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml @@ -0,0 +1,114 @@ +!Feature +next_elt_id: 3 +name: Fetch stage +id: 10 +display_order: 10 +subfeatures: !!omap +- 001_MMU translation: !Subfeature + name: 001_MMU translation + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S001_I000 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a program with virtual PC + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F010_S001_I001 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Check the translation does not impact execution time by executing + Coremark in pphysical and virtual modes. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Exceptions: !Subfeature + name: 002_Exceptions + tag: VP_IP010_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S002_I000 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate a bus error exception by UVM or by test (to be decided) + and check that the exception address is fetched. Functional cov: a bus error + exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F010_S002_I002 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate an invalid access exception by UVM or by test (to be + decided) and check that the exception address is fetched. Functional cov: + an invalid access exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FRONTEND_F010_S002_I003 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Generate an instruction page faults and check that the exception + is triggered + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' From e03c76bacd37d858b08a04426952e50c7f383c5e Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 11:34:12 +0100 Subject: [PATCH 035/183] DV plans: Switch ISA_RV32 DV plan to Yaml format. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml: New. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck: Delete. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck: Ditto. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck | 1999 --------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml | 697 ++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck | 1828 -------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml | 665 +++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck | 1478 ----------- cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml | 498 ++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck | 1333 ---------- cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml | 454 ++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck | 157 -- cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml | 33 + cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck | 284 --- cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml | 70 + cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck | 780 ------ cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml | 275 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck | 976 -------- cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml | 350 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck | 520 ---- cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml | 179 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck | 2059 ---------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml | 788 ++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck | 2592 -------------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml | 868 +++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck | 920 ------- cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml | 286 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck | 672 ----- cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml | 218 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck | 824 ------- cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml | 263 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck | 157 -- cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml | 32 + 30 files changed, 5676 insertions(+), 16579 deletions(-) delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck deleted file mode 100644 index 01fe8aacb..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck +++ /dev/null @@ -1,1999 +0,0 @@ -(VRV32I Register-Immediate Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I11 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I0 -sVwid_order -p12 -I0 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADDI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP011_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F011_S000_I000 -p34 -sVdescription -p35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_addi_cg.cp_rs1\u000aisacov.rv32i_addi_cg.cp_rd\u000aisacov.rv32i_addi_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F011_S000_I001 -p63 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p64 -sg37 -VISA\u000aChapter 2.4 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_addi_cg.cp_rs1_value\u000aisacov.rv32i_addi_cg.cp_immi_value\u000aisacov.rv32i_addi_cg.cross_rs1_immi_value\u000aisacov.rv32i_addi_cg.cp_rs1_toggle\u000aisacov.rv32i_addi_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F011_S000_I002 -p78 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p79 -sg37 -VISA\u000aChapter 2.4 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_addi_cg.cp_rd_value\u000aisacov.rv32i_addi_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_XORI -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I5 -sg8 -g93 -sg23 -VVP_IP011_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F011_S001_I000 -p105 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p106 -sg37 -VISA\u000aChapter 2.4 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_xori_cg.cp_rs1\u000aisacov.rv32i_xori_cg.cp_rd\u000aisacov.rv32i_xori_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -g115 -sg23 -VVP_ISA_F011_S001_I001 -p119 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p120 -sg37 -VISA\u000aChapter 2.4 -p121 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p122 -sg41 -Visacov.rv32i_xori_cg.cp_rs1_value\u000aisacov.rv32i_xori_cg.cp_immi_value\u000aisacov.rv32i_xori_cg.cross_rs1_immi_value\u000aisacov.rv32i_xori_cg.cp_rs1_toggle\u000aisacov.rv32i_xori_cg.cp_immi_toggle -p123 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp124 -sg15 -(lp125 -sg53 -(lp126 -sg13 -(dp127 -g56 -I0 -ssbtp128 -a(V002 -p129 -g1 -(g29 -g3 -Ntp130 -Rp131 -(dp132 -g8 -g129 -sg23 -VVP_ISA_F011_S001_I002 -p133 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_xori_cg.cp_rd_value\u000aisacov.rv32i_xori_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg88 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_ORI -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I4 -sg8 -g147 -sg23 -VVP_IP011_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F011_S002_I000 -p159 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p162 -sg41 -Visacov.rv32i_ori_cg.cp_rs1\u000aisacov.rv32i_ori_cg.cp_rd\u000aisacov.rv32i_ori_cg.cp_rd_rs1_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -g169 -sg23 -VVP_ISA_F011_S002_I001 -p173 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p174 -sg37 -VISA\u000aChapter 2.4 -p175 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p176 -sg41 -Visacov.rv32i_ori_cg.cp_rs1_value\u000aisacov.rv32i_ori_cg.cp_immi_value\u000aisacov.rv32i_ori_cg.cross_rs1_immi_value\u000aisacov.rv32i_ori_cg.cp_rs1_toggle\u000aisacov.rv32i_ori_cg.cp_immi_toggle -p177 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp178 -sg15 -(lp179 -sg53 -(lp180 -sg13 -(dp181 -g56 -I0 -ssbtp182 -a(V002 -p183 -g1 -(g29 -g3 -Ntp184 -Rp185 -(dp186 -g8 -g183 -sg23 -VVP_ISA_F011_S002_I002 -p187 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p188 -sg37 -VISA\u000aChapter 2.4 -p189 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p190 -sg41 -Visacov.rv32i_ori_cg.cp_rd_value\u000aisacov.rv32i_ori_cg.cp_rd_toggle -p191 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp192 -sg15 -(lp193 -sg53 -(lp194 -sg13 -(dp195 -g56 -I0 -ssbtp196 -asg88 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -sbtp200 -a(V003_ANDI -p201 -g1 -(g18 -g3 -Ntp202 -Rp203 -(dp204 -g22 -I3 -sg8 -g201 -sg23 -VVP_IP011_P003 -p205 -sg25 -(dp206 -sg12 -I3 -sg15 -(lp207 -(V000 -p208 -g1 -(g29 -g3 -Ntp209 -Rp210 -(dp211 -g8 -V000 -p212 -sg23 -VVP_ISA_F011_S003_I000 -p213 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p214 -sg37 -VISA\u000aChapter 2.4 -p215 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p216 -sg41 -Visacov.rv32i_andi_cg.cp_rs1\u000aisacov.rv32i_andi_cg.cp_rd\u000aisacov.rv32i_andi_cg.cp_rd_rs1_hazard -p217 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp218 -sg15 -(lp219 -sg53 -(lp220 -sg13 -(dp221 -g56 -I0 -ssbtp222 -a(V001 -p223 -g1 -(g29 -g3 -Ntp224 -Rp225 -(dp226 -g8 -V001 -p227 -sg23 -VVP_ISA_F011_S003_I001 -p228 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p229 -sg37 -VISA\u000aChapter 2.4 -p230 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p231 -sg41 -Visacov.rv32i_andi_cg.cp_rs1_value\u000aisacov.rv32i_andi_cg.cp_immi_value\u000aisacov.rv32i_andi_cg.cross_rs1_immi_value\u000aisacov.rv32i_andi_cg.cp_rs1_toggle\u000aisacov.rv32i_andi_cg.cp_immi_toggle -p232 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp233 -sg15 -(lp234 -sg53 -(lp235 -sg13 -(dp236 -g56 -I0 -ssbtp237 -a(V002 -p238 -g1 -(g29 -g3 -Ntp239 -Rp240 -(dp241 -g8 -V002 -p242 -sg23 -VVP_ISA_F011_S003_I002 -p243 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p244 -sg37 -VISA\u000aChapter 2.4 -p245 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p246 -sg41 -Visacov.rv32i_andi_cg.cp_rd_value\u000aisacov.rv32i_andi_cg.cp_rd_toggle -p247 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp248 -sg15 -(lp249 -sg53 -(lp250 -sg13 -(dp251 -g56 -I0 -ssbtp252 -asg88 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -sbtp256 -a(V004_SLTI -p257 -g1 -(g18 -g3 -Ntp258 -Rp259 -(dp260 -g22 -I3 -sg8 -g257 -sg23 -VVP_IP011_P004 -p261 -sg25 -(dp262 -sg12 -I4 -sg15 -(lp263 -(V000 -p264 -g1 -(g29 -g3 -Ntp265 -Rp266 -(dp267 -g8 -V000 -p268 -sg23 -VVP_ISA_F011_S004_I000 -p269 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p270 -sg37 -VISA\u000aChapter 2.4 -p271 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p272 -sg41 -Visacov.rv32i_slti_cg.cp_rs1\u000aisacov.rv32i_slti_cg.cp_rd\u000aisacov.rv32i_slti_cg.cp_rd_rs1_hazard -p273 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp274 -sg15 -(lp275 -sg53 -(lp276 -sg13 -(dp277 -g56 -I0 -ssbtp278 -a(V001 -p279 -g1 -(g29 -g3 -Ntp280 -Rp281 -(dp282 -g8 -V001 -p283 -sg23 -VVP_ISA_F011_S004_I001 -p284 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p285 -sg37 -VISA\u000aChapter 2.4 -p286 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p287 -sg41 -Visacov.rv32i_slti_cg.cp_rs1_value\u000aisacov.rv32i_slti_cg.cp_immi_value\u000aisacov.rv32i_slti_cg.cross_rs1_immi_value\u000aisacov.rv32i_slti_cg.cp_rs1_toggle\u000aisacov.rv32i_slti_cg.cp_immi_toggle -p288 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp289 -sg15 -(lp290 -sg53 -(lp291 -sg13 -(dp292 -g56 -I0 -ssbtp293 -a(V002 -p294 -g1 -(g29 -g3 -Ntp295 -Rp296 -(dp297 -g8 -V002 -p298 -sg23 -VVP_ISA_F011_S004_I002 -p299 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p300 -sg37 -VISA\u000aChapter 2.4 -p301 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p302 -sg41 -Visacov.rv32i_slti_cg.cp_rd_value -p303 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp304 -sg15 -(lp305 -sg53 -(lp306 -sg13 -(dp307 -g56 -I0 -ssbtp308 -asg88 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -sbtp312 -a(V005_SLTIU -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP011_P005 -p317 -sg25 -(dp318 -sg12 -I5 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F011_S005_I000 -p325 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p326 -sg37 -VISA\u000aChapter 2.4 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p328 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1\u000aisacov.rv32i_sltiu_cg.cp_rd\u000aisacov.rv32i_sltiu_cg.cp_rd_rs1_hazard -p329 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp330 -sg15 -(lp331 -sg53 -(lp332 -sg13 -(dp333 -g56 -I0 -ssbtp334 -a(V001 -p335 -g1 -(g29 -g3 -Ntp336 -Rp337 -(dp338 -g8 -V001 -p339 -sg23 -VVP_ISA_F011_S005_I001 -p340 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p341 -sg37 -VISA\u000aChapter 2.4 -p342 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p343 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1_value\u000aisacov.rv32i_sltiu_cg.cp_immi_value\u000aisacov.rv32i_sltiu_cg.cross_rs1_immi_value\u000aisacov.rv32i_sltiu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltiu_cg.cp_immi_toggle -p344 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp345 -sg15 -(lp346 -sg53 -(lp347 -sg13 -(dp348 -g56 -I0 -ssbtp349 -a(V002 -p350 -g1 -(g29 -g3 -Ntp351 -Rp352 -(dp353 -g8 -V002 -p354 -sg23 -VVP_ISA_F011_S005_I002 -p355 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p356 -sg37 -VISA\u000aChapter 2.4 -p357 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p358 -sg41 -Visacov.rv32i_sltiu_cg.cp_rd_value -p359 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp360 -sg15 -(lp361 -sg53 -(lp362 -sg13 -(dp363 -g56 -I0 -ssbtp364 -asg88 -(lp365 -sg53 -(lp366 -sg13 -(dp367 -sbtp368 -a(V006_SLLI -p369 -g1 -(g18 -g3 -Ntp370 -Rp371 -(dp372 -g22 -I3 -sg8 -g369 -sg23 -VVP_IP011_P006 -p373 -sg25 -(dp374 -sg12 -I6 -sg15 -(lp375 -(V000 -p376 -g1 -(g29 -g3 -Ntp377 -Rp378 -(dp379 -g8 -V000 -p380 -sg23 -VVP_ISA_F011_S006_I000 -p381 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p382 -sg37 -VISA\u000aChapter 2.4 -p383 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p384 -sg41 -Visacov.rv32i_slli_cg.cp_rs1\u000aisacov.rv32i_slli_cg.cp_rd\u000aisacov.rv32i_slli_cg.cp_rd_rs1_hazard -p385 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp386 -sg15 -(lp387 -sg53 -(lp388 -sg13 -(dp389 -g56 -I0 -ssbtp390 -a(V001 -p391 -g1 -(g29 -g3 -Ntp392 -Rp393 -(dp394 -g8 -V001 -p395 -sg23 -VVP_ISA_F011_S006_I001 -p396 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p397 -sg37 -VISA\u000aChapter 2.4 -p398 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p399 -sg41 -Visacov.rv32i_slli_cg.cp_rs1_value\u000aisacov.rv32i_slli_cg.cp_immi_value\u000aisacov.rv32i_slli_cg.cross_rs1_immi_value\u000aisacov.rv32i_slli_cg.cp_rs1_toggle -p400 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp401 -sg15 -(lp402 -sg53 -(lp403 -sg13 -(dp404 -g56 -I0 -ssbtp405 -a(V002 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V002 -p410 -sg23 -VVP_ISA_F011_S006_I002 -p411 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p412 -sg37 -VISA\u000aChapter 2.4 -p413 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p414 -sg41 -Visacov.rv32i_slli_cg.cp_rd_value\u000aisacov.rv32i_slli_cg.cp_rd_toggle -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -asg88 -(lp421 -sg53 -(lp422 -sg13 -(dp423 -sbtp424 -a(V007_SRLI -p425 -g1 -(g18 -g3 -Ntp426 -Rp427 -(dp428 -g22 -I4 -sg8 -g425 -sg23 -VVP_IP011_P007 -p429 -sg25 -(dp430 -sg12 -I7 -sg15 -(lp431 -(V000 -p432 -g1 -(g29 -g3 -Ntp433 -Rp434 -(dp435 -g8 -V000 -p436 -sg23 -VVP_ISA_F011_S007_I000 -p437 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p438 -sg37 -VISA\u000aChapter 2.4 -p439 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p440 -sg41 -Visacov.rv32i_srli_cg.cp_rs1\u000aisacov.rv32i_srli_cg.cp_rd\u000aisacov.rv32i_srli_cg.cp_rd_rs1_hazard -p441 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp442 -sg15 -(lp443 -sg53 -(lp444 -sg13 -(dp445 -g56 -I0 -ssbtp446 -a(V001 -p447 -g1 -(g29 -g3 -Ntp448 -Rp449 -(dp450 -g8 -g447 -sg23 -VVP_ISA_F011_S007_I001 -p451 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p452 -sg37 -VISA\u000aChapter 2.4 -p453 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p454 -sg41 -Visacov.rv32i_srli_cg.cp_rs1_value\u000aisacov.rv32i_srli_cg.cp_immi_value\u000aisacov.rv32i_srli_cg.cross_rs1_immi_value\u000aisacov.rv32i_srli_cg.cp_rs1_toggle -p455 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp456 -sg15 -(lp457 -sg53 -(lp458 -sg13 -(dp459 -g56 -I0 -ssbtp460 -a(V002 -p461 -g1 -(g29 -g3 -Ntp462 -Rp463 -(dp464 -g8 -g461 -sg23 -VVP_ISA_F011_S007_I002 -p465 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p466 -sg37 -VISA\u000aChapter 2.4 -p467 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p468 -sg41 -Visacov.rv32i_srli_cg.cp_rd_value\u000aisacov.rv32i_srli_cg.cp_rd_toggle -p469 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp470 -sg15 -(lp471 -sg53 -(lp472 -sg13 -(dp473 -g56 -I0 -ssbtp474 -asg88 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -sbtp478 -a(V008_SRAI -p479 -g1 -(g18 -g3 -Ntp480 -Rp481 -(dp482 -g22 -I3 -sg8 -g479 -sg23 -VVP_IP011_P008 -p483 -sg25 -(dp484 -sg12 -I8 -sg15 -(lp485 -(V000 -p486 -g1 -(g29 -g3 -Ntp487 -Rp488 -(dp489 -g8 -V000 -p490 -sg23 -VVP_ISA_F011_S008_I000 -p491 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p492 -sg37 -VISA\u000aChapter 2.4 -p493 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p494 -sg41 -Visacov.rv32i_srai_cg.cp_rs1\u000aisacov.rv32i_srai_cg.cp_rd\u000aisacov.rv32i_srai_cg.cp_rd_rs1_hazard -p495 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp496 -sg15 -(lp497 -sg53 -(lp498 -sg13 -(dp499 -g56 -I0 -ssbtp500 -a(V001 -p501 -g1 -(g29 -g3 -Ntp502 -Rp503 -(dp504 -g8 -V001 -p505 -sg23 -VVP_ISA_F011_S008_I001 -p506 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p507 -sg37 -VISA\u000aChapter 2.4 -p508 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p509 -sg41 -Visacov.rv32i_srai_cg.cp_rs1_value\u000aisacov.rv32i_srai_cg.cp_immi_value\u000aisacov.rv32i_srai_cg.cross_rs1_immi_value\u000aisacov.rv32i_srai_cg.cp_rs1_toggle -p510 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp511 -sg15 -(lp512 -sg53 -(lp513 -sg13 -(dp514 -g56 -I0 -ssbtp515 -a(V002 -p516 -g1 -(g29 -g3 -Ntp517 -Rp518 -(dp519 -g8 -V002 -p520 -sg23 -VVP_ISA_F011_S008_I002 -p521 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p522 -sg37 -VISA\u000aChapter 2.4 -p523 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p524 -sg41 -Visacov.rv32i_srai_cg.cp_rd_value\u000aisacov.rv32i_srai_cg.cp_rd_toggle -p525 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp526 -sg15 -(lp527 -sg53 -(lp528 -sg13 -(dp529 -g56 -I0 -ssbtp530 -asg88 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -sbtp534 -a(V009_LUI -p535 -g1 -(g18 -g3 -Ntp536 -Rp537 -(dp538 -g22 -I3 -sg8 -g535 -sg23 -VVP_IP011_P009 -p539 -sg25 -(dp540 -sg12 -I9 -sg15 -(lp541 -(V000 -p542 -g1 -(g29 -g3 -Ntp543 -Rp544 -(dp545 -g8 -V000 -p546 -sg23 -VVP_ISA_F011_S009_I000 -p547 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p548 -sg37 -VISA\u000aChapter 2.4 -p549 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p550 -sg41 -Visacov.rv32i_lui_cg.cp_rd -p551 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp552 -sg15 -(lp553 -sg53 -(lp554 -sg13 -(dp555 -g56 -I0 -ssbtp556 -a(V001 -p557 -g1 -(g29 -g3 -Ntp558 -Rp559 -(dp560 -g8 -V001 -p561 -sg23 -VVP_ISA_F011_S009_I001 -p562 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p563 -sg37 -VISA\u000aChapter 2.4 -p564 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p565 -sg41 -Visacov.rv32i_lui_cg.cp_immu_value\u000aisacov.rv32i_lui_cg.cp_immu_toggle -p566 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp567 -sg15 -(lp568 -sg53 -(lp569 -sg13 -(dp570 -g56 -I0 -ssbtp571 -a(V002 -p572 -g1 -(g29 -g3 -Ntp573 -Rp574 -(dp575 -g8 -V002 -p576 -sg23 -VVP_ISA_F011_S009_I002 -p577 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p578 -sg37 -VISA\u000aChapter 2.4 -p579 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p580 -sg41 -Visacov.rv32i_lui_cg.cp_rd_value\u000aisacov.rv32i_lui_cg.cp_rd_toggle -p581 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp582 -sg15 -(lp583 -sg53 -(lp584 -sg13 -(dp585 -g56 -I0 -ssbtp586 -asg88 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -sbtp590 -a(V010_AUIPC -p591 -g1 -(g18 -g3 -Ntp592 -Rp593 -(dp594 -g22 -I3 -sg8 -g591 -sg23 -VVP_IP011_P010 -p595 -sg25 -(dp596 -sg12 -I10 -sg15 -(lp597 -(V000 -p598 -g1 -(g29 -g3 -Ntp599 -Rp600 -(dp601 -g8 -V000 -p602 -sg23 -VVP_ISA_F011_S010_I000 -p603 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p604 -sg37 -VISA\u000aChapter 2.4 -p605 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p606 -sg41 -Visacov.rv32i_auipc_cg.cp_rd -p607 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp608 -sg15 -(lp609 -sg53 -(lp610 -sg13 -(dp611 -g56 -I0 -ssbtp612 -a(V001 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V001 -p617 -sg23 -VVP_ISA_F011_S010_I001 -p618 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p619 -sg37 -VISA\u000aChapter 2.4 -p620 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p621 -sg41 -Visacov.rv32i_auipc_cg.cp_immu_value\u000aisacov.rv32i_auipc_cg.cp_immu_toggle -p622 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp623 -sg15 -(lp624 -sg53 -(lp625 -sg13 -(dp626 -g56 -I0 -ssbtp627 -a(V002 -p628 -g1 -(g29 -g3 -Ntp629 -Rp630 -(dp631 -g8 -V002 -p632 -sg23 -VVP_ISA_F011_S010_I002 -p633 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p634 -sg37 -VISA\u000aChapter 2.4 -p635 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p636 -sg41 -Visacov.rv32i_auipc_cg.cp_rd_value\u000aisacov.rv32i_auipc_cg.cp_rd_toggle -p637 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp638 -sg15 -(lp639 -sg53 -(lp640 -sg13 -(dp641 -g56 -I0 -ssbtp642 -asg88 -(lp643 -sg53 -(lp644 -sg13 -(dp645 -sbtp646 -asVrfu_list_0 -p647 -(lp648 -sg88 -(lp649 -sVvptool_gitrev -p650 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p651 -sVio_fmt_gitrev -p652 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p653 -sVconfig_gitrev -p654 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p655 -sVymlcfg_gitrev -p656 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p657 -sbtp658 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml new file mode 100644 index 000000000..70b22805d --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -0,0 +1,697 @@ +!Feature +next_elt_id: 11 +name: RV32I Register-Immediate Instructions +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_ADDI: !Subfeature + name: 000_ADDI + tag: VP_IP011_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S000_I000 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1\nisacov.rv32i_addi_cg.cp_rd\nisacov.rv32i_addi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S000_I001 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1_value\nisacov.rv32i_addi_cg.cp_immi_value\n\ + isacov.rv32i_addi_cg.cross_rs1_immi_value\nisacov.rv32i_addi_cg.cp_rs1_toggle\n\ + isacov.rv32i_addi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S000_I002 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rd_value\nisacov.rv32i_addi_cg.cp_rd_toggle" + comments: '' +- 001_XORI: !Subfeature + name: 001_XORI + tag: VP_IP011_P001 + next_elt_id: 5 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S001_I000 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1\nisacov.rv32i_xori_cg.cp_rd\nisacov.rv32i_xori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S001_I001 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1_value\nisacov.rv32i_xori_cg.cp_immi_value\n\ + isacov.rv32i_xori_cg.cross_rs1_immi_value\nisacov.rv32i_xori_cg.cp_rs1_toggle\n\ + isacov.rv32i_xori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S001_I002 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rd_value\nisacov.rv32i_xori_cg.cp_rd_toggle" + comments: '' +- 002_ORI: !Subfeature + name: 002_ORI + tag: VP_IP011_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S002_I000 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1\nisacov.rv32i_ori_cg.cp_rd\nisacov.rv32i_ori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S002_I001 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1_value\nisacov.rv32i_ori_cg.cp_immi_value\n\ + isacov.rv32i_ori_cg.cross_rs1_immi_value\nisacov.rv32i_ori_cg.cp_rs1_toggle\n\ + isacov.rv32i_ori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S002_I002 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rd_value\nisacov.rv32i_ori_cg.cp_rd_toggle" + comments: '' +- 003_ANDI: !Subfeature + name: 003_ANDI + tag: VP_IP011_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S003_I000 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1\nisacov.rv32i_andi_cg.cp_rd\nisacov.rv32i_andi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S003_I001 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1_value\nisacov.rv32i_andi_cg.cp_immi_value\n\ + isacov.rv32i_andi_cg.cross_rs1_immi_value\nisacov.rv32i_andi_cg.cp_rs1_toggle\n\ + isacov.rv32i_andi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S003_I002 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rd_value\nisacov.rv32i_andi_cg.cp_rd_toggle" + comments: '' +- 004_SLTI: !Subfeature + name: 004_SLTI + tag: VP_IP011_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S004_I000 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1\nisacov.rv32i_slti_cg.cp_rd\nisacov.rv32i_slti_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S004_I001 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1_value\nisacov.rv32i_slti_cg.cp_immi_value\n\ + isacov.rv32i_slti_cg.cross_rs1_immi_value\nisacov.rv32i_slti_cg.cp_rs1_toggle\n\ + isacov.rv32i_slti_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S004_I002 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slti_cg.cp_rd_value + comments: '' +- 005_SLTIU: !Subfeature + name: 005_SLTIU + tag: VP_IP011_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S005_I000 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1\nisacov.rv32i_sltiu_cg.cp_rd\n\ + isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S005_I001 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1_value\nisacov.rv32i_sltiu_cg.cp_immi_value\n\ + isacov.rv32i_sltiu_cg.cross_rs1_immi_value\nisacov.rv32i_sltiu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltiu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S005_I002 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltiu_cg.cp_rd_value + comments: '' +- 006_SLLI: !Subfeature + name: 006_SLLI + tag: VP_IP011_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S006_I000 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1\nisacov.rv32i_slli_cg.cp_rd\nisacov.rv32i_slli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S006_I001 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1_value\nisacov.rv32i_slli_cg.cp_immi_value\n\ + isacov.rv32i_slli_cg.cross_rs1_immi_value\nisacov.rv32i_slli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S006_I002 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rd_value\nisacov.rv32i_slli_cg.cp_rd_toggle" + comments: '' +- 007_SRLI: !Subfeature + name: 007_SRLI + tag: VP_IP011_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S007_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1\nisacov.rv32i_srli_cg.cp_rd\nisacov.rv32i_srli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S007_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1_value\nisacov.rv32i_srli_cg.cp_immi_value\n\ + isacov.rv32i_srli_cg.cross_rs1_immi_value\nisacov.rv32i_srli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S007_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rd_value\nisacov.rv32i_srli_cg.cp_rd_toggle" + comments: '' +- 008_SRAI: !Subfeature + name: 008_SRAI + tag: VP_IP011_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S008_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1\nisacov.rv32i_srai_cg.cp_rd\nisacov.rv32i_srai_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S008_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1_value\nisacov.rv32i_srai_cg.cp_immi_value\n\ + isacov.rv32i_srai_cg.cross_rs1_immi_value\nisacov.rv32i_srai_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S008_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rd_value\nisacov.rv32i_srai_cg.cp_rd_toggle" + comments: '' +- 009_LUI: !Subfeature + name: 009_LUI + tag: VP_IP011_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S009_I000 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_lui_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S009_I001 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_immu_value\nisacov.rv32i_lui_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S009_I002 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_rd_value\nisacov.rv32i_lui_cg.cp_rd_toggle" + comments: '' +- 010_AUIPC: !Subfeature + name: 010_AUIPC + tag: VP_IP011_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S010_I000 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_auipc_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S010_I001 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_immu_value\nisacov.rv32i_auipc_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S010_I002 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_rd_value\nisacov.rv32i_auipc_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck deleted file mode 100644 index 4c356dddb..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck +++ /dev/null @@ -1,1828 +0,0 @@ -(VRV32I Register-Register Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I1 -sVwid_order -p12 -I1 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADD -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP001_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F001_S000_I000 -p34 -sVdescription -p35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_add_cg.cp_rs1\u000aisacov.rv32i_add_cg.cp_rs2\u000aisacov.rv32i_add_cg.cp_rd\u000aisacov.rv32i_add_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_add_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -g58 -sg23 -VVP_ISA_F001_S000_I001 -p62 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p63 -sg37 -VISA\u000aChapter 2.4 -p64 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p65 -sg41 -Visacov.rv32i_add_cg.cp_rs1_value\u000aisacov.rv32i_add_cg.cp_rs2_value\u000aisacov.rv32i_add_cg.cross_rs1_rs2_value\u000aisacov.rv32i_add_cg.cp_rs1_toggle\u000aisacov.rv32i_add_cg.cp_rs2_toggle -p66 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp67 -sg15 -(lp68 -sg53 -(lp69 -sg13 -(dp70 -g56 -I0 -ssbtp71 -a(V002 -p72 -g1 -(g29 -g3 -Ntp73 -Rp74 -(dp75 -g8 -g72 -sg23 -VVP_ISA_F001_S000_I002 -p76 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p77 -sg37 -VISA\u000aChapter 2.4 -p78 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p79 -sg41 -Visacov.rv32i_add_cg.cp_rd_value\u000aisacov.rv32i_add_cg.cp_rd_toggle -p80 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp81 -sg15 -(lp82 -sg53 -(lp83 -sg13 -(dp84 -g56 -I0 -ssbtp85 -asVrfu_list_1 -p86 -(lp87 -sg53 -(lp88 -sg13 -(dp89 -sbtp90 -a(V001_SUB -p91 -g1 -(g18 -g3 -Ntp92 -Rp93 -(dp94 -g22 -I3 -sg8 -g91 -sg23 -VVP_IP001_P001 -p95 -sg25 -(dp96 -sg12 -I1 -sg15 -(lp97 -(V000 -p98 -g1 -(g29 -g3 -Ntp99 -Rp100 -(dp101 -g8 -V000 -p102 -sg23 -VVP_ISA_F001_S001_I000 -p103 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p104 -sg37 -VISA\u000aChapter 2.4 -p105 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p106 -sg41 -Visacov.rv32i_sub_cg.cp_rs1\u000aisacov.rv32i_sub_cg.cp_rs2\u000aisacov.rv32i_sub_cg.cp_rd\u000aisacov.rv32i_sub_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sub_cg.cp_rd_rs2_hazard -p107 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp108 -sg15 -(lp109 -sg53 -(lp110 -sg13 -(dp111 -g56 -I0 -ssbtp112 -a(V001 -p113 -g1 -(g29 -g3 -Ntp114 -Rp115 -(dp116 -g8 -V001 -p117 -sg23 -VVP_ISA_F001_S001_I001 -p118 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p119 -sg37 -VISA\u000aChapter 2.4 -p120 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p121 -sg41 -Visacov.rv32i_sub_cg.cp_rs1_value\u000aisacov.rv32i_sub_cg.cp_rs2_value\u000aisacov.rv32i_sub_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sub_cg.cp_rs1_toggle\u000aisacov.rv32i_sub_cg.cp_rs2_toggle -p122 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp123 -sg15 -(lp124 -sg53 -(lp125 -sg13 -(dp126 -g56 -I0 -ssbtp127 -a(V002 -p128 -g1 -(g29 -g3 -Ntp129 -Rp130 -(dp131 -g8 -V002 -p132 -sg23 -VVP_ISA_F001_S001_I002 -p133 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_sub_cg.cp_rd_value\u000aisacov.rv32i_sub_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg86 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_AND -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I3 -sg8 -g147 -sg23 -VVP_IP001_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F001_S002_I000 -p159 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p162 -sg41 -Visacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard\u000aisacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -V001 -p173 -sg23 -VVP_ISA_F001_S002_I001 -p174 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p175 -sg37 -VISA\u000aChapter 2.4 -p176 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p177 -sg41 -Visacov.rv32i_and_cg.cp_rs1_value\u000aisacov.rv32i_and_cg.cp_rs2_value\u000aisacov.rv32i_and_cg.cross_rs1_rs2_value\u000aisacov.rv32i_and_cg.cp_rs1_toggle\u000aisacov.rv32i_and_cg.cp_rs2_toggle -p178 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp179 -sg15 -(lp180 -sg53 -(lp181 -sg13 -(dp182 -g56 -I0 -ssbtp183 -a(V002 -p184 -g1 -(g29 -g3 -Ntp185 -Rp186 -(dp187 -g8 -V002 -p188 -sg23 -VVP_ISA_F001_S002_I002 -p189 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p190 -sg37 -VISA\u000aChapter 2.4 -p191 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p192 -sg41 -Visacov.rv32i_and_cg.cp_rd_value\u000aisacov.rv32i_and_cg.cp_rd_toggle -p193 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp194 -sg15 -(lp195 -sg53 -(lp196 -sg13 -(dp197 -g56 -I0 -ssbtp198 -asg86 -(lp199 -sg53 -(lp200 -sg13 -(dp201 -sbtp202 -a(V003_OR -p203 -g1 -(g18 -g3 -Ntp204 -Rp205 -(dp206 -g22 -I3 -sg8 -g203 -sg23 -VVP_IP001_P003 -p207 -sg25 -(dp208 -sg12 -I3 -sg15 -(lp209 -(V000 -p210 -g1 -(g29 -g3 -Ntp211 -Rp212 -(dp213 -g8 -V000 -p214 -sg23 -VVP_ISA_F001_S003_I000 -p215 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p216 -sg37 -VISA\u000aChapter 2.4 -p217 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p218 -sg41 -Visacov.rv32i_or_cg.cp_rs1\u000aisacov.rv32i_or_cg.cp_rs2\u000aisacov.rv32i_or_cg.cp_rd\u000aisacov.rv32i_or_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_or_cg.cp_rd_rs2_hazard -p219 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp220 -sg15 -(lp221 -sg53 -(lp222 -sg13 -(dp223 -g56 -I0 -ssbtp224 -a(V001 -p225 -g1 -(g29 -g3 -Ntp226 -Rp227 -(dp228 -g8 -V001 -p229 -sg23 -VVP_ISA_F001_S003_I001 -p230 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p231 -sg37 -VISA\u000aChapter 2.4 -p232 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p233 -sg41 -Visacov.rv32i_or_cg.cp_rs1_value\u000aisacov.rv32i_or_cg.cp_rs2_value\u000aisacov.rv32i_or_cg.cross_rs1_rs2_value\u000aisacov.rv32i_or_cg.cp_rs1_toggle\u000aisacov.rv32i_or_cg.cp_rs2_toggle -p234 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp235 -sg15 -(lp236 -sg53 -(lp237 -sg13 -(dp238 -g56 -I0 -ssbtp239 -a(V002 -p240 -g1 -(g29 -g3 -Ntp241 -Rp242 -(dp243 -g8 -V002 -p244 -sg23 -VVP_ISA_F001_S003_I002 -p245 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p246 -sg37 -VISA\u000aChapter 2.4 -p247 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p248 -sg41 -Visacov.rv32i_or_cg.cp_rd_value\u000aisacov.rv32i_or_cg.cp_rd_toggle -p249 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp250 -sg15 -(lp251 -sg53 -(lp252 -sg13 -(dp253 -g56 -I0 -ssbtp254 -asg86 -(lp255 -sg53 -(lp256 -sg13 -(dp257 -sbtp258 -a(V004_XOR -p259 -g1 -(g18 -g3 -Ntp260 -Rp261 -(dp262 -g22 -I3 -sg8 -g259 -sg23 -VVP_IP001_P004 -p263 -sg25 -(dp264 -sg12 -I4 -sg15 -(lp265 -(V000 -p266 -g1 -(g29 -g3 -Ntp267 -Rp268 -(dp269 -g8 -V000 -p270 -sg23 -VVP_ISA_F001_S004_I000 -p271 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p272 -sg37 -VISA\u000aChapter 2.4 -p273 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p274 -sg41 -Visacov.rv32i_xor_cg.cp_rs1\u000aisacov.rv32i_xor_cg.cp_rs2\u000aisacov.rv32i_xor_cg.cp_rd\u000aisacov.rv32i_xor_cg.rd_rs1_hazard\u000aisacov.rv32i_xor_cg.rd_rs2_hazard -p275 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp276 -sg15 -(lp277 -sg53 -(lp278 -sg13 -(dp279 -g56 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F001_S004_I001 -p286 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p287 -sg37 -VISA\u000aChapter 2.4 -p288 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p289 -sg41 -Visacov.rv32i_xor_cg.cp_rs1_value\u000aisacov.rv32i_xor_cg.cp_rs2_value\u000aisacov.rv32i_xor_cg.cross_rs1_rs2_value\u000aisacov.rv32i_xor_cg.cp_rs1_toggle\u000aisacov.rv32i_xor_cg.cp_rs2_toggle -p290 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp291 -sg15 -(lp292 -sg53 -(lp293 -sg13 -(dp294 -g56 -I0 -ssbtp295 -a(V002 -p296 -g1 -(g29 -g3 -Ntp297 -Rp298 -(dp299 -g8 -V002 -p300 -sg23 -VVP_ISA_F001_S004_I002 -p301 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p302 -sg37 -VISA\u000aChapter 2.4 -p303 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p304 -sg41 -Visacov.rv32i_xor_cg.cp_rd_value\u000aisacov.rv32i_xor_cg.cp_rd_toggle -p305 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp306 -sg15 -(lp307 -sg53 -(lp308 -sg13 -(dp309 -g56 -I0 -ssbtp310 -asg86 -(lp311 -sg53 -(lp312 -sg13 -(dp313 -sbtp314 -a(V005_SLT -p315 -g1 -(g18 -g3 -Ntp316 -Rp317 -(dp318 -g22 -I3 -sg8 -g315 -sg23 -VVP_IP001_P005 -p319 -sg25 -(dp320 -sg12 -I5 -sg15 -(lp321 -(V000 -p322 -g1 -(g29 -g3 -Ntp323 -Rp324 -(dp325 -g8 -V000 -p326 -sg23 -VVP_ISA_F001_S005_I000 -p327 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p328 -sg37 -VISA\u000aChapter 2.4 -p329 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p330 -sg41 -Visacov.rv32i_slt_cg.cp_rs1\u000aisacov.rv32i_slt_cg.cp_rs2\u000aisacov.rv32i_slt_cg.cp_rd\u000aisacov.rv32i_slt_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_slt_cg.cp_rd_rs2_hazard -p331 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp332 -sg15 -(lp333 -sg53 -(lp334 -sg13 -(dp335 -g56 -I0 -ssbtp336 -a(V001 -p337 -g1 -(g29 -g3 -Ntp338 -Rp339 -(dp340 -g8 -V001 -p341 -sg23 -VVP_ISA_F001_S005_I001 -p342 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p343 -sg37 -VISA\u000aChapter 2.4 -p344 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p345 -sg41 -Visacov.rv32i_slt_cg.cp_rs1_value\u000aisacov.rv32i_slt_cg.cp_rs2_value\u000aisacov.rv32i_slt_cg.cross_rs1_rs2_value\u000aisacov.rv32i_slt_cg.cp_rs1_toggle\u000aisacov.rv32i_slt_cg.cp_rs2_toggle -p346 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp347 -sg15 -(lp348 -sg53 -(lp349 -sg13 -(dp350 -g56 -I0 -ssbtp351 -a(V002 -p352 -g1 -(g29 -g3 -Ntp353 -Rp354 -(dp355 -g8 -V002 -p356 -sg23 -VVP_ISA_F001_S005_I002 -p357 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p358 -sg37 -VISA\u000aChapter 2.4 -p359 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p360 -sg41 -Visacov.rv32i_slt_cg.cp_rd_value -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg86 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_SLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP001_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F001_S006_I000 -p383 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p384 -sg37 -VISA\u000aChapter 2.4 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p386 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1\u000aisacov.rv32i_sltu_cg.cp_rs2\u000aisacov.rv32i_sltu_cg.cp_rd\u000aisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sltu_cg.cp_rd_rs2_hazard -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F001_S006_I001 -p398 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p399 -sg37 -VISA\u000aChapter 2.4 -p400 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1_value\u000aisacov.rv32i_sltu_cg.cp_rs2_value\u000aisacov.rv32i_sltu_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sltu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F001_S006_I002 -p413 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p414 -sg37 -VISA\u000aChapter 2.4 -p415 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p416 -sg41 -Visacov.rv32i_sltu_cg.cp_rd_value -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg86 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_SLL -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP001_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F001_S007_I000 -p439 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p440 -sg37 -VISA\u000aChapter 2.4 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p442 -sg41 -Visacov.rv32i_sll_cg.cp_rs1\u000aisacov.rv32i_sll_cg.cp_rs2\u000aisacov.rv32i_sll_cg.cp_rd\u000aisacov.rv32i_sll_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sll_cg.cp_rd_rs2_hazard -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F001_S007_I001 -p454 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p455 -sg37 -VISA\u000aChapter 2.4 -p456 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p457 -sg41 -Visacov.rv32i_sll_cg.cp_rs1_value\u000aisacov.rv32i_sll_cg.cp_rs2_value\u000aisacov.rv32i_sll_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sll_cg.cp_rs1_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F001_S007_I002 -p469 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p470 -sg37 -VISA\u000aChapter 2.4 -p471 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p472 -sg41 -Visacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle\u000aisacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg86 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -a(V008_SRL -p483 -g1 -(g18 -g3 -Ntp484 -Rp485 -(dp486 -g22 -I3 -sg8 -g483 -sg23 -VVP_IP001_P008 -p487 -sg25 -(dp488 -sg12 -I8 -sg15 -(lp489 -(V000 -p490 -g1 -(g29 -g3 -Ntp491 -Rp492 -(dp493 -g8 -V000 -p494 -sg23 -VVP_ISA_F001_S008_I000 -p495 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p496 -sg37 -VISA\u000aChapter 2.4 -p497 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p498 -sg41 -Visacov.rv32i_srl_cg.cp_rs1\u000aisacov.rv32i_srl_cg.cp_rs2\u000aisacov.rv32i_srl_cg.cp_rd\u000aisacov.rv32i_srl_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_srl_cg.cp_rd_rs2_hazard -p499 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp500 -sg15 -(lp501 -sg53 -(lp502 -sg13 -(dp503 -g56 -I0 -ssbtp504 -a(V001 -p505 -g1 -(g29 -g3 -Ntp506 -Rp507 -(dp508 -g8 -V001 -p509 -sg23 -VVP_ISA_F001_S008_I001 -p510 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p511 -sg37 -VISA\u000aChapter 2.4 -p512 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p513 -sg41 -Visacov.rv32i_srl_cg.cp_rs1_value\u000aisacov.rv32i_srl_cg.cp_rs2_value\u000aisacov.rv32i_srl_cg.cross_rs1_rs2_value\u000aisacov.rv32i_srl_cg.cp_rs1_toggle -p514 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp515 -sg15 -(lp516 -sg53 -(lp517 -sg13 -(dp518 -g56 -I0 -ssbtp519 -a(V002 -p520 -g1 -(g29 -g3 -Ntp521 -Rp522 -(dp523 -g8 -V002 -p524 -sg23 -VVP_ISA_F001_S008_I002 -p525 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p526 -sg37 -VISA\u000aChapter 2.4 -p527 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p528 -sg41 -Visacov.rv32i_srl_cg.cp_rd_value\u000aisacov.rv32i_srl_cg.cp_rd_toggle -p529 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp530 -sg15 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -g56 -I0 -ssbtp534 -asg86 -(lp535 -sg53 -(lp536 -sg13 -(dp537 -sbtp538 -a(V009_SRA -p539 -g1 -(g18 -g3 -Ntp540 -Rp541 -(dp542 -g22 -I3 -sg8 -g539 -sg23 -VVP_IP001_P009 -p543 -sg25 -(dp544 -sg12 -I9 -sg15 -(lp545 -(V000 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V000 -p550 -sg23 -VVP_ISA_F001_S009_I000 -p551 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p552 -sg37 -VISA\u000aChapter 2.4 -p553 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p554 -sg41 -Visacov.rv32i_sra_cg.cp_rs1\u000aisacov.rv32i_sra_cg.cp_rs2\u000aisacov.rv32i_sra_cg.cp_rd\u000aisacov.rv32i_sra_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sra_cg.cp_rd_rs2_hazard -p555 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp556 -sg15 -(lp557 -sg53 -(lp558 -sg13 -(dp559 -g56 -I0 -ssbtp560 -a(V001 -p561 -g1 -(g29 -g3 -Ntp562 -Rp563 -(dp564 -g8 -V001 -p565 -sg23 -VVP_ISA_F001_S009_I001 -p566 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p567 -sg37 -VISA\u000aChapter 2.4 -p568 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve, and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 +ve, -ve and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p569 -sg41 -Visacov.rv32i_sra_cg.cp_rs1_value\u000aisacov.rv32i_sra_cg.cp_rs2_value\u000aisacov.rv32i_sra_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sra_cg.cp_rs1_toggle -p570 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp571 -sg15 -(lp572 -sg53 -(lp573 -sg13 -(dp574 -g56 -I0 -ssbtp575 -a(V002 -p576 -g1 -(g29 -g3 -Ntp577 -Rp578 -(dp579 -g8 -V002 -p580 -sg23 -VVP_ISA_F001_S009_I002 -p581 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p582 -sg37 -VISA\u000aChapter 2.4 -p583 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve, and zero.\u000aAll bits of rd are toggled -p584 -sg41 -Visacov.rv32i_sra_cg.cp_rd_value\u000aisacov.rv32i_sra_cg.cp_rd_toggle -p585 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp586 -sg15 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -g56 -I0 -ssbtp590 -asg86 -(lp591 -sg53 -(lp592 -sg13 -(dp593 -sbtp594 -asVrfu_list_0 -p595 -(lp596 -sg86 -(lp597 -sVvptool_gitrev -p598 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p599 -sVio_fmt_gitrev -p600 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p601 -sVconfig_gitrev -p602 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p603 -sVymlcfg_gitrev -p604 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p605 -sbtp606 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml new file mode 100644 index 000000000..81184060b --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -0,0 +1,665 @@ +!Feature +next_elt_id: 10 +name: RV32I Register-Register Instructions +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_ADD: !Subfeature + name: 000_ADD + tag: VP_IP001_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S000_I000 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1\nisacov.rv32i_add_cg.cp_rs2\nisacov.rv32i_add_cg.cp_rd\n\ + isacov.rv32i_add_cg.cp_rd_rs1_hazard\nisacov.rv32i_add_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S000_I001 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1_value\nisacov.rv32i_add_cg.cp_rs2_value\n\ + isacov.rv32i_add_cg.cross_rs1_rs2_value\nisacov.rv32i_add_cg.cp_rs1_toggle\n\ + isacov.rv32i_add_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S000_I002 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rd_value\nisacov.rv32i_add_cg.cp_rd_toggle" + comments: '' +- 001_SUB: !Subfeature + name: 001_SUB + tag: VP_IP001_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S001_I000 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1\nisacov.rv32i_sub_cg.cp_rs2\nisacov.rv32i_sub_cg.cp_rd\n\ + isacov.rv32i_sub_cg.cp_rd_rs1_hazard\nisacov.rv32i_sub_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S001_I001 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1_value\nisacov.rv32i_sub_cg.cp_rs2_value\n\ + isacov.rv32i_sub_cg.cross_rs1_rs2_value\nisacov.rv32i_sub_cg.cp_rs1_toggle\n\ + isacov.rv32i_sub_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S001_I002 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rd_value\nisacov.rv32i_sub_cg.cp_rd_toggle" + comments: '' +- 002_AND: !Subfeature + name: 002_AND + tag: VP_IP001_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S002_I000 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard\n\ + isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S002_I001 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1_value\nisacov.rv32i_and_cg.cp_rs2_value\n\ + isacov.rv32i_and_cg.cross_rs1_rs2_value\nisacov.rv32i_and_cg.cp_rs1_toggle\n\ + isacov.rv32i_and_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S002_I002 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rd_value\nisacov.rv32i_and_cg.cp_rd_toggle" + comments: '' +- 003_OR: !Subfeature + name: 003_OR + tag: VP_IP001_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S003_I000 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1\nisacov.rv32i_or_cg.cp_rs2\nisacov.rv32i_or_cg.cp_rd\n\ + isacov.rv32i_or_cg.cp_rd_rs1_hazard\nisacov.rv32i_or_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S003_I001 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1_value\nisacov.rv32i_or_cg.cp_rs2_value\n\ + isacov.rv32i_or_cg.cross_rs1_rs2_value\nisacov.rv32i_or_cg.cp_rs1_toggle\n\ + isacov.rv32i_or_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S003_I002 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rd_value\nisacov.rv32i_or_cg.cp_rd_toggle" + comments: '' +- 004_XOR: !Subfeature + name: 004_XOR + tag: VP_IP001_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S004_I000 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1\nisacov.rv32i_xor_cg.cp_rs2\nisacov.rv32i_xor_cg.cp_rd\n\ + isacov.rv32i_xor_cg.rd_rs1_hazard\nisacov.rv32i_xor_cg.rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S004_I001 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1_value\nisacov.rv32i_xor_cg.cp_rs2_value\n\ + isacov.rv32i_xor_cg.cross_rs1_rs2_value\nisacov.rv32i_xor_cg.cp_rs1_toggle\n\ + isacov.rv32i_xor_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S004_I002 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rd_value\nisacov.rv32i_xor_cg.cp_rd_toggle" + comments: '' +- 005_SLT: !Subfeature + name: 005_SLT + tag: VP_IP001_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S005_I000 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1\nisacov.rv32i_slt_cg.cp_rs2\nisacov.rv32i_slt_cg.cp_rd\n\ + isacov.rv32i_slt_cg.cp_rd_rs1_hazard\nisacov.rv32i_slt_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S005_I001 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1_value\nisacov.rv32i_slt_cg.cp_rs2_value\n\ + isacov.rv32i_slt_cg.cross_rs1_rs2_value\nisacov.rv32i_slt_cg.cp_rs1_toggle\n\ + isacov.rv32i_slt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S005_I002 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slt_cg.cp_rd_value + comments: '' +- 006_SLTU: !Subfeature + name: 006_SLTU + tag: VP_IP001_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S006_I000 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1\nisacov.rv32i_sltu_cg.cp_rs2\n\ + isacov.rv32i_sltu_cg.cp_rd\nisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\nisacov.rv32i_sltu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S006_I001 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1_value\nisacov.rv32i_sltu_cg.cp_rs2_value\n\ + isacov.rv32i_sltu_cg.cross_rs1_rs2_value\nisacov.rv32i_sltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S006_I002 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltu_cg.cp_rd_value + comments: '' +- 007_SLL: !Subfeature + name: 007_SLL + tag: VP_IP001_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S007_I000 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1\nisacov.rv32i_sll_cg.cp_rs2\nisacov.rv32i_sll_cg.cp_rd\n\ + isacov.rv32i_sll_cg.cp_rd_rs1_hazard\nisacov.rv32i_sll_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S007_I001 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1_value\nisacov.rv32i_sll_cg.cp_rs2_value\n\ + isacov.rv32i_sll_cg.cross_rs1_rs2_value\nisacov.rv32i_sll_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S007_I002 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle\n\ + isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle" + comments: '' +- 008_SRL: !Subfeature + name: 008_SRL + tag: VP_IP001_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S008_I000 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1\nisacov.rv32i_srl_cg.cp_rs2\nisacov.rv32i_srl_cg.cp_rd\n\ + isacov.rv32i_srl_cg.cp_rd_rs1_hazard\nisacov.rv32i_srl_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S008_I001 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1_value\nisacov.rv32i_srl_cg.cp_rs2_value\n\ + isacov.rv32i_srl_cg.cross_rs1_rs2_value\nisacov.rv32i_srl_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S008_I002 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rd_value\nisacov.rv32i_srl_cg.cp_rd_toggle" + comments: '' +- 009_SRA: !Subfeature + name: 009_SRA + tag: VP_IP001_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S009_I000 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1\nisacov.rv32i_sra_cg.cp_rs2\nisacov.rv32i_sra_cg.cp_rd\n\ + isacov.rv32i_sra_cg.cp_rd_rs1_hazard\nisacov.rv32i_sra_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S009_I001 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve, and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 +ve, -ve and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1_value\nisacov.rv32i_sra_cg.cp_rs2_value\n\ + isacov.rv32i_sra_cg.cross_rs1_rs2_value\nisacov.rv32i_sra_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S009_I002 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve, and zero.\nAll bits\ + \ of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rd_value\nisacov.rv32i_sra_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck deleted file mode 100644 index e2b333919..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck +++ /dev/null @@ -1,1478 +0,0 @@ -(VRV32I Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I2 -sVwid_order -p12 -I2 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_JAL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP002_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F002_S000_I000 -p34 -sVdescription -p35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p36 -sVpurpose -p37 -VISA\u000aChapter 2.5 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -Visacov.rv32i_jal_cg.cp_rd -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F002_S000_I001 -p63 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p64 -sg37 -VISA\u000aChapter 2.5 -p65 -sg39 -VInput operands:\u000a\u000aimmj value is +ve, -ve, and zero\u000aAll bits of immj are toggled -p66 -sg41 -Visacov.rv32i_jal_cg.cp_immj_value\u000aisacov.rv32i_jal_cg.cp_immj_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F002_S000_I002 -p78 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p79 -sg37 -VISA\u000aChapter 2.5 -p80 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_jal_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_JALR -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP002_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F002_S001_I000 -p105 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.5 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_jalr_cg.cp_rs1\u000aisacov.rv32i_jalr_cg.cp_rd\u000aisacov.rv32i_jalr_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F002_S001_I001 -p120 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.5 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve, and zero\u000aAll bits of immi are toggled\u000aAll bits of rs1 are toggled -p123 -sg41 -Visacov.rv32i_jalr_cg.cp_immi_value\u000aisacov.rv32i_jalr_cg.cp_immi_toggle\u000aisacov.rv32i_jalr_cg.cp_rs1_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F002_S001_I002 -p135 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.5 -p137 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_jalr_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_BEQ -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP002_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F002_S002_I000 -p161 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.5 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p164 -sg41 -Visacov.rv32i_beq_cg.cp_rs1\u000aisacov.rv32i_beq_cg.cp_rs2 -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F002_S002_I001 -p176 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.5 -p178 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32i_beq_cg.cp_immb_value\u000aisacov.rv32i_beq_cg.cp_rs1_toggle\u000aisacov.rv32i_beq_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F002_S002_I002 -p191 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.5 -p193 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p194 -sg41 -Visacov.rv32i_beq_cg.cp_branch_taken -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_BNE -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP002_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F002_S003_I000 -p217 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p218 -sg37 -VISA\u000aChapter 2.5 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p220 -sg41 -Visacov.rv32i_bne_cg.cp_rs1\u000aisacov.rv32i_bne_cg.cp_rs2 -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F002_S003_I001 -p232 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p233 -sg37 -VISA\u000aChapter 2.5 -p234 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32i_bne_cg.cp_immb_value\u000aisacov.rv32i_bne_cg.cp_rs1_toggle\u000aisacov.rv32i_bne_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F002_S003_I002 -p247 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p248 -sg37 -VISA\u000aChapter 2.5 -p249 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p250 -sg41 -Visacov.rv32i_bne_cg.cp_branch_taken -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_BLT -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP002_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F002_S004_I000 -p273 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p274 -sg37 -VISA\u000aChapter 2.5 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p276 -sg41 -Visacov.rv32i_blt_cg.cp_rs1\u000aisacov.rv32i_blt_cg.cp_rs2 -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F002_S004_I001 -p288 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p289 -sg37 -VISA\u000aChapter 2.5 -p290 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p291 -sg41 -Visacov.rv32i_blt_cg.cp_immb_value\u000aisacov.rv32i_blt_cg.cp_rs1_toggle\u000aisacov.rv32i_blt_cg.cp_rs2_toggle -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F002_S004_I002 -p303 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p304 -sg37 -VISA\u000aChapter 2.5 -p305 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p306 -sg41 -Visacov.rv32i_blt_cg.cp_branch_taken -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_BGE -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I6 -sg8 -g317 -sg23 -VVP_IP002_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F002_S005_I000 -p329 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p330 -sg37 -VISA\u000aChapter 2.5 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_bge_cg.cp_rs1\u000aisacov.rv32i_bge_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -g339 -sg23 -VVP_ISA_F002_S005_I001 -p343 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p344 -sg37 -VISA\u000aChapter 2.5 -p345 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p346 -sg41 -Visacov.rv32i_bge_cg.cp_immb_value\u000aisacov.rv32i_bge_cg.cp_rs1_toggle\u000aisacov.rv32i_bge_cg.cp_rs2_toggle -p347 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp348 -sg15 -(lp349 -sg53 -(lp350 -sg13 -(dp351 -g56 -I0 -ssbtp352 -a(V002 -p353 -g1 -(g29 -g3 -Ntp354 -Rp355 -(dp356 -g8 -g353 -sg23 -VVP_ISA_F002_S005_I002 -p357 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p358 -sg37 -VISA\u000aChapter 2.5 -p359 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p360 -sg41 -Visacov.rv32i_bge_cg.cp_branch_taken -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg88 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_BLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP002_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F002_S006_I000 -p383 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p384 -sg37 -VISA\u000aChapter 2.5 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p386 -sg41 -Visacov.rv32i_bltu_cg.cp_rs1\u000aisacov.rv32i_bltu_cg.cp_rs2 -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F002_S006_I001 -p398 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p399 -sg37 -VISA\u000aChapter 2.5 -p400 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_bltu_cg.cp_immb_value\u000aisacov.rv32i_bltu_cg.cp_rs1_toggle\u000aisacov.rv32i_bltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F002_S006_I002 -p413 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p414 -sg37 -VISA\u000aChapter 2.5 -p415 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p416 -sg41 -Visacov.rv32i_bltu_cg.cp_branch_taken -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg88 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_BGEU -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP002_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F002_S007_I000 -p439 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p440 -sg37 -VISA\u000aChapter 2.5 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p442 -sg41 -Visacov.rv32i_bgeu_cg.cp_rs1\u000aisacov.rv32i_bgeu_cg.cp_rs2 -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F002_S007_I001 -p454 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p455 -sg37 -VISA\u000aChapter 2.5 -p456 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p457 -sg41 -Visacov.rv32i_bgeu_cg.cp_immb_value\u000aisacov.rv32i_bgeu_cg.cp_rs1_toggle\u000aisacov.rv32i_bgeu_cg.cp_rs2_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F002_S007_I002 -p469 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p470 -sg37 -VISA\u000aChapter 2.5 -p471 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p472 -sg41 -Visacov.rv32i_bgeu_cg.cp_branch_taken -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg88 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -asVrfu_list_0 -p483 -(lp484 -sg88 -(lp485 -sVvptool_gitrev -p486 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p487 -sVio_fmt_gitrev -p488 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p489 -sVconfig_gitrev -p490 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p491 -sVymlcfg_gitrev -p492 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p493 -sbtp494 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml new file mode 100644 index 000000000..a6903df29 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -0,0 +1,498 @@ +!Feature +next_elt_id: 8 +name: RV32I Control Transfer Instructions +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_JAL: !Subfeature + name: 000_JAL + tag: VP_IP002_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S000_I000 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S000_I001 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmj value is +ve, -ve, and zero\nAll bits\ + \ of immj are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jal_cg.cp_immj_value\nisacov.rv32i_jal_cg.cp_immj_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S000_I002 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd_toggle + comments: '' +- 001_JALR: !Subfeature + name: 001_JALR + tag: VP_IP002_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S001_I000 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_rs1\nisacov.rv32i_jalr_cg.cp_rd\nisacov.rv32i_jalr_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S001_I001 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve, and zero\nAll bits\ + \ of immi are toggled\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_immi_value\nisacov.rv32i_jalr_cg.cp_immi_toggle\n\ + isacov.rv32i_jalr_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S001_I002 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jalr_cg.cp_rd_toggle + comments: '' +- 002_BEQ: !Subfeature + name: 002_BEQ + tag: VP_IP002_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S002_I000 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_rs1\nisacov.rv32i_beq_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S002_I001 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_immb_value\nisacov.rv32i_beq_cg.cp_rs1_toggle\n\ + isacov.rv32i_beq_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S002_I002 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_beq_cg.cp_branch_taken + comments: '' +- 003_BNE: !Subfeature + name: 003_BNE + tag: VP_IP002_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S003_I000 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_rs1\nisacov.rv32i_bne_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S003_I001 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_immb_value\nisacov.rv32i_bne_cg.cp_rs1_toggle\n\ + isacov.rv32i_bne_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S003_I002 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bne_cg.cp_branch_taken + comments: '' +- 004_BLT: !Subfeature + name: 004_BLT + tag: VP_IP002_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S004_I000 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_rs1\nisacov.rv32i_blt_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S004_I001 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_immb_value\nisacov.rv32i_blt_cg.cp_rs1_toggle\n\ + isacov.rv32i_blt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S004_I002 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_blt_cg.cp_branch_taken + comments: '' +- 005_BGE: !Subfeature + name: 005_BGE + tag: VP_IP002_P005 + next_elt_id: 6 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S005_I000 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_rs1\nisacov.rv32i_bge_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S005_I001 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_immb_value\nisacov.rv32i_bge_cg.cp_rs1_toggle\n\ + isacov.rv32i_bge_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S005_I002 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bge_cg.cp_branch_taken + comments: '' +- 006_BLTU: !Subfeature + name: 006_BLTU + tag: VP_IP002_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S006_I000 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_rs1\nisacov.rv32i_bltu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S006_I001 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_immb_value\nisacov.rv32i_bltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S006_I002 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bltu_cg.cp_branch_taken + comments: '' +- 007_BGEU: !Subfeature + name: 007_BGEU + tag: VP_IP002_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S007_I000 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_rs1\nisacov.rv32i_bgeu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S007_I001 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_immb_value\nisacov.rv32i_bgeu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bgeu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S007_I002 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bgeu_cg.cp_branch_taken + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck deleted file mode 100644 index bcd79324f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck +++ /dev/null @@ -1,1333 +0,0 @@ -(VRV32I Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP003_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F003_S000_I000 -p34 -sVdescription -p35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VISA\u000aChapter 2.6 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_lb_cg.cp_rs1\u000aisacov.rv32i_lb_cg.cp_rd\u000aisacov.rv32i_lb_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F003_S000_I001 -p63 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p64 -sg37 -VISA\u000aChapter 2.6 -p65 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_lb_cg.cp_immi_value\u000aisacov.rv32i_lb_cg.cp_rs1_toggle\u000aisacov.rv32i_lb_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F003_S000_I002 -p78 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p79 -sg37 -VISA\u000aChapter 2.6 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_lb_cg.cp_rd_value\u000aisacov.rv32i_lb_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_LH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP003_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F003_S001_I000 -p105 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.6 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_lh_cg.cp_rs1\u000aisacov.rv32i_lh_cg.cp_rd\u000aisacov.rv32i_lh_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F003_S001_I001 -p120 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.6 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p123 -sg41 -Visacov.rv32i_lh_cg.cp_immi_value\u000aisacov.rv32i_lh_cg.cp_rs1_toggle\u000aisacov.rv32i_lh_cg.cp_immi_toggle\u000aisacov.rv32i_lh_cg.cp_aligned -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F003_S001_I002 -p135 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.6 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_lh_cg.cp_rd_value\u000aisacov.rv32i_lh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_LW -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP003_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F003_S002_I000 -p161 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.6 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p164 -sg41 -Visacov.rv32i_lw_cg.cp_rs1\u000aisacov.rv32i_lw_cg.cp_rd\u000aisacov.rv32i_lw_cg.cp_rd_rs1_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F003_S002_I001 -p176 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.6 -p178 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p179 -sg41 -Visacov.rv32i_lw_cg.cp_immi_value\u000aisacov.rv32i_lw_cg.cp_rs1_toggle\u000aisacov.rv32i_lw_cg.cp_immi_toggle\u000aisacov.rv32i_lw_cg.cp_aligned -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F003_S002_I002 -p191 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.6 -p193 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32i_lw_cg.cp_rd_value\u000aisacov.rv32i_lw_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_LBU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP003_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F003_S003_I000 -p217 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p218 -sg37 -VISA\u000aChapter 2.6 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p220 -sg41 -Visacov.rv32i_lbu_cg.cp_rs1\u000aisacov.rv32i_lbu_cg.cp_rd\u000aisacov.rv32i_lbu_cg.cp_rd_rs1_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F003_S003_I001 -p232 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p233 -sg37 -VISA\u000aChapter 2.6 -p234 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p235 -sg41 -Visacov.rv32i_lbu_cg.cp_immi_value\u000aisacov.rv32i_lbu_cg.cp_rs1_toggle\u000aisacov.rv32i_lbu_cg.cp_immi_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F003_S003_I002 -p247 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p248 -sg37 -VISA\u000aChapter 2.6 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[7:0] are toggled -p250 -sg41 -Visacov.rv32i_lbu_cg.cp_rd_value\u000aisacov.rv32i_lbu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_LHU -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP003_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F003_S004_I000 -p273 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p274 -sg37 -VISA\u000aChapter 2.6 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p276 -sg41 -Visacov.rv32i_lhu_cg.cp_rs1\u000aisacov.rv32i_lhu_cg.cp_rd\u000aisacov.rv32i_lhu_cg.cp_rd_rs1_hazard -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F003_S004_I001 -p288 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p289 -sg37 -VISA\u000aChapter 2.6 -p290 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p291 -sg41 -Visacov.rv32i_lhu_cg.cp_immi_value\u000aisacov.rv32i_lhu_cg.cp_rs1_toggle\u000aisacov.rv32i_lhu_cg.cp_immi_toggle\u000aisacov.rv32i_lhu_cg.cp_aligned -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F003_S004_I002 -p303 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p304 -sg37 -VISA\u000aChapter 2.6 -p305 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[15:0] are toggled -p306 -sg41 -Visacov.rv32i_lhu_cg.cp_rd_value\u000aisacov.rv32i_lhu_cg.cp_rd_toggle -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_SB -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I3 -sg8 -g317 -sg23 -VVP_IP003_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F003_S005_I000 -p329 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p330 -sg37 -VISA\u000aChapter 2.6 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_sb_cg.cp_rs1\u000aisacov.rv32i_sb_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -V001 -p343 -sg23 -VVP_ISA_F003_S005_I001 -p344 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p345 -sg37 -VISA\u000aChapter 2.6 -p346 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled -p347 -sg41 -Visacov.rv32i_sb_cg.cp_imms_value\u000aisacov.rv32i_sb_cg.cp_rs1_toggle\u000aisacov.rv32i_sb_cg.cp_rs2_toggle\u000aisacov.rv32i_sb_cg.cp_imms_toggle -p348 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp349 -sg15 -(lp350 -sg53 -(lp351 -sg13 -(dp352 -g56 -I0 -ssbtp353 -asg88 -(lp354 -sg53 -(lp355 -sg13 -(dp356 -sbtp357 -a(V006_SH -p358 -g1 -(g18 -g3 -Ntp359 -Rp360 -(dp361 -g22 -I2 -sg8 -g358 -sg23 -VVP_IP003_P006 -p362 -sg25 -(dp363 -sg12 -I6 -sg15 -(lp364 -(V000 -p365 -g1 -(g29 -g3 -Ntp366 -Rp367 -(dp368 -g8 -V000 -p369 -sg23 -VVP_ISA_F003_S006_I000 -p370 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p371 -sg37 -VISA\u000aChapter 2.6 -p372 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p373 -sg41 -Visacov.rv32i_sh_cg.cp_rs1\u000aisacov.rv32i_sh_cg.cp_rs2 -p374 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp375 -sg15 -(lp376 -sg53 -(lp377 -sg13 -(dp378 -g56 -I0 -ssbtp379 -a(V001 -p380 -g1 -(g29 -g3 -Ntp381 -Rp382 -(dp383 -g8 -V001 -p384 -sg23 -VVP_ISA_F003_S006_I001 -p385 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p386 -sg37 -VISA\u000aChapter 2.6 -p387 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p388 -sg41 -Visacov.rv32i_sh_cg.cp_imms_value\u000aisacov.rv32i_sh_cg.cp_rs1_toggle\u000aisacov.rv32i_sh_cg.cp_rs2_toggle\u000aisacov.rv32i_sh_cg.cp_imms_toggle\u000aisacov.rv32i_sh_cg.cp_aligned -p389 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp390 -sg15 -(lp391 -sg53 -(lp392 -sg13 -(dp393 -g56 -I0 -ssbtp394 -asg88 -(lp395 -sg53 -(lp396 -sg13 -(dp397 -sbtp398 -a(V007_SW -p399 -g1 -(g18 -g3 -Ntp400 -Rp401 -(dp402 -g22 -I2 -sg8 -g399 -sg23 -VVP_IP003_P007 -p403 -sg25 -(dp404 -sg12 -I7 -sg15 -(lp405 -(V000 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V000 -p410 -sg23 -VVP_ISA_F003_S007_I000 -p411 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p412 -sg37 -VISA\u000aChapter 2.6 -p413 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p414 -sg41 -Visacov.rv32i_sw_cg.cp_rs1\u000aisacov.rv32i_sw_cg.cp_rs2 -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -a(V001 -p421 -g1 -(g29 -g3 -Ntp422 -Rp423 -(dp424 -g8 -V001 -p425 -sg23 -VVP_ISA_F003_S007_I001 -p426 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p427 -sg37 -VISA\u000aChapter 2.6 -p428 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p429 -sg41 -Visacov.rv32i_sw_cg.cp_imms_value\u000aisacov.rv32i_sw_cg.cp_rs1_toggle\u000aisacov.rv32i_sw_cg.cp_rs2_toggle\u000aisacov.rv32i_sw_cg.cp_imms_toggle\u000aisacov.rv32i_sw_cg.cp_aligned -p430 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp431 -sg15 -(lp432 -sg53 -(lp433 -sg13 -(dp434 -g56 -I0 -ssbtp435 -asg88 -(lp436 -sg53 -(lp437 -sg13 -(dp438 -sbtp439 -asVrfu_list_0 -p440 -(lp441 -sg88 -(lp442 -sVvptool_gitrev -p443 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p444 -sVio_fmt_gitrev -p445 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p446 -sVconfig_gitrev -p447 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p448 -sVymlcfg_gitrev -p449 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p450 -sbtp451 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml new file mode 100644 index 000000000..cf67b09c1 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -0,0 +1,454 @@ +!Feature +next_elt_id: 8 +name: RV32I Load and Store Instructions +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_LB: !Subfeature + name: 000_LB + tag: VP_IP003_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S000_I000 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rs1\nisacov.rv32i_lb_cg.cp_rd\nisacov.rv32i_lb_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S000_I001 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_immi_value\nisacov.rv32i_lb_cg.cp_rs1_toggle\n\ + isacov.rv32i_lb_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S000_I002 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rd_value\nisacov.rv32i_lb_cg.cp_rd_toggle" + comments: '' +- 001_LH: !Subfeature + name: 001_LH + tag: VP_IP003_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S001_I000 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rs1\nisacov.rv32i_lh_cg.cp_rd\nisacov.rv32i_lh_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S001_I001 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_immi_value\nisacov.rv32i_lh_cg.cp_rs1_toggle\n\ + isacov.rv32i_lh_cg.cp_immi_toggle\nisacov.rv32i_lh_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S001_I002 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rd_value\nisacov.rv32i_lh_cg.cp_rd_toggle" + comments: '' +- 002_LW: !Subfeature + name: 002_LW + tag: VP_IP003_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S002_I000 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rs1\nisacov.rv32i_lw_cg.cp_rd\nisacov.rv32i_lw_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S002_I001 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_immi_value\nisacov.rv32i_lw_cg.cp_rs1_toggle\n\ + isacov.rv32i_lw_cg.cp_immi_toggle\nisacov.rv32i_lw_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S002_I002 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rd_value\nisacov.rv32i_lw_cg.cp_rd_toggle" + comments: '' +- 003_LBU: !Subfeature + name: 003_LBU + tag: VP_IP003_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S003_I000 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rs1\nisacov.rv32i_lbu_cg.cp_rd\nisacov.rv32i_lbu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S003_I001 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_immi_value\nisacov.rv32i_lbu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lbu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S003_I002 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[7:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rd_value\nisacov.rv32i_lbu_cg.cp_rd_toggle" + comments: '' +- 004_LHU: !Subfeature + name: 004_LHU + tag: VP_IP003_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S004_I000 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rs1\nisacov.rv32i_lhu_cg.cp_rd\nisacov.rv32i_lhu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S004_I001 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_immi_value\nisacov.rv32i_lhu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lhu_cg.cp_immi_toggle\nisacov.rv32i_lhu_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S004_I002 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[15:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rd_value\nisacov.rv32i_lhu_cg.cp_rd_toggle" + comments: '' +- 005_SB: !Subfeature + name: 005_SB + tag: VP_IP003_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S005_I000 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_rs1\nisacov.rv32i_sb_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S005_I001 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_imms_value\nisacov.rv32i_sb_cg.cp_rs1_toggle\n\ + isacov.rv32i_sb_cg.cp_rs2_toggle\nisacov.rv32i_sb_cg.cp_imms_toggle" + comments: '' +- 006_SH: !Subfeature + name: 006_SH + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S006_I000 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_rs1\nisacov.rv32i_sh_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S006_I001 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_imms_value\nisacov.rv32i_sh_cg.cp_rs1_toggle\n\ + isacov.rv32i_sh_cg.cp_rs2_toggle\nisacov.rv32i_sh_cg.cp_imms_toggle\nisacov.rv32i_sh_cg.cp_aligned" + comments: '' +- 007_SW: !Subfeature + name: 007_SW + tag: VP_IP003_P007 + next_elt_id: 2 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S007_I000 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_rs1\nisacov.rv32i_sw_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S007_I001 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_imms_value\nisacov.rv32i_sw_cg.cp_rs1_toggle\n\ + isacov.rv32i_sw_cg.cp_rs2_toggle\nisacov.rv32i_sw_cg.cp_imms_toggle\nisacov.rv32i_sw_cg.cp_aligned" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck deleted file mode 100644 index bd77b2b90..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32I Memory Ordering Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F004_S000_I000 -p34 -sVdescription -p35 -VFence operation executed\u000aImplementation is microarchitecture specific -p36 -sVpurpose -p37 -VISA\u000aChapter 2.7 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_fence.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml new file mode 100644 index 000000000..01a61498b --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -0,0 +1,33 @@ +!Feature +next_elt_id: 1 +name: RV32I Memory Ordering Instructions +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_FENCE: !Subfeature + name: 000_FENCE + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F004_S000_I000 + description: "Fence operation executed\nImplementation is microarchitecture\ + \ specific" + reqt_doc: "ISA\nChapter 2.7" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_fence.cp_fixed + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck deleted file mode 100644 index f17fd3ee4..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck +++ /dev/null @@ -1,284 +0,0 @@ -(VRV32I Environment Call and Breakpoints -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ECALL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F005_S000_I000 -p34 -sVdescription -p35 -VSoftware exception vector entered -p36 -sVpurpose -p37 -VISA\u000aChapter 2.8 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_ecall.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F005_S000_I001 -p63 -sg35 -VReturn control to a debugger -p64 -sg37 -VISA\u000aChapter 2.8 -p65 -sg39 -VInstruction executed -p66 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -asVrfu_list_1 -p73 -(lp74 -sg53 -(lp75 -sg13 -(dp76 -sbtp77 -a(V001_EBREAK -p78 -g1 -(g18 -g3 -Ntp79 -Rp80 -(dp81 -g22 -I1 -sg8 -g78 -sg23 -VVP_IP005_P001 -p82 -sg25 -(dp83 -sg12 -I1 -sg15 -(lp84 -(V000 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V000 -p89 -sg23 -VVP_ISA_F005_S001_I000 -p90 -sg35 -VReturn control to a debugger -p91 -sg37 -VISA\u000aChapter 2.8 -p92 -sg39 -VInstruction executed -p93 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p94 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp95 -sg15 -(lp96 -sg53 -(lp97 -sg13 -(dp98 -Vlock_status -p99 -I0 -ssbtp100 -asg73 -(lp101 -sg53 -(lp102 -sg13 -(dp103 -sbtp104 -asVrfu_list_0 -p105 -(lp106 -sg73 -(lp107 -sVvptool_gitrev -p108 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p109 -sVio_fmt_gitrev -p110 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p111 -sVconfig_gitrev -p112 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p113 -sVymlcfg_gitrev -p114 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p115 -sbtp116 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml new file mode 100644 index 000000000..85fd2a35c --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -0,0 +1,70 @@ +!Feature +next_elt_id: 2 +name: RV32I Environment Call and Breakpoints +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_ECALL: !Subfeature + name: 000_ECALL + tag: VP_IP005_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F005_S000_I000 + description: Software exception vector entered + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ecall.cp_fixed + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F005_S000_I001 + description: Return control to a debugger + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +- 001_EBREAK: !Subfeature + name: 001_EBREAK + tag: VP_IP005_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F005_S001_I000 + description: Return control to a debugger + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck deleted file mode 100644 index 540f7f495..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck +++ /dev/null @@ -1,780 +0,0 @@ -(VRV32M Multiplication Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I7 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_MUL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP000_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F000_S000_I000 -p34 -sVdescription -p35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.1 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_mul_cg.cp_rs1\u000aisacov.rv32m_mul_cg.cp_rs2\u000aisacov.rv32m_mul_cg.cp_rd\u000aisacov.rv32m_mul_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mul_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F000_S000_I001 -p63 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_mul_cg.cp_rs1_value\u000aisacov.rv32m_mul_cg.cp_rs2_value\u000aisacov.rv32m_mul_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mul_cg.cp_rs1_toggle \u000aisacov.rv32m_mul_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F000_S000_I002 -p78 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p80 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_mul_cg.cp_rd_value\u000aisacov.rv32m_mul_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_MULH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP000_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F000_S001_I000 -p105 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p106 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p108 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1\u000aisacov.rv32m_mulh_cg.cp_rs2\u000aisacov.rv32m_mulh_cg.cp_rd\u000aisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulh_cg.cp_rd_rs2_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F000_S001_I001 -p120 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p122 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p123 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1_value\u000aisacov.rv32m_mulh_cg.cp_rs2_value\u000aisacov.rv32m_mulh_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulh_cg.cp_rs1_toggle \u000aisacov.rv32m_mulh_cg.cp_rs2_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F000_S001_I002 -p135 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32m_mulh_cg.cp_rd_value\u000aisacov.rv32m_mulh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_MULHU -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP000_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F000_S002_I000 -p161 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p162 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p164 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1\u000aisacov.rv32m_mulhu_cg.cp_rs2\u000aisacov.rv32m_mulhu_cg.cp_rd\u000aisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F000_S002_I001 -p176 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p177 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p178 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1_value\u000aisacov.rv32m_mulhu_cg.cp_rs2_value\u000aisacov.rv32m_mulhu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhu_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F000_S002_I002 -p191 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p193 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32m_mulhu_cg.cp_rd_value\u000aisacov.rv32m_mulhu_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_MULHSU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP000_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F000_S003_I000 -p217 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p218 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p220 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1\u000aisacov.rv32m_mulhsu_cg.cp_rs2\u000aisacov.rv32m_mulhsu_cg.cp_rd\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F000_S003_I001 -p232 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p233 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p234 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1_value\u000aisacov.rv32m_mulhsu_cg.cp_rs2_value\u000aisacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhsu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhsu_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F000_S003_I002 -p247 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p248 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p250 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rd_value\u000aisacov.rv32m_mulhsu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -asVrfu_list_0 -p261 -(lp262 -sg88 -(lp263 -sVvptool_gitrev -p264 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p265 -sVio_fmt_gitrev -p266 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p267 -sVconfig_gitrev -p268 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p269 -sVymlcfg_gitrev -p270 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p271 -sbtp272 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml new file mode 100644 index 000000000..fa7e67190 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -0,0 +1,275 @@ +!Feature +next_elt_id: 7 +name: RV32M Multiplication Operations +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_MUL: !Subfeature + name: 000_MUL + tag: VP_IP000_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S000_I000 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1\nisacov.rv32m_mul_cg.cp_rs2\nisacov.rv32m_mul_cg.cp_rd\n\ + isacov.rv32m_mul_cg.cp_rd_rs1_hazard\nisacov.rv32m_mul_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S000_I001 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1_value\nisacov.rv32m_mul_cg.cp_rs2_value\n\ + isacov.rv32m_mul_cg.cross_rs1_rs2_value\nisacov.rv32m_mul_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mul_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S000_I002 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rd_value\nisacov.rv32m_mul_cg.cp_rd_toggle" + comments: '' +- 001_MULH: !Subfeature + name: 001_MULH + tag: VP_IP000_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S001_I000 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1\nisacov.rv32m_mulh_cg.cp_rs2\n\ + isacov.rv32m_mulh_cg.cp_rd\nisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulh_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S001_I001 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1_value\nisacov.rv32m_mulh_cg.cp_rs2_value\n\ + isacov.rv32m_mulh_cg.cross_rs1_rs2_value\nisacov.rv32m_mulh_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulh_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S001_I002 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rd_value\nisacov.rv32m_mulh_cg.cp_rd_toggle" + comments: '' +- 002_MULHU: !Subfeature + name: 002_MULHU + tag: VP_IP000_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S002_I000 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1\nisacov.rv32m_mulhu_cg.cp_rs2\n\ + isacov.rv32m_mulhu_cg.cp_rd\nisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S002_I001 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1_value\nisacov.rv32m_mulhu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S002_I002 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rd_value\nisacov.rv32m_mulhu_cg.cp_rd_toggle" + comments: '' +- 003_MULHSU: !Subfeature + name: 003_MULHSU + tag: VP_IP000_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S003_I000 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1\nisacov.rv32m_mulhsu_cg.cp_rs2\n\ + isacov.rv32m_mulhsu_cg.cp_rd\nisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\n\ + isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S003_I001 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1_value\nisacov.rv32m_mulhsu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhsu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhsu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S003_I002 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rd_value\nisacov.rv32m_mulhsu_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck deleted file mode 100644 index 057f15b89..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck +++ /dev/null @@ -1,976 +0,0 @@ -(VRV32M Division Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_DIV -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_div_cg.cp_rs1\u000aisacov.rv32m_div_cg.cp_rs2\u000aisacov.rv32m_div_cg.cp_rd\u000aisacov.rv32m_div_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_div_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F007_S000_I001 -p63 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F007_S000_I002 -p78 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -a(V003 -p88 -g1 -(g29 -g3 -Ntp89 -Rp90 -(dp91 -g8 -V003 -p92 -sg23 -VVP_ISA_F007_S000_I003 -p93 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p94 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p95 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = -2^31).\u000aExercise division by zero (returns -1 ; all bits set) -p96 -sg41 -Visacov.rv32m_div_results_cg.cp_div_special_results\u000aisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow -p97 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp98 -sg15 -(lp99 -sg53 -(lp100 -sg13 -(dp101 -g56 -I0 -ssbtp102 -asVrfu_list_1 -p103 -(lp104 -sg53 -(lp105 -sg13 -(dp106 -sbtp107 -a(V001_REM -p108 -g1 -(g18 -g3 -Ntp109 -Rp110 -(dp111 -g22 -I4 -sg8 -g108 -sg23 -VVP_IP007_P001 -p112 -sg25 -(dp113 -sg12 -I1 -sg15 -(lp114 -(V000 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V000 -p119 -sg23 -VVP_ISA_F007_S001_I000 -p120 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p122 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p123 -sg41 -Visacov.rv32m_rem_cg.cp_rs1\u000aisacov.rv32m_rem_cg.cp_rs2\u000aisacov.rv32m_rem_cg.cp_rd\u000aisacov.rv32m_rem_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_rem_cg.cp_rd_rs2_hazard -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V001 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V001 -p134 -sg23 -VVP_ISA_F007_S001_I001 -p135 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p137 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p138 -sg41 -Visacov.rv32m_rem_cg.cp_rs1_value\u000aisacov.rv32m_rem_cg.cp_rs2_value\u000aisacov.rv32m_rem_cg.cross_rs1_rs2_value\u000aisacov.rv32m_rem_cg.cp_rs1_toggle \u000aisacov.rv32m_rem_cg.cp_rs2_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -a(V002 -p145 -g1 -(g29 -g3 -Ntp146 -Rp147 -(dp148 -g8 -V002 -p149 -sg23 -VVP_ISA_F007_S001_I002 -p150 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p151 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p152 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p153 -sg41 -Visacov.rv32m_rem_cg.cp_rd_value\u000aisacov.rv32m_rem_cg.cp_rd_toggle -p154 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp155 -sg15 -(lp156 -sg53 -(lp157 -sg13 -(dp158 -g56 -I0 -ssbtp159 -a(V003 -p160 -g1 -(g29 -g3 -Ntp161 -Rp162 -(dp163 -g8 -V003 -p164 -sg23 -VVP_ISA_F007_S001_I003 -p165 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p166 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p167 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = 0).\u000aExercise division by zero (returns rs1) -p168 -sg41 -Visacov.rv32m_rem_results_cg.cp_div_zero\u000aisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow -p169 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp170 -sg15 -(lp171 -sg53 -(lp172 -sg13 -(dp173 -g56 -I0 -ssbtp174 -asg103 -(lp175 -sg53 -(lp176 -sg13 -(dp177 -sbtp178 -a(V002_DIVU -p179 -g1 -(g18 -g3 -Ntp180 -Rp181 -(dp182 -g22 -I4 -sg8 -g179 -sg23 -VVP_IP007_P002 -p183 -sg25 -(dp184 -sg12 -I2 -sg15 -(lp185 -(V000 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V000 -p190 -sg23 -VVP_ISA_F007_S002_I000 -p191 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p193 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p194 -sg41 -Visacov.rv32m_divu_cg.cp_rs1\u000aisacov.rv32m_divu_cg.cp_rs2\u000aisacov.rv32m_divu_cg.cp_rd\u000aisacov.rv32m_divu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_divu_cg.cp_rd_rs2_hazard -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -a(V001 -p201 -g1 -(g29 -g3 -Ntp202 -Rp203 -(dp204 -g8 -V001 -p205 -sg23 -VVP_ISA_F007_S002_I001 -p206 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p207 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p208 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p209 -sg41 -Visacov.rv32m_divu_cg.cp_rs1_value\u000aisacov.rv32m_divu_cg.cp_rs2_value\u000aisacov.rv32m_divu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_divu_cg.cp_rs1_toggle \u000aisacov.rv32m_divu_cg.cp_rs2_toggle -p210 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp211 -sg15 -(lp212 -sg53 -(lp213 -sg13 -(dp214 -g56 -I0 -ssbtp215 -a(V002 -p216 -g1 -(g29 -g3 -Ntp217 -Rp218 -(dp219 -g8 -V002 -p220 -sg23 -VVP_ISA_F007_S002_I002 -p221 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p222 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p223 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p224 -sg41 -Visacov.rv32m_divu_cg.cp_rd_value\u000aisacov.rv32m_divu_cg.cp_rd_toggle -p225 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp226 -sg15 -(lp227 -sg53 -(lp228 -sg13 -(dp229 -g56 -I0 -ssbtp230 -a(V003 -p231 -g1 -(g29 -g3 -Ntp232 -Rp233 -(dp234 -g8 -V003 -p235 -sg23 -VVP_ISA_F007_S002_I003 -p236 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p237 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p238 -sg39 -VExercise division by zero (returns 2^32-1 ; all bits set) -p239 -sg41 -Visacov.rv32m_divu_results_cg.cp_div_zero -p240 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp241 -sg15 -(lp242 -sg53 -(lp243 -sg13 -(dp244 -g56 -I0 -ssbtp245 -asg103 -(lp246 -sg53 -(lp247 -sg13 -(dp248 -sbtp249 -a(V003_REMU -p250 -g1 -(g18 -g3 -Ntp251 -Rp252 -(dp253 -g22 -I4 -sg8 -g250 -sg23 -VVP_IP007_P003 -p254 -sg25 -(dp255 -sg12 -I3 -sg15 -(lp256 -(V000 -p257 -g1 -(g29 -g3 -Ntp258 -Rp259 -(dp260 -g8 -V000 -p261 -sg23 -VVP_ISA_F007_S003_I000 -p262 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p263 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p264 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p265 -sg41 -Visacov.rv32m_remu_cg.cp_rs1\u000aisacov.rv32m_remu_cg.cp_rs2\u000aisacov.rv32m_remu_cg.cp_rd\u000aisacov.rv32m_remu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_remu_cg.cp_rd_rs2_hazard -p266 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp267 -sg15 -(lp268 -sg53 -(lp269 -sg13 -(dp270 -g56 -I0 -ssbtp271 -a(V001 -p272 -g1 -(g29 -g3 -Ntp273 -Rp274 -(dp275 -g8 -V001 -p276 -sg23 -VVP_ISA_F007_S003_I001 -p277 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p278 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p279 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p280 -sg41 -Visacov.rv32m_remu_cg.cp_rs1_value\u000aisacov.rv32m_remu_cg.cp_rs2_value\u000aisacov.rv32m_remu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_remu_cg.cp_rs1_toggle \u000aisacov.rv32m_remu_cg.cp_rs2_toggle -p281 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp282 -sg15 -(lp283 -sg53 -(lp284 -sg13 -(dp285 -g56 -I0 -ssbtp286 -a(V002 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V002 -p291 -sg23 -VVP_ISA_F007_S003_I002 -p292 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p293 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p294 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p295 -sg41 -Visacov.rv32m_remu_cg.cp_rd_value\u000aisacov.rv32m_remu_cg.cp_rd_toggle -p296 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp297 -sg15 -(lp298 -sg53 -(lp299 -sg13 -(dp300 -g56 -I0 -ssbtp301 -a(V003 -p302 -g1 -(g29 -g3 -Ntp303 -Rp304 -(dp305 -g8 -V003 -p306 -sg23 -VVP_ISA_F007_S003_I003 -p307 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p308 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p309 -sg39 -VExercise division by zero (returns rs1) -p310 -sg41 -Visacov.rv32m_remu_results_cg.cp_div_zero -p311 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp312 -sg15 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -g56 -I0 -ssbtp316 -asg103 -(lp317 -sg53 -(lp318 -sg13 -(dp319 -sbtp320 -asVrfu_list_0 -p321 -(lp322 -sg103 -(lp323 -sVvptool_gitrev -p324 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p325 -sVio_fmt_gitrev -p326 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p327 -sVconfig_gitrev -p328 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p329 -sVymlcfg_gitrev -p330 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p331 -sbtp332 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml new file mode 100644 index 000000000..bb6964c43 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -0,0 +1,350 @@ +!Feature +next_elt_id: 4 +name: RV32M Division Operations +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_DIV: !Subfeature + name: 000_DIV + tag: VP_IP007_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S000_I000 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\ + isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S000_I001 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S000_I002 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S000_I003 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 001_REM: !Subfeature + name: 001_REM + tag: VP_IP007_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S001_I000 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\ + isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S001_I001 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\ + isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_rem_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S001_I002 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S001_I003 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = 0).\nExercise division by zero (returns rs1)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 002_DIVU: !Subfeature + name: 002_DIVU + tag: VP_IP007_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S002_I000 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\ + isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S002_I001 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\ + isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_divu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S002_I002 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S002_I003 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero + comments: '' +- 003_REMU: !Subfeature + name: 003_REMU + tag: VP_IP007_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S003_I000 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\ + isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S003_I001 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\ + isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_remu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S003_I002 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S003_I003 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Exercise division by zero (returns rs1) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck deleted file mode 100644 index 2844a13db..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck +++ /dev/null @@ -1,520 +0,0 @@ -(VRV32A Load-Reserved/Store-Conditional Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LR.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F008_S000_I002 -p76 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p78 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F008_S000_I003 -p90 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exceptio -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_SC.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP008_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F008_S001_I000 -p116 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p118 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F008_S001_I001 -p130 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F008_S001_I002 -p144 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p146 -sg39 -VOutput result:\u000a\u000ard is either zero or non-zero to indicate success or failure, respectively -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F008_S001_I003 -p158 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -asVrfu_list_0 -p171 -(lp172 -sg99 -(lp173 -sVvptool_gitrev -p174 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p175 -sVio_fmt_gitrev -p176 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p177 -sVconfig_gitrev -p178 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p179 -sVymlcfg_gitrev -p180 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p181 -sbtp182 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml new file mode 100644 index 000000000..9677eec74 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 2 +name: RV32A Load-Reserved/Store-Conditional Instructions +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_LR.W: !Subfeature + name: 000_LR.W + tag: VP_IP008_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S000_I000 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S000_I001 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S000_I002 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F008_S000_I003 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exceptio" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_SC.W: !Subfeature + name: 001_SC.W + tag: VP_IP008_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S001_I000 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used\nAll possible register combinations where rs2\ + \ == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S001_I001 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S001_I002 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd is either zero or non-zero to indicate\ + \ success or failure, respectively" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F008_S001_I003 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck deleted file mode 100644 index 09577a56f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck +++ /dev/null @@ -1,2059 +0,0 @@ -(VRV32A Atomic Memory Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I9 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_AMOSWAP.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p78 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F009_S000_I003 -p90 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_AMOADD.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP009_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F009_S001_I000 -p116 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p118 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F009_S001_I001 -p130 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F009_S001_I002 -p144 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p146 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F009_S001_I003 -p158 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -a(V002_AMOAND.W -p171 -g1 -(g18 -g3 -Ntp172 -Rp173 -(dp174 -g22 -I4 -sg8 -g171 -sg23 -VVP_IP009_P002 -p175 -sg25 -(dp176 -sg12 -I2 -sg15 -(lp177 -(V000 -p178 -g1 -(g29 -g3 -Ntp179 -Rp180 -(dp181 -g8 -V000 -p182 -sg23 -VVP_ISA_F009_S002_I000 -p183 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p184 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p185 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p186 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp187 -sg15 -(lp188 -sg52 -(lp189 -sg13 -(dp190 -g55 -I0 -ssbtp191 -a(V001 -p192 -g1 -(g29 -g3 -Ntp193 -Rp194 -(dp195 -g8 -V001 -p196 -sg23 -VVP_ISA_F009_S002_I001 -p197 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p198 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p199 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p200 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp201 -sg15 -(lp202 -sg52 -(lp203 -sg13 -(dp204 -g55 -I0 -ssbtp205 -a(V002 -p206 -g1 -(g29 -g3 -Ntp207 -Rp208 -(dp209 -g8 -V002 -p210 -sg23 -VVP_ISA_F009_S002_I002 -p211 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p212 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p213 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p214 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp215 -sg15 -(lp216 -sg52 -(lp217 -sg13 -(dp218 -g55 -I0 -ssbtp219 -a(V003 -p220 -g1 -(g29 -g3 -Ntp221 -Rp222 -(dp223 -g8 -V003 -p224 -sg23 -VVP_ISA_F009_S002_I003 -p225 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p226 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p227 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p228 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp229 -sg15 -(lp230 -sg52 -(lp231 -sg13 -(dp232 -g55 -I0 -ssbtp233 -asg99 -(lp234 -sg52 -(lp235 -sg13 -(dp236 -sbtp237 -a(V003_AMOOR.W -p238 -g1 -(g18 -g3 -Ntp239 -Rp240 -(dp241 -g22 -I4 -sg8 -g238 -sg23 -VVP_IP009_P003 -p242 -sg25 -(dp243 -sg12 -I3 -sg15 -(lp244 -(V000 -p245 -g1 -(g29 -g3 -Ntp246 -Rp247 -(dp248 -g8 -V000 -p249 -sg23 -VVP_ISA_F009_S003_I000 -p250 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p251 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p252 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p253 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp254 -sg15 -(lp255 -sg52 -(lp256 -sg13 -(dp257 -g55 -I0 -ssbtp258 -a(V001 -p259 -g1 -(g29 -g3 -Ntp260 -Rp261 -(dp262 -g8 -V001 -p263 -sg23 -VVP_ISA_F009_S003_I001 -p264 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p265 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p266 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p267 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp268 -sg15 -(lp269 -sg52 -(lp270 -sg13 -(dp271 -g55 -I0 -ssbtp272 -a(V002 -p273 -g1 -(g29 -g3 -Ntp274 -Rp275 -(dp276 -g8 -V002 -p277 -sg23 -VVP_ISA_F009_S003_I002 -p278 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p279 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p280 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p281 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp282 -sg15 -(lp283 -sg52 -(lp284 -sg13 -(dp285 -g55 -I0 -ssbtp286 -a(V003 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V003 -p291 -sg23 -VVP_ISA_F009_S003_I003 -p292 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p293 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p294 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p295 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp296 -sg15 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -g55 -I0 -ssbtp300 -asg99 -(lp301 -sg52 -(lp302 -sg13 -(dp303 -sbtp304 -a(V004_AMOXOR.W -p305 -g1 -(g18 -g3 -Ntp306 -Rp307 -(dp308 -g22 -I4 -sg8 -g305 -sg23 -VVP_IP009_P004 -p309 -sg25 -(dp310 -sg12 -I4 -sg15 -(lp311 -(V000 -p312 -g1 -(g29 -g3 -Ntp313 -Rp314 -(dp315 -g8 -V000 -p316 -sg23 -VVP_ISA_F009_S004_I000 -p317 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p318 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p319 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p320 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp321 -sg15 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -g55 -I0 -ssbtp325 -a(V001 -p326 -g1 -(g29 -g3 -Ntp327 -Rp328 -(dp329 -g8 -V001 -p330 -sg23 -VVP_ISA_F009_S004_I001 -p331 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p332 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p333 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p334 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp335 -sg15 -(lp336 -sg52 -(lp337 -sg13 -(dp338 -g55 -I0 -ssbtp339 -a(V002 -p340 -g1 -(g29 -g3 -Ntp341 -Rp342 -(dp343 -g8 -V002 -p344 -sg23 -VVP_ISA_F009_S004_I002 -p345 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p346 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p347 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p348 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp349 -sg15 -(lp350 -sg52 -(lp351 -sg13 -(dp352 -g55 -I0 -ssbtp353 -a(V003 -p354 -g1 -(g29 -g3 -Ntp355 -Rp356 -(dp357 -g8 -V003 -p358 -sg23 -VVP_ISA_F009_S004_I003 -p359 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p360 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p361 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p362 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp363 -sg15 -(lp364 -sg52 -(lp365 -sg13 -(dp366 -g55 -I0 -ssbtp367 -asg99 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -sbtp371 -a(V005_AMOMAX.W -p372 -g1 -(g18 -g3 -Ntp373 -Rp374 -(dp375 -g22 -I4 -sg8 -g372 -sg23 -VVP_IP009_P005 -p376 -sg25 -(dp377 -sg12 -I5 -sg15 -(lp378 -(V000 -p379 -g1 -(g29 -g3 -Ntp380 -Rp381 -(dp382 -g8 -V000 -p383 -sg23 -VVP_ISA_F009_S005_I000 -p384 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p385 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p386 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p387 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp388 -sg15 -(lp389 -sg52 -(lp390 -sg13 -(dp391 -g55 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F009_S005_I001 -p398 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p399 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p400 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p401 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp402 -sg15 -(lp403 -sg52 -(lp404 -sg13 -(dp405 -g55 -I0 -ssbtp406 -a(V002 -p407 -g1 -(g29 -g3 -Ntp408 -Rp409 -(dp410 -g8 -g407 -sg23 -VVP_ISA_F009_S005_I002 -p411 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p412 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p413 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p414 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp415 -sg15 -(lp416 -sg52 -(lp417 -sg13 -(dp418 -g55 -I0 -ssbtp419 -a(V003 -p420 -g1 -(g29 -g3 -Ntp421 -Rp422 -(dp423 -g8 -V003 -p424 -sg23 -VVP_ISA_F009_S005_I003 -p425 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p426 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p427 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p428 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp429 -sg15 -(lp430 -sg52 -(lp431 -sg13 -(dp432 -g55 -I0 -ssbtp433 -asg99 -(lp434 -sg52 -(lp435 -sg13 -(dp436 -sbtp437 -a(V006_AMOMAXU.W -p438 -g1 -(g18 -g3 -Ntp439 -Rp440 -(dp441 -g22 -I4 -sg8 -g438 -sg23 -VVP_IP009_P006 -p442 -sg25 -(dp443 -sg12 -I6 -sg15 -(lp444 -(V000 -p445 -g1 -(g29 -g3 -Ntp446 -Rp447 -(dp448 -g8 -V000 -p449 -sg23 -VVP_ISA_F009_S006_I000 -p450 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p451 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p452 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p453 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp454 -sg15 -(lp455 -sg52 -(lp456 -sg13 -(dp457 -g55 -I0 -ssbtp458 -a(V001 -p459 -g1 -(g29 -g3 -Ntp460 -Rp461 -(dp462 -g8 -V001 -p463 -sg23 -VVP_ISA_F009_S006_I001 -p464 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p465 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p466 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p467 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp468 -sg15 -(lp469 -sg52 -(lp470 -sg13 -(dp471 -g55 -I0 -ssbtp472 -a(V002 -p473 -g1 -(g29 -g3 -Ntp474 -Rp475 -(dp476 -g8 -V002 -p477 -sg23 -VVP_ISA_F009_S006_I002 -p478 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p479 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p480 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p481 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp482 -sg15 -(lp483 -sg52 -(lp484 -sg13 -(dp485 -g55 -I0 -ssbtp486 -a(V003 -p487 -g1 -(g29 -g3 -Ntp488 -Rp489 -(dp490 -g8 -V003 -p491 -sg23 -VVP_ISA_F009_S006_I003 -p492 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p493 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p494 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p495 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp496 -sg15 -(lp497 -sg52 -(lp498 -sg13 -(dp499 -g55 -I0 -ssbtp500 -asg99 -(lp501 -sg52 -(lp502 -sg13 -(dp503 -sbtp504 -a(V007_AMOMIN.W -p505 -g1 -(g18 -g3 -Ntp506 -Rp507 -(dp508 -g22 -I4 -sg8 -g505 -sg23 -VVP_IP009_P007 -p509 -sg25 -(dp510 -sg12 -I7 -sg15 -(lp511 -(V000 -p512 -g1 -(g29 -g3 -Ntp513 -Rp514 -(dp515 -g8 -V000 -p516 -sg23 -VVP_ISA_F009_S007_I000 -p517 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p518 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p519 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p520 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp521 -sg15 -(lp522 -sg52 -(lp523 -sg13 -(dp524 -g55 -I0 -ssbtp525 -a(V001 -p526 -g1 -(g29 -g3 -Ntp527 -Rp528 -(dp529 -g8 -V001 -p530 -sg23 -VVP_ISA_F009_S007_I001 -p531 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p532 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p533 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p534 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp535 -sg15 -(lp536 -sg52 -(lp537 -sg13 -(dp538 -g55 -I0 -ssbtp539 -a(V002 -p540 -g1 -(g29 -g3 -Ntp541 -Rp542 -(dp543 -g8 -V002 -p544 -sg23 -VVP_ISA_F009_S007_I002 -p545 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p546 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p547 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p548 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp549 -sg15 -(lp550 -sg52 -(lp551 -sg13 -(dp552 -g55 -I0 -ssbtp553 -a(V003 -p554 -g1 -(g29 -g3 -Ntp555 -Rp556 -(dp557 -g8 -V003 -p558 -sg23 -VVP_ISA_F009_S007_I003 -p559 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p560 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p561 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p562 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp563 -sg15 -(lp564 -sg52 -(lp565 -sg13 -(dp566 -g55 -I0 -ssbtp567 -asg99 -(lp568 -sg52 -(lp569 -sg13 -(dp570 -sbtp571 -a(V008_AMOMINU.W -p572 -g1 -(g18 -g3 -Ntp573 -Rp574 -(dp575 -g22 -I4 -sg8 -g572 -sg23 -VVP_IP009_P008 -p576 -sg25 -(dp577 -sg12 -I8 -sg15 -(lp578 -(V000 -p579 -g1 -(g29 -g3 -Ntp580 -Rp581 -(dp582 -g8 -V000 -p583 -sg23 -VVP_ISA_F009_S008_I000 -p584 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p585 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p586 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p587 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp588 -sg15 -(lp589 -sg52 -(lp590 -sg13 -(dp591 -g55 -I0 -ssbtp592 -a(V001 -p593 -g1 -(g29 -g3 -Ntp594 -Rp595 -(dp596 -g8 -V001 -p597 -sg23 -VVP_ISA_F009_S008_I001 -p598 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p599 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p600 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p601 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp602 -sg15 -(lp603 -sg52 -(lp604 -sg13 -(dp605 -g55 -I0 -ssbtp606 -a(V002 -p607 -g1 -(g29 -g3 -Ntp608 -Rp609 -(dp610 -g8 -V002 -p611 -sg23 -VVP_ISA_F009_S008_I002 -p612 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p613 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p614 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p615 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp616 -sg15 -(lp617 -sg52 -(lp618 -sg13 -(dp619 -g55 -I0 -ssbtp620 -a(V003 -p621 -g1 -(g29 -g3 -Ntp622 -Rp623 -(dp624 -g8 -V003 -p625 -sg23 -VVP_ISA_F009_S008_I003 -p626 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p627 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p628 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p629 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp630 -sg15 -(lp631 -sg52 -(lp632 -sg13 -(dp633 -g55 -I0 -ssbtp634 -asg99 -(lp635 -sg52 -(lp636 -sg13 -(dp637 -sbtp638 -asVrfu_list_0 -p639 -(lp640 -sg99 -(lp641 -sVvptool_gitrev -p642 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p643 -sVio_fmt_gitrev -p644 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p645 -sVconfig_gitrev -p646 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p647 -sVymlcfg_gitrev -p648 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p649 -sbtp650 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml new file mode 100644 index 000000000..3c1a267e4 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -0,0 +1,788 @@ +!Feature +next_elt_id: 9 +name: RV32A Atomic Memory Operations +id: 9 +display_order: 9 +subfeatures: !!omap +- 000_AMOSWAP.W: !Subfeature + name: 000_AMOSWAP.W + tag: VP_IP009_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S000_I000 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S000_I001 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S000_I002 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S000_I003 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_AMOADD.W: !Subfeature + name: 001_AMOADD.W + tag: VP_IP009_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S001_I000 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S001_I001 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S001_I002 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S001_I003 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_AMOAND.W: !Subfeature + name: 002_AMOAND.W + tag: VP_IP009_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S002_I000 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S002_I001 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S002_I002 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S002_I003 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_AMOOR.W: !Subfeature + name: 003_AMOOR.W + tag: VP_IP009_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S003_I000 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S003_I001 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S003_I002 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S003_I003 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_AMOXOR.W: !Subfeature + name: 004_AMOXOR.W + tag: VP_IP009_P004 + next_elt_id: 4 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S004_I000 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S004_I001 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S004_I002 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S004_I003 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_AMOMAX.W: !Subfeature + name: 005_AMOMAX.W + tag: VP_IP009_P005 + next_elt_id: 4 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S005_I000 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S005_I001 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S005_I002 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S005_I003 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AMOMAXU.W: !Subfeature + name: 006_AMOMAXU.W + tag: VP_IP009_P006 + next_elt_id: 4 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S006_I000 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S006_I001 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S006_I002 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S006_I003 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AMOMIN.W: !Subfeature + name: 007_AMOMIN.W + tag: VP_IP009_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S007_I000 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S007_I001 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S007_I002 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S007_I003 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_AMOMINU.W: !Subfeature + name: 008_AMOMINU.W + tag: VP_IP009_P008 + next_elt_id: 4 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S008_I000 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S008_I001 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S008_I002 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S008_I003 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck deleted file mode 100644 index 997752667..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck +++ /dev/null @@ -1,2592 +0,0 @@ -(VRV32C Integer Computational Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I16 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.5 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll bits of imm[5:0] are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p64 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_C.LUI -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP008_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F008_S001_I000 -p88 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p90 -sg39 -VInput operands:\u000a\u000aAll bits of imm[17:12] are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F008_S001_I001 -p102 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p104 -sg39 -VOutput result:\u000a\u000aAll bits of rd[31:12] are toggled -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_C.ADDI -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I3 -sg8 -g115 -sg23 -VVP_IP008_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F008_S002_I000 -p127 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F008_S002_I001 -p141 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p143 -sg39 -VInput operands:\u000a\u000aAll inputs bits of rd before instruction execution are toggled\u000aAll bits of nzimm are toggled -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V002 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V002 -p154 -sg23 -VVP_ISA_F008_S002_I002 -p155 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p157 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -asg71 -(lp164 -sg52 -(lp165 -sg13 -(dp166 -sbtp167 -a(V003_C.ADDI16SP -p168 -g1 -(g18 -g3 -Ntp169 -Rp170 -(dp171 -g22 -I3 -sg8 -g168 -sg23 -VVP_IP008_P003 -p172 -sg25 -(dp173 -sg12 -I3 -sg15 -(lp174 -(V000 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V000 -p179 -sg23 -VVP_ISA_F008_S003_I000 -p180 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p182 -sg39 -VInput operands:\u000a\u000a+ve and -ve values of nzimm are used\u000aAll bits of nzimm[9:4] are toggled\u000aAll bits of x2 before instruction execution are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -a(V001 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V001 -p193 -sg23 -VVP_ISA_F008_S003_I001 -p194 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p196 -sg39 -VOutput result:\u000a\u000aAll bits of x2 are toggled -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -asg71 -(lp203 -sg52 -(lp204 -sg13 -(dp205 -sbtp206 -a(V004_C.ADDI4SPN -p207 -g1 -(g18 -g3 -Ntp208 -Rp209 -(dp210 -g22 -I3 -sg8 -g207 -sg23 -VVP_IP008_P004 -p211 -sg25 -(dp212 -sg12 -I4 -sg15 -(lp213 -(V000 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V000 -p218 -sg23 -VVP_ISA_F008_S004_I000 -p219 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p221 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V001 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V001 -p232 -sg23 -VVP_ISA_F008_S004_I001 -p233 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p235 -sg39 -VInput operands:\u000a\u000aAll bits of nzuimm[9:2] are toggled\u000aAll bits of x2 before instruction execution are toggled -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F008_S004_I002 -p247 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p248 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p249 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p250 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp251 -sg15 -(lp252 -sg52 -(lp253 -sg13 -(dp254 -g55 -I0 -ssbtp255 -asg71 -(lp256 -sg52 -(lp257 -sg13 -(dp258 -sbtp259 -a(V005_C.SLLI -p260 -g1 -(g18 -g3 -Ntp261 -Rp262 -(dp263 -g22 -I3 -sg8 -g260 -sg23 -VVP_IP008_P005 -p264 -sg25 -(dp265 -sg12 -I5 -sg15 -(lp266 -(V000 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V000 -p271 -sg23 -VVP_ISA_F008_S005_I000 -p272 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p274 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F008_S005_I001 -p286 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p288 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -a(V002 -p295 -g1 -(g29 -g3 -Ntp296 -Rp297 -(dp298 -g8 -V002 -p299 -sg23 -VVP_ISA_F008_S005_I002 -p300 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p301 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p302 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p303 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp304 -sg15 -(lp305 -sg52 -(lp306 -sg13 -(dp307 -g55 -I0 -ssbtp308 -asg71 -(lp309 -sg52 -(lp310 -sg13 -(dp311 -sbtp312 -a(V006_C.SRLI -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP008_P006 -p317 -sg25 -(dp318 -sg12 -I6 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F008_S006_I000 -p325 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p326 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p328 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp329 -sg15 -(lp330 -sg52 -(lp331 -sg13 -(dp332 -g55 -I0 -ssbtp333 -a(V001 -p334 -g1 -(g29 -g3 -Ntp335 -Rp336 -(dp337 -g8 -V001 -p338 -sg23 -VVP_ISA_F008_S006_I001 -p339 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p340 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p341 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p342 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp343 -sg15 -(lp344 -sg52 -(lp345 -sg13 -(dp346 -g55 -I0 -ssbtp347 -a(V002 -p348 -g1 -(g29 -g3 -Ntp349 -Rp350 -(dp351 -g8 -V002 -p352 -sg23 -VVP_ISA_F008_S006_I002 -p353 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p354 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p355 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p356 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp357 -sg15 -(lp358 -sg52 -(lp359 -sg13 -(dp360 -g55 -I0 -ssbtp361 -asg71 -(lp362 -sg52 -(lp363 -sg13 -(dp364 -sbtp365 -a(V007_C.SRAI -p366 -g1 -(g18 -g3 -Ntp367 -Rp368 -(dp369 -g22 -I3 -sg8 -g366 -sg23 -VVP_IP008_P007 -p370 -sg25 -(dp371 -sg12 -I7 -sg15 -(lp372 -(V000 -p373 -g1 -(g29 -g3 -Ntp374 -Rp375 -(dp376 -g8 -V000 -p377 -sg23 -VVP_ISA_F008_S007_I000 -p378 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p379 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p380 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p381 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp382 -sg15 -(lp383 -sg52 -(lp384 -sg13 -(dp385 -g55 -I0 -ssbtp386 -a(V001 -p387 -g1 -(g29 -g3 -Ntp388 -Rp389 -(dp390 -g8 -V001 -p391 -sg23 -VVP_ISA_F008_S007_I001 -p392 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p393 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p394 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of rd` are used\u000aAll bits of rd` before instruction execution are toggled -p395 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp396 -sg15 -(lp397 -sg52 -(lp398 -sg13 -(dp399 -g55 -I0 -ssbtp400 -a(V002 -p401 -g1 -(g29 -g3 -Ntp402 -Rp403 -(dp404 -g8 -V002 -p405 -sg23 -VVP_ISA_F008_S007_I002 -p406 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p407 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p408 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p409 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp410 -sg15 -(lp411 -sg52 -(lp412 -sg13 -(dp413 -g55 -I0 -ssbtp414 -asg71 -(lp415 -sg52 -(lp416 -sg13 -(dp417 -sbtp418 -a(V008_C.ANDI -p419 -g1 -(g18 -g3 -Ntp420 -Rp421 -(dp422 -g22 -I3 -sg8 -g419 -sg23 -VVP_IP008_P008 -p423 -sg25 -(dp424 -sg12 -I8 -sg15 -(lp425 -(V000 -p426 -g1 -(g29 -g3 -Ntp427 -Rp428 -(dp429 -g8 -V000 -p430 -sg23 -VVP_ISA_F008_S008_I000 -p431 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p432 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p433 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p434 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp435 -sg15 -(lp436 -sg52 -(lp437 -sg13 -(dp438 -g55 -I0 -ssbtp439 -a(V001 -p440 -g1 -(g29 -g3 -Ntp441 -Rp442 -(dp443 -g8 -V001 -p444 -sg23 -VVP_ISA_F008_S008_I001 -p445 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p446 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p447 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of imm are used\u000aAll bits of rd` before instruction execution are toggled -p448 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp449 -sg15 -(lp450 -sg52 -(lp451 -sg13 -(dp452 -g55 -I0 -ssbtp453 -a(V002 -p454 -g1 -(g29 -g3 -Ntp455 -Rp456 -(dp457 -g8 -V002 -p458 -sg23 -VVP_ISA_F008_S008_I002 -p459 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p460 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p461 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p462 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp463 -sg15 -(lp464 -sg52 -(lp465 -sg13 -(dp466 -g55 -I0 -ssbtp467 -asg71 -(lp468 -sg52 -(lp469 -sg13 -(dp470 -sbtp471 -a(V009_C.MV -p472 -g1 -(g18 -g3 -Ntp473 -Rp474 -(dp475 -g22 -I3 -sg8 -g472 -sg23 -VVP_IP008_P009 -p476 -sg25 -(dp477 -sg12 -I9 -sg15 -(lp478 -(V000 -p479 -g1 -(g29 -g3 -Ntp480 -Rp481 -(dp482 -g8 -V000 -p483 -sg23 -VVP_ISA_F008_S009_I000 -p484 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p485 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p486 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs2 == rd are used -p487 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp488 -sg15 -(lp489 -sg52 -(lp490 -sg13 -(dp491 -g55 -I0 -ssbtp492 -a(V001 -p493 -g1 -(g29 -g3 -Ntp494 -Rp495 -(dp496 -g8 -V001 -p497 -sg23 -VVP_ISA_F008_S009_I001 -p498 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p499 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p500 -sg39 -VInput operands:\u000a\u000aAll bits of rs2 are toggled -p501 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp502 -sg15 -(lp503 -sg52 -(lp504 -sg13 -(dp505 -g55 -I0 -ssbtp506 -a(V002 -p507 -g1 -(g29 -g3 -Ntp508 -Rp509 -(dp510 -g8 -V002 -p511 -sg23 -VVP_ISA_F008_S009_I002 -p512 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p513 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p514 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p515 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp516 -sg15 -(lp517 -sg52 -(lp518 -sg13 -(dp519 -g55 -I0 -ssbtp520 -asg71 -(lp521 -sg52 -(lp522 -sg13 -(dp523 -sbtp524 -a(V010_C.ADD -p525 -g1 -(g18 -g3 -Ntp526 -Rp527 -(dp528 -g22 -I3 -sg8 -g525 -sg23 -VVP_IP008_P010 -p529 -sg25 -(dp530 -sg12 -I10 -sg15 -(lp531 -(V000 -p532 -g1 -(g29 -g3 -Ntp533 -Rp534 -(dp535 -g8 -V000 -p536 -sg23 -VVP_ISA_F008_S010_I000 -p537 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p538 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p539 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p540 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp541 -sg15 -(lp542 -sg52 -(lp543 -sg13 -(dp544 -g55 -I0 -ssbtp545 -a(V001 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V001 -p550 -sg23 -VVP_ISA_F008_S010_I001 -p551 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p552 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p553 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2 are used\u000a+ve,-ve, and zero values of rdrs1 are used\u000aAll bits of rs2 are toggled\u000aAll bits of rd before instruction execution are toggled -p554 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp555 -sg15 -(lp556 -sg52 -(lp557 -sg13 -(dp558 -g55 -I0 -ssbtp559 -a(V002 -p560 -g1 -(g29 -g3 -Ntp561 -Rp562 -(dp563 -g8 -V002 -p564 -sg23 -VVP_ISA_F008_S010_I002 -p565 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p566 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p567 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled\u000a+ve,-ve and zero values of rd are used -p568 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp569 -sg15 -(lp570 -sg52 -(lp571 -sg13 -(dp572 -g55 -I0 -ssbtp573 -asg71 -(lp574 -sg52 -(lp575 -sg13 -(dp576 -sbtp577 -a(V011_C.AND -p578 -g1 -(g18 -g3 -Ntp579 -Rp580 -(dp581 -g22 -I3 -sg8 -g578 -sg23 -VVP_IP008_P011 -p582 -sg25 -(dp583 -sg12 -I11 -sg15 -(lp584 -(V000 -p585 -g1 -(g29 -g3 -Ntp586 -Rp587 -(dp588 -g8 -V000 -p589 -sg23 -VVP_ISA_F008_S011_I000 -p590 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p591 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p592 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p593 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp594 -sg15 -(lp595 -sg52 -(lp596 -sg13 -(dp597 -g55 -I0 -ssbtp598 -a(V001 -p599 -g1 -(g29 -g3 -Ntp600 -Rp601 -(dp602 -g8 -V001 -p603 -sg23 -VVP_ISA_F008_S011_I001 -p604 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p605 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p606 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p607 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp608 -sg15 -(lp609 -sg52 -(lp610 -sg13 -(dp611 -g55 -I0 -ssbtp612 -a(V002 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V002 -p617 -sg23 -VVP_ISA_F008_S011_I002 -p618 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p619 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p620 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p621 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp622 -sg15 -(lp623 -sg52 -(lp624 -sg13 -(dp625 -g55 -I0 -ssbtp626 -asg71 -(lp627 -sg52 -(lp628 -sg13 -(dp629 -sbtp630 -a(V012_C.OR -p631 -g1 -(g18 -g3 -Ntp632 -Rp633 -(dp634 -g22 -I3 -sg8 -g631 -sg23 -VVP_IP008_P012 -p635 -sg25 -(dp636 -sg12 -I12 -sg15 -(lp637 -(V000 -p638 -g1 -(g29 -g3 -Ntp639 -Rp640 -(dp641 -g8 -V000 -p642 -sg23 -VVP_ISA_F008_S012_I000 -p643 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p644 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p645 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p646 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp647 -sg15 -(lp648 -sg52 -(lp649 -sg13 -(dp650 -g55 -I0 -ssbtp651 -a(V001 -p652 -g1 -(g29 -g3 -Ntp653 -Rp654 -(dp655 -g8 -V001 -p656 -sg23 -VVP_ISA_F008_S012_I001 -p657 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p658 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p659 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p660 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp661 -sg15 -(lp662 -sg52 -(lp663 -sg13 -(dp664 -g55 -I0 -ssbtp665 -a(V002 -p666 -g1 -(g29 -g3 -Ntp667 -Rp668 -(dp669 -g8 -V002 -p670 -sg23 -VVP_ISA_F008_S012_I002 -p671 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p672 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p673 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p674 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp675 -sg15 -(lp676 -sg52 -(lp677 -sg13 -(dp678 -g55 -I0 -ssbtp679 -asg71 -(lp680 -sg52 -(lp681 -sg13 -(dp682 -sbtp683 -a(V013_C.XOR -p684 -g1 -(g18 -g3 -Ntp685 -Rp686 -(dp687 -g22 -I3 -sg8 -g684 -sg23 -VVP_IP008_P013 -p688 -sg25 -(dp689 -sg12 -I13 -sg15 -(lp690 -(V000 -p691 -g1 -(g29 -g3 -Ntp692 -Rp693 -(dp694 -g8 -V000 -p695 -sg23 -VVP_ISA_F008_S013_I000 -p696 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p697 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p698 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p699 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp700 -sg15 -(lp701 -sg52 -(lp702 -sg13 -(dp703 -g55 -I0 -ssbtp704 -a(V001 -p705 -g1 -(g29 -g3 -Ntp706 -Rp707 -(dp708 -g8 -V001 -p709 -sg23 -VVP_ISA_F008_S013_I001 -p710 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p711 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p712 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p713 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp714 -sg15 -(lp715 -sg52 -(lp716 -sg13 -(dp717 -g55 -I0 -ssbtp718 -a(V002 -p719 -g1 -(g29 -g3 -Ntp720 -Rp721 -(dp722 -g8 -V002 -p723 -sg23 -VVP_ISA_F008_S013_I002 -p724 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p725 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p726 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p727 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp728 -sg15 -(lp729 -sg52 -(lp730 -sg13 -(dp731 -g55 -I0 -ssbtp732 -asg71 -(lp733 -sg52 -(lp734 -sg13 -(dp735 -sbtp736 -a(V014_C.SUB -p737 -g1 -(g18 -g3 -Ntp738 -Rp739 -(dp740 -g22 -I3 -sg8 -g737 -sg23 -VVP_IP008_P014 -p741 -sg25 -(dp742 -sg12 -I14 -sg15 -(lp743 -(V000 -p744 -g1 -(g29 -g3 -Ntp745 -Rp746 -(dp747 -g8 -V000 -p748 -sg23 -VVP_ISA_F008_S014_I000 -p749 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p750 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p751 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p752 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp753 -sg15 -(lp754 -sg52 -(lp755 -sg13 -(dp756 -g55 -I0 -ssbtp757 -a(V001 -p758 -g1 -(g29 -g3 -Ntp759 -Rp760 -(dp761 -g8 -V001 -p762 -sg23 -VVP_ISA_F008_S014_I001 -p763 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p764 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p765 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2` are used\u000a+ve, -ve, and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p766 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp767 -sg15 -(lp768 -sg52 -(lp769 -sg13 -(dp770 -g55 -I0 -ssbtp771 -a(V002 -p772 -g1 -(g29 -g3 -Ntp773 -Rp774 -(dp775 -g8 -V002 -p776 -sg23 -VVP_ISA_F008_S014_I002 -p777 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p778 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p779 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p780 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp781 -sg15 -(lp782 -sg52 -(lp783 -sg13 -(dp784 -g55 -I0 -ssbtp785 -asg71 -(lp786 -sg52 -(lp787 -sg13 -(dp788 -sbtp789 -a(V015_C.EBREAK -p790 -g1 -(g18 -g3 -Ntp791 -Rp792 -(dp793 -g22 -I1 -sg8 -g790 -sg23 -VVP_IP008_P015 -p794 -sg25 -(dp795 -sg12 -I15 -sg15 -(lp796 -(V000 -p797 -g1 -(g29 -g3 -Ntp798 -Rp799 -(dp800 -g8 -V000 -p801 -sg23 -VVP_ISA_F008_S015_I000 -p802 -sg35 -Vc.ebreak\u000aRaiseException(Breakpoint)\u000aExpands to ebreak. -p803 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p804 -sg39 -VInstruction executed -p805 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp806 -sg15 -(lp807 -sg52 -(lp808 -sg13 -(dp809 -g55 -I0 -ssbtp810 -asg71 -(lp811 -sg52 -(lp812 -sg13 -(dp813 -sbtp814 -asVrfu_list_0 -p815 -(lp816 -sg71 -(lp817 -sVvptool_gitrev -p818 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p819 -sVio_fmt_gitrev -p820 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p821 -sVconfig_gitrev -p822 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p823 -sVymlcfg_gitrev -p824 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p825 -sbtp826 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml new file mode 100644 index 000000000..21eb1d64e --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -0,0 +1,868 @@ +!Feature +next_elt_id: 16 +name: RV32C Integer Computational Instructions +id: 10 +display_order: 10 +subfeatures: !!omap +- 000_C.LI: !Subfeature + name: 000_C.LI + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S000_I000 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of imm[5:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S000_I001 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.LUI: !Subfeature + name: 001_C.LUI + tag: VP_IP008_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S001_I000 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of imm[17:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S001_I001 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd[31:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.ADDI: !Subfeature + name: 002_C.ADDI + tag: VP_IP008_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S002_I000 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S002_I001 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll inputs bits of rd before instruction\ + \ execution are toggled\nAll bits of nzimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S002_I002 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.ADDI16SP: !Subfeature + name: 003_C.ADDI16SP + tag: VP_IP008_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S003_I000 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve and -ve values of nzimm are used\nAll\ + \ bits of nzimm[9:4] are toggled\nAll bits of x2 before instruction execution\ + \ are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S003_I001 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.ADDI4SPN: !Subfeature + name: 004_C.ADDI4SPN + tag: VP_IP008_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S004_I000 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S004_I001 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of nzuimm[9:2] are toggled\nAll\ + \ bits of x2 before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S004_I002 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.SLLI: !Subfeature + name: 005_C.SLLI + tag: VP_IP008_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S005_I000 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S005_I001 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S005_I002 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_C.SRLI: !Subfeature + name: 006_C.SRLI + tag: VP_IP008_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S006_I000 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S006_I001 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S006_I002 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_C.SRAI: !Subfeature + name: 007_C.SRAI + tag: VP_IP008_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S007_I000 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S007_I001 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of rd` are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S007_I002 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_C.ANDI: !Subfeature + name: 008_C.ANDI + tag: VP_IP008_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S008_I000 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S008_I001 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of imm are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S008_I002 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_C.MV: !Subfeature + name: 009_C.MV + tag: VP_IP008_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S009_I000 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used.\n\ + All possible register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S009_I001 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S009_I002 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 010_C.ADD: !Subfeature + name: 010_C.ADD + tag: VP_IP008_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S010_I000 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S010_I001 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2 are used\n\ + +ve,-ve, and zero values of rdrs1 are used\nAll bits of rs2 are toggled\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S010_I002 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled\n+ve,-ve and zero\ + \ values of rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 011_C.AND: !Subfeature + name: 011_C.AND + tag: VP_IP008_P011 + next_elt_id: 3 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S011_I000 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S011_I001 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S011_I002 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 012_C.OR: !Subfeature + name: 012_C.OR + tag: VP_IP008_P012 + next_elt_id: 3 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S012_I000 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S012_I001 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S012_I002 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 013_C.XOR: !Subfeature + name: 013_C.XOR + tag: VP_IP008_P013 + next_elt_id: 3 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S013_I000 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S013_I001 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S013_I002 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 014_C.SUB: !Subfeature + name: 014_C.SUB + tag: VP_IP008_P014 + next_elt_id: 3 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S014_I000 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S014_I001 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2` are used\n\ + +ve, -ve, and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S014_I002 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 015_C.EBREAK: !Subfeature + name: 015_C.EBREAK + tag: VP_IP008_P015 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S015_I000 + description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck deleted file mode 100644 index e8ad3e411..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck +++ /dev/null @@ -1,920 +0,0 @@ -(VRV32C Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I11 -sVwid_order -p12 -I11 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.J -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP010_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F010_S000_I000 -p34 -sVdescription -p35 -Vc.j imm[11:1]\u000apc += sext(imm)\u000apc is calculated using signed arithmetic\u000aExpands to jal x0, imm[11:1]. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_C.JAL -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I2 -sg8 -g62 -sg23 -VVP_IP010_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_ISA_F010_S001_I000 -p74 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p75 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p76 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p77 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -a(V001 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V001 -p87 -sg23 -VVP_ISA_F010_S001_I001 -p88 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p90 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -asg57 -(lp97 -sg52 -(lp98 -sg13 -(dp99 -sbtp100 -a(V002_C.JR -p101 -g1 -(g18 -g3 -Ntp102 -Rp103 -(dp104 -g22 -I2 -sg8 -g101 -sg23 -VVP_IP010_P002 -p105 -sg25 -(dp106 -sg12 -I2 -sg15 -(lp107 -(V000 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V000 -p112 -sg23 -VVP_ISA_F010_S002_I000 -p113 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p114 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p115 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p116 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -a(V001 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V001 -p126 -sg23 -VVP_ISA_F010_S002_I001 -p127 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p129 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -asg57 -(lp136 -sg52 -(lp137 -sg13 -(dp138 -sbtp139 -a(V003_C.JALR -p140 -g1 -(g18 -g3 -Ntp141 -Rp142 -(dp143 -g22 -I3 -sg8 -g140 -sg23 -VVP_IP010_P003 -p144 -sg25 -(dp145 -sg12 -I3 -sg15 -(lp146 -(V000 -p147 -g1 -(g29 -g3 -Ntp148 -Rp149 -(dp150 -g8 -V000 -p151 -sg23 -VVP_ISA_F010_S003_I000 -p152 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p153 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p154 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p155 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp156 -sg15 -(lp157 -sg52 -(lp158 -sg13 -(dp159 -g55 -I0 -ssbtp160 -a(V001 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V001 -p165 -sg23 -VVP_ISA_F010_S003_I001 -p166 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p167 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p168 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V002 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V002 -p179 -sg23 -VVP_ISA_F010_S003_I002 -p180 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p182 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg57 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_C.BEQZ -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I3 -sg8 -g193 -sg23 -VVP_IP010_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F010_S004_I000 -p205 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p206 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F010_S004_I001 -p219 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p221 -sg39 -VInput operands:\u000a\u000aAll bits of rs1` are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V002 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V002 -p232 -sg23 -VVP_ISA_F010_S004_I002 -p233 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p235 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -asg57 -(lp242 -sg52 -(lp243 -sg13 -(dp244 -sbtp245 -a(V005_C.BNEZ -p246 -g1 -(g18 -g3 -Ntp247 -Rp248 -(dp249 -g22 -I3 -sg8 -g246 -sg23 -VVP_IP010_P005 -p250 -sg25 -(dp251 -sg12 -I5 -sg15 -(lp252 -(V000 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V000 -p257 -sg23 -VVP_ISA_F010_S005_I000 -p258 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p259 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p260 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -a(V001 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V001 -p271 -sg23 -VVP_ISA_F010_S005_I001 -p272 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p274 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V002 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V002 -p285 -sg23 -VVP_ISA_F010_S005_I002 -p286 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p288 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -asg57 -(lp295 -sg52 -(lp296 -sg13 -(dp297 -sbtp298 -asVrfu_list_0 -p299 -(lp300 -sg57 -(lp301 -sVvptool_gitrev -p302 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p303 -sVio_fmt_gitrev -p304 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p305 -sVconfig_gitrev -p306 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p307 -sVymlcfg_gitrev -p308 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p309 -sbtp310 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml new file mode 100644 index 000000000..c95e04332 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -0,0 +1,286 @@ +!Feature +next_elt_id: 6 +name: RV32C Control Transfer Instructions +id: 11 +display_order: 11 +subfeatures: !!omap +- 000_C.J: !Subfeature + name: 000_C.J + tag: VP_IP010_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S000_I000 + description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ + \ arithmetic\nExpands to jal x0, imm[11:1]." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.JAL: !Subfeature + name: 001_C.JAL + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S001_I000 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S001_I001 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.JR: !Subfeature + name: 002_C.JR + tag: VP_IP010_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S002_I000 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S002_I001 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.JALR: !Subfeature + name: 003_C.JALR + tag: VP_IP010_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S003_I000 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S003_I001 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S003_I002 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.BEQZ: !Subfeature + name: 004_C.BEQZ + tag: VP_IP010_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S004_I000 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S004_I001 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S004_I002 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.BNEZ: !Subfeature + name: 005_C.BNEZ + tag: VP_IP010_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S005_I000 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S005_I001 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S005_I002 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck deleted file mode 100644 index 73c3f301f..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck +++ /dev/null @@ -1,672 +0,0 @@ -(VRV32C Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I12 -sVwid_order -p12 -I12 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LWSP -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.3 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p64 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p77 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p78 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V001_C.SWSP -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I2 -sg8 -g90 -sg23 -VVP_IP009_P001 -p94 -sg25 -(dp95 -sg12 -I1 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_ISA_F009_S001_I000 -p102 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p104 -sg39 -VRegister operands:\u000a\u000aAll possible rs2 registers are used. -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V001 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V001 -p115 -sg23 -VVP_ISA_F009_S001_I001 -p116 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p117 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p118 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg85 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -a(V002_C.LW -p129 -g1 -(g18 -g3 -Ntp130 -Rp131 -(dp132 -g22 -I3 -sg8 -g129 -sg23 -VVP_IP009_P002 -p133 -sg25 -(dp134 -sg12 -I2 -sg15 -(lp135 -(V000 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V000 -p140 -sg23 -VVP_ISA_F009_S002_I000 -p141 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p143 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V001 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V001 -p154 -sg23 -VVP_ISA_F009_S002_I001 -p155 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p157 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -a(V002 -p164 -g1 -(g29 -g3 -Ntp165 -Rp166 -(dp167 -g8 -V002 -p168 -sg23 -VVP_ISA_F009_S002_I002 -p169 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p170 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p171 -sg39 -VOutput result:\u000a\u000ard` value is non-zero and zero\u000aAll bits of rd are toggled -p172 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp173 -sg15 -(lp174 -sg52 -(lp175 -sg13 -(dp176 -g55 -I0 -ssbtp177 -asg85 -(lp178 -sg52 -(lp179 -sg13 -(dp180 -sbtp181 -a(V003_C.SW -p182 -g1 -(g18 -g3 -Ntp183 -Rp184 -(dp185 -g22 -I2 -sg8 -g182 -sg23 -VVP_IP009_P003 -p186 -sg25 -(dp187 -sg12 -I3 -sg15 -(lp188 -(V000 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V000 -p193 -sg23 -VVP_ISA_F009_S003_I000 -p194 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p196 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -a(V001 -p203 -g1 -(g29 -g3 -Ntp204 -Rp205 -(dp206 -g8 -V001 -p207 -sg23 -VVP_ISA_F009_S003_I001 -p208 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p209 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p210 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled\u000aAll bits of rs2` are toggled -p211 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp212 -sg15 -(lp213 -sg52 -(lp214 -sg13 -(dp215 -g55 -I0 -ssbtp216 -asg85 -(lp217 -sg52 -(lp218 -sg13 -(dp219 -sbtp220 -asVrfu_list_0 -p221 -(lp222 -sg85 -(lp223 -sVvptool_gitrev -p224 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p225 -sVio_fmt_gitrev -p226 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p227 -sVconfig_gitrev -p228 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p229 -sVymlcfg_gitrev -p230 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p231 -sbtp232 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml new file mode 100644 index 000000000..7fe21ee0d --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -0,0 +1,218 @@ +!Feature +next_elt_id: 4 +name: RV32C Load and Store Instructions +id: 12 +display_order: 12 +subfeatures: !!omap +- 000_C.LWSP: !Subfeature + name: 000_C.LWSP + tag: VP_IP009_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S000_I000 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S000_I001 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S000_I002 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.SWSP: !Subfeature + name: 001_C.SWSP + tag: VP_IP009_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S001_I000 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S001_I001 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.LW: !Subfeature + name: 002_C.LW + tag: VP_IP009_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S002_I000 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S002_I001 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S002_I002 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd` value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.SW: !Subfeature + name: 003_C.SW + tag: VP_IP009_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S003_I000 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S003_I001 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled\nAll bits of rs2` are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck deleted file mode 100644 index acac41764..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck +++ /dev/null @@ -1,824 +0,0 @@ -(VRV32Zicsr Control and Status Register (CSR) Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I13 -sVwid_order -p12 -I13 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_CSRRW -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p36 -sVpurpose -p37 -VISA Chapter 9 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F007_S000_I001 -p62 -sg35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p63 -sg37 -VISA Chapter 9 -p64 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_CSRRS -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP007_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F007_S001_I000 -p88 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p89 -sg37 -VISA Chapter 9 -p90 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F007_S001_I001 -p102 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p103 -sg37 -VISA Chapter 9 -p104 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_CSRRC -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I2 -sg8 -g115 -sg23 -VVP_IP007_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F007_S002_I000 -p127 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p128 -sg37 -VISA Chapter 9 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F007_S002_I001 -p141 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p142 -sg37 -VISA Chapter 9 -p143 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -asg71 -(lp150 -sg52 -(lp151 -sg13 -(dp152 -sbtp153 -a(V003_CSRRWI -p154 -g1 -(g18 -g3 -Ntp155 -Rp156 -(dp157 -g22 -I2 -sg8 -g154 -sg23 -VVP_IP007_P003 -p158 -sg25 -(dp159 -sg12 -I3 -sg15 -(lp160 -(V000 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V000 -p165 -sg23 -VVP_ISA_F007_S003_I000 -p166 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p167 -sg37 -VISA Chapter 9 -p168 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V001 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V001 -p179 -sg23 -VVP_ISA_F007_S003_I001 -p180 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p181 -sg37 -VISA Chapter 9 -p182 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg71 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_CSRRSI -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I2 -sg8 -g193 -sg23 -VVP_IP007_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F007_S004_I000 -p205 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p206 -sg37 -VISA Chapter 9 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F007_S004_I001 -p219 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p220 -sg37 -VISA Chapter 9 -p221 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -asg71 -(lp228 -sg52 -(lp229 -sg13 -(dp230 -sbtp231 -a(V005_CSRRCI -p232 -g1 -(g18 -g3 -Ntp233 -Rp234 -(dp235 -g22 -I2 -sg8 -g232 -sg23 -VVP_IP007_P005 -p236 -sg25 -(dp237 -sg12 -I5 -sg15 -(lp238 -(V000 -p239 -g1 -(g29 -g3 -Ntp240 -Rp241 -(dp242 -g8 -V000 -p243 -sg23 -VVP_ISA_F007_S005_I000 -p244 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p245 -sg37 -VISA Chapter 9 -p246 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p247 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp248 -sg15 -(lp249 -sg52 -(lp250 -sg13 -(dp251 -g55 -I0 -ssbtp252 -a(V001 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V001 -p257 -sg23 -VVP_ISA_F007_S005_I001 -p258 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p259 -sg37 -VISA Chapter 9 -p260 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -asg71 -(lp267 -sg52 -(lp268 -sg13 -(dp269 -sbtp270 -asVrfu_list_0 -p271 -(lp272 -sg71 -(lp273 -sVvptool_gitrev -p274 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p275 -sVio_fmt_gitrev -p276 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p277 -sVconfig_gitrev -p278 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p279 -sVymlcfg_gitrev -p280 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p281 -sbtp282 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml new file mode 100644 index 000000000..b13e60860 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -0,0 +1,263 @@ +!Feature +next_elt_id: 6 +name: RV32Zicsr Control and Status Register (CSR) Instructions +id: 13 +display_order: 13 +subfeatures: !!omap +- 000_CSRRW: !Subfeature + name: 000_CSRRW + tag: VP_IP007_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S000_I000 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S000_I001 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_CSRRS: !Subfeature + name: 001_CSRRS + tag: VP_IP007_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S001_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S001_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_CSRRC: !Subfeature + name: 002_CSRRC + tag: VP_IP007_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S002_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S002_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSRRWI: !Subfeature + name: 003_CSRRWI + tag: VP_IP007_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S003_I000 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S003_I001 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_CSRRSI: !Subfeature + name: 004_CSRRSI + tag: VP_IP007_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S004_I000 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S004_I001 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_CSRRCI: !Subfeature + name: 005_CSRRCI + tag: VP_IP007_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S005_I000 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S005_I001 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck deleted file mode 100644 index d3b9272ec..000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32Zifencei Instruction-Fetch Fence -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I14 -sVwid_order -p12 -I14 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE.I -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F006_S000_I000 -p34 -sVdescription -p35 -VFence.I instruction executed\u000aImplementation is core-specific -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 3 -p38 -sVverif_goals -p39 -VFence.I instruction is executed -p40 -sVcoverage_loc -p41 -Visacov.rv32zifencei_fence_i_cg -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml new file mode 100644 index 000000000..b12d713c9 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -0,0 +1,32 @@ +!Feature +next_elt_id: 1 +name: RV32Zifencei Instruction-Fetch Fence +id: 14 +display_order: 14 +subfeatures: !!omap +- 000_FENCE.I: !Subfeature + name: 000_FENCE.I + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F006_S000_I000 + description: "Fence.I instruction executed\nImplementation is core-specific" + reqt_doc: "Unprivileged ISA\nChapter 3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Fence.I instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32zifencei_fence_i_cg + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' From 33d8a6499706639d0f9cfffe1ccf683a545e34dc Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 17:59:30 +0100 Subject: [PATCH 036/183] DV plans: Update ISA_RV32 item tags: match feature order, remove duplicates. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml: Name tags after feature number used in DB file name. Use 'ISA_RV32' in tag names to match project name. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/runme.sh (PROJECT_NAME): USe more explicit printable name. (PROJECT_IDENT): Use same name as in directory naming to prevent future ambiguity with 64b ISA. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml | 66 ++++++++--------- cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml | 60 +++++++-------- cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml | 48 ++++++------ cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml | 42 +++++------ cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml | 2 +- cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml | 6 +- cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml | 24 +++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml | 32 ++++---- cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml | 16 ++-- cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml | 72 +++++++++--------- cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml | 86 +++++++++++----------- cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml | 28 +++---- cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml | 20 ++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml | 24 +++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml | 2 +- cva6/docs/VerifPlans/ISA_RV32/runme.sh | 4 +- 16 files changed, 266 insertions(+), 266 deletions(-) diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml index 70b22805d..4fa8fffdf 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S000_I000 + tag: VP_ISA_RV32_F000_S000_I000 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S000_I001 + tag: VP_ISA_RV32_F000_S000_I001 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -52,7 +52,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S000_I002 + tag: VP_ISA_RV32_F000_S000_I002 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -76,7 +76,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S001_I000 + tag: VP_ISA_RV32_F000_S001_I000 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -95,7 +95,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S001_I001 + tag: VP_ISA_RV32_F000_S001_I001 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -116,7 +116,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S001_I002 + tag: VP_ISA_RV32_F000_S001_I002 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -140,7 +140,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S002_I000 + tag: VP_ISA_RV32_F000_S002_I000 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -159,7 +159,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S002_I001 + tag: VP_ISA_RV32_F000_S002_I001 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -180,7 +180,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S002_I002 + tag: VP_ISA_RV32_F000_S002_I002 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -204,7 +204,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S003_I000 + tag: VP_ISA_RV32_F000_S003_I000 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -223,7 +223,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S003_I001 + tag: VP_ISA_RV32_F000_S003_I001 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -244,7 +244,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S003_I002 + tag: VP_ISA_RV32_F000_S003_I002 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -268,7 +268,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S004_I000 + tag: VP_ISA_RV32_F000_S004_I000 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -287,7 +287,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S004_I001 + tag: VP_ISA_RV32_F000_S004_I001 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -308,7 +308,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S004_I002 + tag: VP_ISA_RV32_F000_S004_I002 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -331,7 +331,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S005_I000 + tag: VP_ISA_RV32_F000_S005_I000 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -351,7 +351,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S005_I001 + tag: VP_ISA_RV32_F000_S005_I001 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -372,7 +372,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S005_I002 + tag: VP_ISA_RV32_F000_S005_I002 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -395,7 +395,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S006_I000 + tag: VP_ISA_RV32_F000_S006_I000 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -414,7 +414,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S006_I001 + tag: VP_ISA_RV32_F000_S006_I001 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -434,7 +434,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S006_I002 + tag: VP_ISA_RV32_F000_S006_I002 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -458,7 +458,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S007_I000 + tag: VP_ISA_RV32_F000_S007_I000 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -477,7 +477,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S007_I001 + tag: VP_ISA_RV32_F000_S007_I001 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -497,7 +497,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S007_I002 + tag: VP_ISA_RV32_F000_S007_I002 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -521,7 +521,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S008_I000 + tag: VP_ISA_RV32_F000_S008_I000 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ \ bit is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -540,7 +540,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S008_I001 + tag: VP_ISA_RV32_F000_S008_I001 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ \ bit is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -560,7 +560,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S008_I002 + tag: VP_ISA_RV32_F000_S008_I002 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -584,7 +584,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S009_I000 + tag: VP_ISA_RV32_F000_S009_I000 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -600,7 +600,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S009_I001 + tag: VP_ISA_RV32_F000_S009_I001 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -617,7 +617,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S009_I002 + tag: VP_ISA_RV32_F000_S009_I002 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -640,7 +640,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S010_I000 + tag: VP_ISA_RV32_F000_S010_I000 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" @@ -657,7 +657,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S010_I001 + tag: VP_ISA_RV32_F000_S010_I001 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" @@ -675,7 +675,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S010_I002 + tag: VP_ISA_RV32_F000_S010_I002 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml index 81184060b..3c9c81846 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S000_I000 + tag: VP_ISA_RV32_F001_S000_I000 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S000_I001 + tag: VP_ISA_RV32_F001_S000_I001 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S000_I002 + tag: VP_ISA_RV32_F001_S000_I002 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -78,7 +78,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S001_I000 + tag: VP_ISA_RV32_F001_S001_I000 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -98,7 +98,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S001_I001 + tag: VP_ISA_RV32_F001_S001_I001 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -118,7 +118,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S001_I002 + tag: VP_ISA_RV32_F001_S001_I002 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -141,7 +141,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S002_I000 + tag: VP_ISA_RV32_F001_S002_I000 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -164,7 +164,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S002_I001 + tag: VP_ISA_RV32_F001_S002_I001 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -185,7 +185,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S002_I002 + tag: VP_ISA_RV32_F001_S002_I002 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -209,7 +209,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S003_I000 + tag: VP_ISA_RV32_F001_S003_I000 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -230,7 +230,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S003_I001 + tag: VP_ISA_RV32_F001_S003_I001 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -251,7 +251,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S003_I002 + tag: VP_ISA_RV32_F001_S003_I002 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -275,7 +275,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S004_I000 + tag: VP_ISA_RV32_F001_S004_I000 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -296,7 +296,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S004_I001 + tag: VP_ISA_RV32_F001_S004_I001 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -317,7 +317,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S004_I002 + tag: VP_ISA_RV32_F001_S004_I002 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -341,7 +341,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S005_I000 + tag: VP_ISA_RV32_F001_S005_I000 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -362,7 +362,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S005_I001 + tag: VP_ISA_RV32_F001_S005_I001 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -383,7 +383,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S005_I002 + tag: VP_ISA_RV32_F001_S005_I002 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -406,7 +406,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S006_I000 + tag: VP_ISA_RV32_F001_S006_I000 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -427,7 +427,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S006_I001 + tag: VP_ISA_RV32_F001_S006_I001 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -448,7 +448,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S006_I002 + tag: VP_ISA_RV32_F001_S006_I002 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -471,7 +471,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S007_I000 + tag: VP_ISA_RV32_F001_S007_I000 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -492,7 +492,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S007_I001 + tag: VP_ISA_RV32_F001_S007_I001 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -512,7 +512,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S007_I002 + tag: VP_ISA_RV32_F001_S007_I002 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -537,7 +537,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S008_I000 + tag: VP_ISA_RV32_F001_S008_I000 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -558,7 +558,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S008_I001 + tag: VP_ISA_RV32_F001_S008_I001 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -578,7 +578,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S008_I002 + tag: VP_ISA_RV32_F001_S008_I002 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -602,7 +602,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S009_I000 + tag: VP_ISA_RV32_F001_S009_I000 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ \ is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -623,7 +623,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S009_I001 + tag: VP_ISA_RV32_F001_S009_I001 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ \ is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -643,7 +643,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S009_I002 + tag: VP_ISA_RV32_F001_S009_I002 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml index a6903df29..1e9626072 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S000_I000 + tag: VP_ISA_RV32_F002_S000_I000 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S000_I001 + tag: VP_ISA_RV32_F002_S000_I001 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -49,7 +49,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S000_I002 + tag: VP_ISA_RV32_F002_S000_I002 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -73,7 +73,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S001_I000 + tag: VP_ISA_RV32_F002_S001_I000 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -92,7 +92,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S001_I001 + tag: VP_ISA_RV32_F002_S001_I001 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -111,7 +111,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S001_I002 + tag: VP_ISA_RV32_F002_S001_I002 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -134,7 +134,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S002_I000 + tag: VP_ISA_RV32_F002_S002_I000 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -152,7 +152,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S002_I001 + tag: VP_ISA_RV32_F002_S002_I001 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -172,7 +172,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S002_I002 + tag: VP_ISA_RV32_F002_S002_I002 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -195,7 +195,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S003_I000 + tag: VP_ISA_RV32_F002_S003_I000 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -213,7 +213,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S003_I001 + tag: VP_ISA_RV32_F002_S003_I001 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -233,7 +233,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S003_I002 + tag: VP_ISA_RV32_F002_S003_I002 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -256,7 +256,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S004_I000 + tag: VP_ISA_RV32_F002_S004_I000 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -274,7 +274,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S004_I001 + tag: VP_ISA_RV32_F002_S004_I001 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -294,7 +294,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S004_I002 + tag: VP_ISA_RV32_F002_S004_I002 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -317,7 +317,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S005_I000 + tag: VP_ISA_RV32_F002_S005_I000 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -335,7 +335,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S005_I001 + tag: VP_ISA_RV32_F002_S005_I001 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -355,7 +355,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S005_I002 + tag: VP_ISA_RV32_F002_S005_I002 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -378,7 +378,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S006_I000 + tag: VP_ISA_RV32_F002_S006_I000 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -396,7 +396,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S006_I001 + tag: VP_ISA_RV32_F002_S006_I001 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -416,7 +416,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S006_I002 + tag: VP_ISA_RV32_F002_S006_I002 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -439,7 +439,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S007_I000 + tag: VP_ISA_RV32_F002_S007_I000 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -457,7 +457,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S007_I001 + tag: VP_ISA_RV32_F002_S007_I001 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -477,7 +477,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S007_I002 + tag: VP_ISA_RV32_F002_S007_I002 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml index cf67b09c1..0fdce09e6 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S000_I000 + tag: VP_ISA_RV32_F003_S000_I000 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S000_I001 + tag: VP_ISA_RV32_F003_S000_I001 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -51,7 +51,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S000_I002 + tag: VP_ISA_RV32_F003_S000_I002 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -75,7 +75,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S001_I000 + tag: VP_ISA_RV32_F003_S001_I000 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -94,7 +94,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S001_I001 + tag: VP_ISA_RV32_F003_S001_I001 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -115,7 +115,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S001_I002 + tag: VP_ISA_RV32_F003_S001_I002 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -139,7 +139,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S002_I000 + tag: VP_ISA_RV32_F003_S002_I000 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -158,7 +158,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S002_I001 + tag: VP_ISA_RV32_F003_S002_I001 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -179,7 +179,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S002_I002 + tag: VP_ISA_RV32_F003_S002_I002 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -203,7 +203,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S003_I000 + tag: VP_ISA_RV32_F003_S003_I000 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -222,7 +222,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S003_I001 + tag: VP_ISA_RV32_F003_S003_I001 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -242,7 +242,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S003_I002 + tag: VP_ISA_RV32_F003_S003_I002 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -266,7 +266,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S004_I000 + tag: VP_ISA_RV32_F003_S004_I000 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -285,7 +285,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S004_I001 + tag: VP_ISA_RV32_F003_S004_I001 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -306,7 +306,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S004_I002 + tag: VP_ISA_RV32_F003_S004_I002 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -330,7 +330,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S005_I000 + tag: VP_ISA_RV32_F003_S005_I000 description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -347,7 +347,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S005_I001 + tag: VP_ISA_RV32_F003_S005_I001 description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -372,7 +372,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S006_I000 + tag: VP_ISA_RV32_F003_S006_I000 description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -389,7 +389,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S006_I001 + tag: VP_ISA_RV32_F003_S006_I001 description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -414,7 +414,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S007_I000 + tag: VP_ISA_RV32_F003_S007_I000 description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -431,7 +431,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S007_I001 + tag: VP_ISA_RV32_F003_S007_I001 description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml index 01a61498b..13e030135 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F004_S000_I000 + tag: VP_ISA_RV32_F004_S000_I000 description: "Fence operation executed\nImplementation is microarchitecture\ \ specific" reqt_doc: "ISA\nChapter 2.7" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml index 85fd2a35c..7de113c11 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F005_S000_I000 + tag: VP_ISA_RV32_F005_S000_I000 description: Software exception vector entered reqt_doc: "ISA\nChapter 2.8" ref_mode: '' @@ -28,7 +28,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F005_S000_I001 + tag: VP_ISA_RV32_F005_S000_I001 description: Return control to a debugger reqt_doc: "ISA\nChapter 2.8" ref_mode: '' @@ -50,7 +50,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F005_S001_I000 + tag: VP_ISA_RV32_F005_S001_I000 description: Return control to a debugger reqt_doc: "ISA\nChapter 2.8" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml index fa7e67190..ad8ffc9a4 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S000_I000 + tag: VP_ISA_RV32_F006_S000_I000 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S000_I001 + tag: VP_ISA_RV32_F006_S000_I001 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S000_I002 + tag: VP_ISA_RV32_F006_S000_I002 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -78,7 +78,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S001_I000 + tag: VP_ISA_RV32_F006_S001_I000 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -99,7 +99,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S001_I001 + tag: VP_ISA_RV32_F006_S001_I001 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -120,7 +120,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S001_I002 + tag: VP_ISA_RV32_F006_S001_I002 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -144,7 +144,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S002_I000 + tag: VP_ISA_RV32_F006_S002_I000 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -165,7 +165,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S002_I001 + tag: VP_ISA_RV32_F006_S002_I001 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -186,7 +186,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S002_I002 + tag: VP_ISA_RV32_F006_S002_I002 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -210,7 +210,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S003_I000 + tag: VP_ISA_RV32_F006_S003_I000 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -232,7 +232,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S003_I001 + tag: VP_ISA_RV32_F006_S003_I001 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -253,7 +253,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S003_I002 + tag: VP_ISA_RV32_F006_S003_I002 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml index bb6964c43..729b10f13 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S000_I000 + tag: VP_ISA_RV32_F007_S000_I000 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S000_I001 + tag: VP_ISA_RV32_F007_S000_I001 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S000_I002 + tag: VP_ISA_RV32_F007_S000_I002 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -74,7 +74,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S000_I003 + tag: VP_ISA_RV32_F007_S000_I003 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -98,7 +98,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S001_I000 + tag: VP_ISA_RV32_F007_S001_I000 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -120,7 +120,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S001_I001 + tag: VP_ISA_RV32_F007_S001_I001 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -142,7 +142,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S001_I002 + tag: VP_ISA_RV32_F007_S001_I002 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -161,7 +161,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S001_I003 + tag: VP_ISA_RV32_F007_S001_I003 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -186,7 +186,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S002_I000 + tag: VP_ISA_RV32_F007_S002_I000 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -207,7 +207,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S002_I001 + tag: VP_ISA_RV32_F007_S002_I001 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -228,7 +228,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S002_I002 + tag: VP_ISA_RV32_F007_S002_I002 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -246,7 +246,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S002_I003 + tag: VP_ISA_RV32_F007_S002_I003 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -269,7 +269,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S003_I000 + tag: VP_ISA_RV32_F007_S003_I000 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -290,7 +290,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S003_I001 + tag: VP_ISA_RV32_F007_S003_I001 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -311,7 +311,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S003_I002 + tag: VP_ISA_RV32_F007_S003_I002 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -329,7 +329,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S003_I003 + tag: VP_ISA_RV32_F007_S003_I003 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml index 9677eec74..4c817cebf 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S000_I000 + tag: VP_ISA_RV32_F008_S000_I000 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S000_I001 + tag: VP_ISA_RV32_F008_S000_I001 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -48,7 +48,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S000_I002 + tag: VP_ISA_RV32_F008_S000_I002 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -65,7 +65,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F008_S000_I003 + tag: VP_ISA_RV32_F008_S000_I003 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -89,7 +89,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S001_I000 + tag: VP_ISA_RV32_F008_S001_I000 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -112,7 +112,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S001_I001 + tag: VP_ISA_RV32_F008_S001_I001 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -133,7 +133,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S001_I002 + tag: VP_ISA_RV32_F008_S001_I002 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -154,7 +154,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F008_S001_I003 + tag: VP_ISA_RV32_F008_S001_I003 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml index 3c1a267e4..75717fbf1 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S000_I000 + tag: VP_ISA_RV32_F009_S000_I000 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S000_I001 + tag: VP_ISA_RV32_F009_S000_I001 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -52,7 +52,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S000_I002 + tag: VP_ISA_RV32_F009_S000_I002 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -70,7 +70,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S000_I003 + tag: VP_ISA_RV32_F009_S000_I003 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -95,7 +95,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S001_I000 + tag: VP_ISA_RV32_F009_S001_I000 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -117,7 +117,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S001_I001 + tag: VP_ISA_RV32_F009_S001_I001 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -137,7 +137,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S001_I002 + tag: VP_ISA_RV32_F009_S001_I002 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -157,7 +157,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S001_I003 + tag: VP_ISA_RV32_F009_S001_I003 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -183,7 +183,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S002_I000 + tag: VP_ISA_RV32_F009_S002_I000 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -205,7 +205,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S002_I001 + tag: VP_ISA_RV32_F009_S002_I001 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -225,7 +225,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S002_I002 + tag: VP_ISA_RV32_F009_S002_I002 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -244,7 +244,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S002_I003 + tag: VP_ISA_RV32_F009_S002_I003 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -270,7 +270,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S003_I000 + tag: VP_ISA_RV32_F009_S003_I000 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -291,7 +291,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S003_I001 + tag: VP_ISA_RV32_F009_S003_I001 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -310,7 +310,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S003_I002 + tag: VP_ISA_RV32_F009_S003_I002 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -328,7 +328,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S003_I003 + tag: VP_ISA_RV32_F009_S003_I003 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -353,7 +353,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S004_I000 + tag: VP_ISA_RV32_F009_S004_I000 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -375,7 +375,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S004_I001 + tag: VP_ISA_RV32_F009_S004_I001 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -395,7 +395,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S004_I002 + tag: VP_ISA_RV32_F009_S004_I002 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -414,7 +414,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S004_I003 + tag: VP_ISA_RV32_F009_S004_I003 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -440,7 +440,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S005_I000 + tag: VP_ISA_RV32_F009_S005_I000 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -462,7 +462,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S005_I001 + tag: VP_ISA_RV32_F009_S005_I001 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -482,7 +482,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S005_I002 + tag: VP_ISA_RV32_F009_S005_I002 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -502,7 +502,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S005_I003 + tag: VP_ISA_RV32_F009_S005_I003 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -528,7 +528,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S006_I000 + tag: VP_ISA_RV32_F009_S006_I000 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -550,7 +550,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S006_I001 + tag: VP_ISA_RV32_F009_S006_I001 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -570,7 +570,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S006_I002 + tag: VP_ISA_RV32_F009_S006_I002 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -589,7 +589,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S006_I003 + tag: VP_ISA_RV32_F009_S006_I003 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -615,7 +615,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S007_I000 + tag: VP_ISA_RV32_F009_S007_I000 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -637,7 +637,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S007_I001 + tag: VP_ISA_RV32_F009_S007_I001 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -657,7 +657,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S007_I002 + tag: VP_ISA_RV32_F009_S007_I002 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -677,7 +677,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S007_I003 + tag: VP_ISA_RV32_F009_S007_I003 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -703,7 +703,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S008_I000 + tag: VP_ISA_RV32_F009_S008_I000 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -725,7 +725,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S008_I001 + tag: VP_ISA_RV32_F009_S008_I001 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -745,7 +745,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S008_I002 + tag: VP_ISA_RV32_F009_S008_I002 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -764,7 +764,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S008_I003 + tag: VP_ISA_RV32_F009_S008_I003 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml index 21eb1d64e..eb4420529 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S000_I000 + tag: VP_ISA_RV32_F010_S000_I000 description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -29,7 +29,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S000_I001 + tag: VP_ISA_RV32_F010_S000_I001 description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -52,7 +52,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S001_I000 + tag: VP_ISA_RV32_F010_S001_I000 description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ \ calculated using signed arithmetic." @@ -70,7 +70,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S001_I001 + tag: VP_ISA_RV32_F010_S001_I001 description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ \ calculated using signed arithmetic." @@ -94,7 +94,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S002_I000 + tag: VP_ISA_RV32_F010_S002_I000 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -112,7 +112,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S002_I001 + tag: VP_ISA_RV32_F010_S002_I001 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -131,7 +131,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S002_I002 + tag: VP_ISA_RV32_F010_S002_I002 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -155,7 +155,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S003_I000 + tag: VP_ISA_RV32_F010_S003_I000 description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ \ signed arithmetic." @@ -175,7 +175,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S003_I001 + tag: VP_ISA_RV32_F010_S003_I001 description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ \ signed arithmetic." @@ -199,7 +199,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S004_I000 + tag: VP_ISA_RV32_F010_S004_I000 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -217,7 +217,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S004_I001 + tag: VP_ISA_RV32_F010_S004_I001 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -236,7 +236,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S004_I002 + tag: VP_ISA_RV32_F010_S004_I002 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -260,7 +260,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S005_I000 + tag: VP_ISA_RV32_F010_S005_I000 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -277,7 +277,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S005_I001 + tag: VP_ISA_RV32_F010_S005_I001 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -295,7 +295,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S005_I002 + tag: VP_ISA_RV32_F010_S005_I002 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -318,7 +318,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S006_I000 + tag: VP_ISA_RV32_F010_S006_I000 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -335,7 +335,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S006_I001 + tag: VP_ISA_RV32_F010_S006_I001 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -353,7 +353,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S006_I002 + tag: VP_ISA_RV32_F010_S006_I002 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -376,7 +376,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S007_I000 + tag: VP_ISA_RV32_F010_S007_I000 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -393,7 +393,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S007_I001 + tag: VP_ISA_RV32_F010_S007_I001 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -412,7 +412,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S007_I002 + tag: VP_ISA_RV32_F010_S007_I002 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -435,7 +435,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S008_I000 + tag: VP_ISA_RV32_F010_S008_I000 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -452,7 +452,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S008_I001 + tag: VP_ISA_RV32_F010_S008_I001 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -471,7 +471,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S008_I002 + tag: VP_ISA_RV32_F010_S008_I002 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -494,7 +494,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S009_I000 + tag: VP_ISA_RV32_F010_S009_I000 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -512,7 +512,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S009_I001 + tag: VP_ISA_RV32_F010_S009_I001 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -529,7 +529,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S009_I002 + tag: VP_ISA_RV32_F010_S009_I002 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -552,7 +552,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S010_I000 + tag: VP_ISA_RV32_F010_S010_I000 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -569,7 +569,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S010_I001 + tag: VP_ISA_RV32_F010_S010_I001 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -588,7 +588,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S010_I002 + tag: VP_ISA_RV32_F010_S010_I002 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -612,7 +612,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S011_I000 + tag: VP_ISA_RV32_F010_S011_I000 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -629,7 +629,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S011_I001 + tag: VP_ISA_RV32_F010_S011_I001 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -648,7 +648,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S011_I002 + tag: VP_ISA_RV32_F010_S011_I002 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -671,7 +671,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S012_I000 + tag: VP_ISA_RV32_F010_S012_I000 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -688,7 +688,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S012_I001 + tag: VP_ISA_RV32_F010_S012_I001 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -707,7 +707,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S012_I002 + tag: VP_ISA_RV32_F010_S012_I002 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -730,7 +730,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S013_I000 + tag: VP_ISA_RV32_F010_S013_I000 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -747,7 +747,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S013_I001 + tag: VP_ISA_RV32_F010_S013_I001 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -766,7 +766,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S013_I002 + tag: VP_ISA_RV32_F010_S013_I002 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -789,7 +789,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S014_I000 + tag: VP_ISA_RV32_F010_S014_I000 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -806,7 +806,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S014_I001 + tag: VP_ISA_RV32_F010_S014_I001 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -825,7 +825,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S014_I002 + tag: VP_ISA_RV32_F010_S014_I002 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -848,7 +848,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S015_I000 + tag: VP_ISA_RV32_F010_S015_I000 description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." reqt_doc: "Unprivileged ISA\nChapter 16.5" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml index c95e04332..38e84fc44 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S000_I000 + tag: VP_ISA_RV32_F011_S000_I000 description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ \ arithmetic\nExpands to jal x0, imm[11:1]." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -36,7 +36,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S001_I000 + tag: VP_ISA_RV32_F011_S001_I000 description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ \ using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S001_I001 + tag: VP_ISA_RV32_F011_S001_I001 description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ \ using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -77,7 +77,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S002_I000 + tag: VP_ISA_RV32_F011_S002_I000 description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ \ when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -94,7 +94,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S002_I001 + tag: VP_ISA_RV32_F011_S002_I001 description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ \ when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -117,7 +117,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S003_I000 + tag: VP_ISA_RV32_F011_S003_I000 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -134,7 +134,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S003_I001 + tag: VP_ISA_RV32_F011_S003_I001 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -151,7 +151,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S003_I002 + tag: VP_ISA_RV32_F011_S003_I002 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -174,7 +174,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S004_I000 + tag: VP_ISA_RV32_F011_S004_I000 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -191,7 +191,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S004_I001 + tag: VP_ISA_RV32_F011_S004_I001 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -208,7 +208,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S004_I002 + tag: VP_ISA_RV32_F011_S004_I002 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -231,7 +231,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S005_I000 + tag: VP_ISA_RV32_F011_S005_I000 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -248,7 +248,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S005_I001 + tag: VP_ISA_RV32_F011_S005_I001 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -265,7 +265,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S005_I002 + tag: VP_ISA_RV32_F011_S005_I002 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml index 7fe21ee0d..776d2d465 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S000_I000 + tag: VP_ISA_RV32_F012_S000_I000 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S000_I001 + tag: VP_ISA_RV32_F012_S000_I001 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -49,7 +49,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S000_I002 + tag: VP_ISA_RV32_F012_S000_I002 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -74,7 +74,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S001_I000 + tag: VP_ISA_RV32_F012_S001_I000 description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -91,7 +91,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S001_I001 + tag: VP_ISA_RV32_F012_S001_I001 description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -115,7 +115,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S002_I000 + tag: VP_ISA_RV32_F012_S002_I000 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -134,7 +134,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S002_I001 + tag: VP_ISA_RV32_F012_S002_I001 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -152,7 +152,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S002_I002 + tag: VP_ISA_RV32_F012_S002_I002 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -176,7 +176,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S003_I000 + tag: VP_ISA_RV32_F012_S003_I000 description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -195,7 +195,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S003_I001 + tag: VP_ISA_RV32_F012_S003_I001 description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." reqt_doc: "Unprivileged ISA\nChapter 16.3" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml index b13e60860..2cd64fbfc 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S000_I000 + tag: VP_ISA_RV32_F013_S000_I000 description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" reqt_doc: ISA Chapter 9 ref_mode: '' @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S000_I001 + tag: VP_ISA_RV32_F013_S000_I001 description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" reqt_doc: ISA Chapter 9 ref_mode: '' @@ -53,7 +53,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S001_I000 + tag: VP_ISA_RV32_F013_S001_I000 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -72,7 +72,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S001_I001 + tag: VP_ISA_RV32_F013_S001_I001 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -96,7 +96,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S002_I000 + tag: VP_ISA_RV32_F013_S002_I000 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -115,7 +115,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S002_I001 + tag: VP_ISA_RV32_F013_S002_I001 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -139,7 +139,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S003_I000 + tag: VP_ISA_RV32_F013_S003_I000 description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ If rd == x0 then CSR is not read." reqt_doc: ISA Chapter 9 @@ -157,7 +157,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S003_I001 + tag: VP_ISA_RV32_F013_S003_I001 description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ If rd == x0 then CSR is not read." reqt_doc: ISA Chapter 9 @@ -181,7 +181,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S004_I000 + tag: VP_ISA_RV32_F013_S004_I000 description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -199,7 +199,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S004_I001 + tag: VP_ISA_RV32_F013_S004_I001 description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -223,7 +223,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S005_I000 + tag: VP_ISA_RV32_F013_S005_I000 description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -241,7 +241,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S005_I001 + tag: VP_ISA_RV32_F013_S005_I001 description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml index b12d713c9..b4fbf21f9 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F006_S000_I000 + tag: VP_ISA_RV32_F014_S000_I000 description: "Fence.I instruction executed\nImplementation is core-specific" reqt_doc: "Unprivileged ISA\nChapter 3" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index b301c7850..0af7efb8d 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -17,11 +17,11 @@ export PLATFORM_TOP_DIR="$ROOTDIR" # Set the printable name for the project that will be used # in the human-readable documentation. -export PROJECT_NAME="ISA" +export PROJECT_NAME="ISA RISC-V 32b" # Set the alphanumerical identifier of the project that # will be used to construct file names etc. -export PROJECT_IDENT="ISA" +export PROJECT_IDENT="ISA_RV32" # Set the destination directory of Markdown files for this project. # Since it will be used by VPTOOL, it shall NOT be a relative path. From b388ebd51c592c02a7b5e9edd28398c0f0c7b654 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Tue, 14 Feb 2023 14:30:48 +0100 Subject: [PATCH 037/183] AXI: Add verification plan and files to run it with vptool Signed-off-by: Alae Eddine Ez zejjari --- cva6/docs/VerifPlans/AXI/VP_IP005.yml | 104 +++++ cva6/docs/VerifPlans/AXI/VP_IP006.yml | 179 +++++++++ cva6/docs/VerifPlans/AXI/VP_IP007.yml | 64 +++ cva6/docs/VerifPlans/AXI/VP_IP008.yml | 141 +++++++ cva6/docs/VerifPlans/AXI/runme.sh | 34 ++ cva6/docs/VerifPlans/source/dvplan_AXI.md | 461 ++++++++++++++++++++++ cva6/docs/VerifPlans/source/index.rst | 1 + 7 files changed, 984 insertions(+) create mode 100644 cva6/docs/VerifPlans/AXI/VP_IP005.yml create mode 100644 cva6/docs/VerifPlans/AXI/VP_IP006.yml create mode 100644 cva6/docs/VerifPlans/AXI/VP_IP007.yml create mode 100644 cva6/docs/VerifPlans/AXI/VP_IP008.yml create mode 100644 cva6/docs/VerifPlans/AXI/runme.sh create mode 100644 cva6/docs/VerifPlans/source/dvplan_AXI.md diff --git a/cva6/docs/VerifPlans/AXI/VP_IP005.yml b/cva6/docs/VerifPlans/AXI/VP_IP005.yml new file mode 100644 index 000000000..05353b025 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP005.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 2 +name: Burst +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_Control_Signals: !Subfeature + name: 000_Control_Signals + tag: VP_IP005_P000 + next_elt_id: 12 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F005_S000_I000 + description: All transaction performed by CVA6 are of type INCR. AxBURST = + 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxBURST == 0b01 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F005_S000_I001 + description: All Read transaction performed by CVA6 are of burst lenght less + or equal to 2. ARLEN = 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F005_S000_I002 + description: All write transaction performed by CVA6 are of burst lenght equal + to 1. AWLEN = 0b00 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F005_S000_I003 + description: The size of a read transfer does not exceed the width of the + data interface. The maximum value can be taking by AxSIZE is 3. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '007': !VerifItem + name: '007' + tag: VP_1_F005_S000_I007 + description: Exclusive access transactions cannot have a length greater than + 16 beats + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID + is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP006.yml b/cva6/docs/VerifPlans/AXI/VP_IP006.yml new file mode 100644 index 000000000..768ff9560 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP006.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 9 +name: Signals +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_ID: !Subfeature + name: 000_ID + tag: VP_IP006_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S000_I000 + description: The CVA6 identify read transaction with an ID equal to 0 or 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S000_I001 + description: The CVA6 identify write transaction with an ID equal to 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWID == 0b01 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_User: !Subfeature + name: 001_User + tag: VP_IP006_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S001_I000 + description: User-defined extension for the write and read address channel + is not supported. AxUSER = 0b00 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S001_I001 + description: User-defined extension for the write response channel is not + supported. + reqt_doc: AXI Design doc - (table 2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that BUSER = 0b00 is always true while B_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 002_Quality_of_Service: !Subfeature + name: 002_Quality_of_Service + tag: VP_IP006_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S002_I000 + description: Quality of Service identifier is not supported. AxQOS = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 003_Cache: !Subfeature + name: 003_Cache + tag: VP_IP006_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S003_I000 + description: AxCACHE always take 0b0000. + reqt_doc: 'AXI Design Doc - Transaction Attributes: Memory types' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxCACHE = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 004_Protection: !Subfeature + name: 004_Protection + tag: VP_IP006_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S004_I000 + description: Protection attributes always take the 0b000 + reqt_doc: AXI Design Doc - (Table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 008_Region: !Subfeature + name: 008_Region + tag: VP_IP006_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S008_I000 + description: Region indicator is not supported. AxREGION = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxREGION = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP007.yml b/cva6/docs/VerifPlans/AXI/VP_IP007.yml new file mode 100644 index 000000000..202bd170b --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP007.yml @@ -0,0 +1,64 @@ +!Feature +next_elt_id: 1 +name: Clock and Reset +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_Signals_Value: !Subfeature + name: 000_Signals_Value + tag: VP_IP007_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F007_S000_I000 + description: A value of X on [Ax | x]VALID is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]VALID != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F007_S000_I001 + description: A value of X on [Ax | x]READY is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]READY != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F007_S000_I002 + description: '[Ax | x]VALID is LOW for the first cycle after RESET goes HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID is low the first cycle after RESET + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/VP_IP008.yml b/cva6/docs/VerifPlans/AXI/VP_IP008.yml new file mode 100644 index 000000000..642c70531 --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/VP_IP008.yml @@ -0,0 +1,141 @@ +!Feature +next_elt_id: 3 +name: Handshake_Process +id: 8 +display_order: 8 +subfeatures: !!omap +- '000_Stability ': !Subfeature + name: '000_Stability ' + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S000_I000 + description: All signals must remain stable when [Ax | x]VALID is asserted + and [Ax | x]READY is LOW + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that all the signals does not change while [Ax | x]VALID + is asserted and [Ax | x]READY not yet asserted. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F008_S000_I001 + description: '[Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID does not change while [Ax | x]READY + is low. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_Timing: !Subfeature + name: 001_Timing + tag: VP_IP008_P001 + next_elt_id: 8 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S001_I000 + description: The Manager must not wait for the Subordinate to assert ARREADY + before asserting ARVALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY\ + \ is asserted on or after same cycle as ARVALID\nARREADY is asserted and\ + \ deasserted during an interval when ARVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F008_S001_I002 + description: The Manager must not wait for the Subordinate to assert AWREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nAWREADY is asserted on or after\ + \ same cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on\ + \ or after same cycle as WVALID and AWVALID is de-asserted\nAWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nAWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F008_S001_I003 + description: The Manager must not wait for the Subordinate to assert WREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nWREADY is asserted on or\ + \ after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted\ + \ on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '005': !VerifItem + name: '005' + tag: VP_1_F008_S001_I005 + description: The Subordinate must not wait for the Manager to assert [B | + R]READY before asserting [B | R]VALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: No specific “observable checks†to be made in simulation. Testbench + will always provide response data independently of [B | R]READY. + pfc: 0 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/AXI/runme.sh b/cva6/docs/VerifPlans/AXI/runme.sh new file mode 100644 index 000000000..b0cfce34d --- /dev/null +++ b/cva6/docs/VerifPlans/AXI/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="AXI" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="AXI" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/cva6/docs/VerifPlans/source/dvplan_AXI.md b/cva6/docs/VerifPlans/source/dvplan_AXI.md new file mode 100644 index 000000000..a7399eca0 --- /dev/null +++ b/cva6/docs/VerifPlans/source/dvplan_AXI.md @@ -0,0 +1,461 @@ +# Module: AXI + +## Feature: Burst + +### Sub-feature: 000_Control_Signals + +#### Item: 000 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All transaction performed by CVA6 are of type INCR. AxBURST = 0b01 +* **Verification Goals** + + Ensure that AxBURST == 0b01 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All Read transaction performed by CVA6 are of burst lenght less or equal to 2. ARLEN = 0b01 +* **Verification Goals** + + Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All write transaction performed by CVA6 are of burst lenght equal to 1. AWLEN = 0b00 +* **Verification Goals** + + Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1) +* **Feature Description** + + The size of a read transfer does not exceed the width of the data interface. The maximum value can be taking by AxSIZE is 3. +* **Verification Goals** + + Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 007 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) +* **Feature Description** + + Exclusive access transactions cannot have a length greater than 16 beats +* **Verification Goals** + + Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I007 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Signals + +### Sub-feature: 000_ID + +#### Item: 000 + +* **Requirement location:** AXI Design doc - Transaction Identifiers +* **Feature Description** + + The CVA6 identify read transaction with an ID equal to 0 or 1 +* **Verification Goals** + + Ensure that ARID == 0b01 || ARID == 0b00 is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - Transaction Identifiers +* **Feature Description** + + The CVA6 identify write transaction with an ID equal to 1 +* **Verification Goals** + + Ensure that AWID == 0b01 is always true while AW_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_User + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + User-defined extension for the write and read address channel is not supported. AxUSER = 0b00 +* **Verification Goals** + + Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - (table 2.4) +* **Feature Description** + + User-defined extension for the write response channel is not supported. +* **Verification Goals** + + Ensure that BUSER = 0b00 is always true while B_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_Quality_of_Service + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + Quality of Service identifier is not supported. AxQOS = 0b0000 +* **Verification Goals** + + Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Cache + +#### Item: 000 + +* **Requirement location:** AXI Design Doc - Transaction Attributes: Memory types +* **Feature Description** + + AxCACHE always take 0b0000. +* **Verification Goals** + + Ensure that AxCACHE = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Protection + +#### Item: 000 + +* **Requirement location:** AXI Design Doc - (Table 2.2 and 2.5) +* **Feature Description** + + Protection attributes always take the 0b000 +* **Verification Goals** + + Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_Region + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + Region indicator is not supported. AxREGION = 0b0000 +* **Verification Goals** + + Ensure that AxREGION = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Clock and Reset + +### Sub-feature: 000_Signals_Value + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) +* **Feature Description** + + A value of X on [Ax | x]VALID is not permitted when not in reset +* **Verification Goals** + + Ensure that reset && [Ax | x]VALID != X is always true +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) +* **Feature Description** + + A value of X on [Ax | x]READY is not permitted when not in reset +* **Verification Goals** + + Ensure that reset && [Ax | x]READY != X is always true +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1) +* **Feature Description** + + [Ax | x]VALID is LOW for the first cycle after RESET goes HIGH +* **Verification Goals** + + Ensure that [Ax | x]VALID is low the first cycle after RESET +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Handshake_Process + +### Sub-feature: 000_Stability + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2) +* **Feature Description** + + All signals must remain stable when [Ax | x]VALID is asserted and [Ax | x]READY is LOW +* **Verification Goals** + + Ensure that all the signals does not change while [Ax | x]VALID is asserted and [Ax | x]READY not yet asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1) +* **Feature Description** + + [Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH +* **Verification Goals** + + Ensure that [Ax | x]VALID does not change while [Ax | x]READY is low. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Timing + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert ARREADY before asserting ARVALID +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are two cases to consider: + + ARREADY is asserted on or after same cycle as ARVALID + ARREADY is asserted and deasserted during an interval when ARVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert AWREADY before asserting AWVALID or WVALID. +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider: + + AWREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted + AWREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted + AWREADY is asserted on or after same cycle as AWVALID and WVALID + AWREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert WREADY before asserting AWVALID or WVALID. +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider: + + WREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted + WREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted + WREADY is asserted on or after same cycle as AWVALID and WVALID + WREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 005 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Subordinate must not wait for the Manager to assert [B | R]READY before asserting [B | R]VALID +* **Verification Goals** + + No specific “observable checks†to be made in simulation. Testbench will always provide response data independently of [B | R]READY. +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I005 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/cva6/docs/VerifPlans/source/index.rst b/cva6/docs/VerifPlans/source/index.rst index 4ef40bc02..9d746186a 100644 --- a/cva6/docs/VerifPlans/source/index.rst +++ b/cva6/docs/VerifPlans/source/index.rst @@ -25,4 +25,5 @@ CV32A6-step1 Design Verification Plan dvplan_intro dvplan_FRONTEND dvplan_ISA + dvplan_AXI From 8fb057b666125a74f97949f9722a726e1081102b Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 7 Dec 2022 17:27:10 +0100 Subject: [PATCH 038/183] axi_agent: Add the Active mode agent and configure the agent to be able to act as active/passive agent Signed-off-by: Alae Eddine Ez zejjari --- .../uvma_axi/src/comps/uvma_axi_agent.sv | 64 ++++++ .../uvma_axi_ar_agent/uvma_axi_ar_agent.sv | 21 ++ .../uvma_axi_ar_agent/uvma_axi_ar_drv.sv | 81 +++++++ .../uvma_axi_ar_agent/uvma_axi_ar_mon.sv | 25 ++ .../uvma_axi_ar_agent/uvma_axi_ar_sqr.sv | 52 +++++ .../uvma_axi_aw_agent/uvma_axi_aw_agent.sv | 23 ++ .../uvma_axi_aw_agent/uvma_axi_aw_drv.sv | 95 ++++++++ .../uvma_axi_aw_agent/uvma_axi_aw_mon.sv | 28 +++ .../uvma_axi_aw_agent/uvma_axi_aw_sqr.sv | 56 +++++ .../uvma_axi_b_agent/uvma_axi_b_agent.sv | 23 +- .../comps/uvma_axi_b_agent/uvma_axi_b_drv.sv | 100 ++++++++ .../comps/uvma_axi_b_agent/uvma_axi_b_mon.sv | 22 ++ .../comps/uvma_axi_b_agent/uvma_axi_b_sqr.sv | 61 +++++ .../uvma_axi_r_agent/uvma_axi_r_agent.sv | 25 ++ .../comps/uvma_axi_r_agent/uvma_axi_r_drv.sv | 106 +++++++++ .../comps/uvma_axi_r_agent/uvma_axi_r_mon.sv | 25 +- .../comps/uvma_axi_r_agent/uvma_axi_r_sqr.sv | 58 +++++ .../uvma_axi/src/comps/uvma_axi_vseq.sv | 105 +++++++++ .../uvma_axi/src/comps/uvma_axi_vsqr.sv | 51 +++++ .../uvma_axi_w_agent/uvma_axi_w_agent.sv | 26 +++ .../comps/uvma_axi_w_agent/uvma_axi_w_drv.sv | 103 +++++++++ .../comps/uvma_axi_w_agent/uvma_axi_w_mon.sv | 22 ++ .../comps/uvma_axi_w_agent/uvma_axi_w_sqr.sv | 58 +++++ .../uvma_axi/src/obj/uvma_axi_cfg.sv | 39 ++++ .../uvma_axi/src/obj/uvma_axi_cntxt.sv | 4 + .../uvma_axi/src/seq/uvma_axi_ar_seq.sv | 54 +++++ .../uvma_axi/src/seq/uvma_axi_aw_seq.sv | 56 +++++ .../uvma_axi/src/seq/uvma_axi_b_seq.sv | 187 +++++++++++++++ .../src/seq/uvma_axi_fw_preload_seq.sv | 91 ++++++++ .../uvma_axi/src/seq/uvma_axi_r_seq.sv | 213 ++++++++++++++++++ .../uvma_axi/src/seq/uvma_axi_seq_lib.sv | 47 ++++ .../uvma_axi/src/seq/uvma_axi_w_seq.sv | 145 ++++++++++++ lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv | 19 ++ 33 files changed, 2083 insertions(+), 2 deletions(-) create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_sqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_sqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_drv.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_sqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_drv.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_sqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vseq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vsqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_sqr.sv create mode 100644 lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_fw_preload_seq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_seq_lib.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv index 6722f2424..b3652b533 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv @@ -22,7 +22,9 @@ class uvma_axi_agent_c extends uvm_agent; uvma_axi_b_agent_c b_agent; uvma_axi_ar_agent_c ar_agent; uvma_axi_r_agent_c r_agent; + uvma_axi_vsqr_c vsequencer; + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; function new(string name = "uvma_axi_agent_c", uvm_component parent = null); @@ -32,6 +34,7 @@ class uvma_axi_agent_c extends uvm_agent; function void build_phase(uvm_phase phase); super.build_phase(phase); + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); @@ -49,6 +52,19 @@ class uvma_axi_agent_c extends uvm_agent; endfunction : get_and_set_cntxt + function void get_and_set_cfg(); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + else begin + `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) + uvm_config_db#(uvma_axi_cfg_c)::set(this, "*", "cfg", cfg); + end + + endfunction : get_and_set_cfg + function void retrieve_vif(); if (!uvm_config_db#(virtual uvma_axi_intf)::get(this, "", "axi_vif", cntxt.axi_vi)) begin @@ -67,9 +83,57 @@ class uvma_axi_agent_c extends uvm_agent; this.b_agent = uvma_axi_b_agent_c :: type_id :: create("b_agent", this); this.ar_agent = uvma_axi_ar_agent_c :: type_id :: create("ar_agent", this); this.r_agent = uvma_axi_r_agent_c :: type_id :: create("r_agent", this); + if( cfg.is_active == UVM_ACTIVE) begin + vsequencer = uvma_axi_vsqr_c::type_id::create("sequencer", this); + end endfunction : create_components + function void connect_phase(uvm_phase phase); + + //super.connect_phase(phase); + if( cfg.is_active == UVM_ACTIVE) begin + connect_mon_2_sqr(); + assemble_vsequencer(); + end else begin + `uvm_info(get_type_name(), $sformatf("PASSIVE MODE"), UVM_LOW) + end + + endfunction + + function void connect_mon_2_sqr(); + + this.aw_agent.monitor.uvma_aw_mon2drv_port.connect(aw_agent.sequencer.aw_req_export); + + this.w_agent.monitor.uvma_w_mon2drv_port.connect(w_agent.sequencer.w_req_export); + + this.aw_agent.monitor.uvma_aw_mon2drv_port.connect(w_agent.sequencer.aw_req_export.analysis_export); + + this.aw_agent.monitor.uvma_aw_mon_port.connect(b_agent.sequencer.aw_req_export.analysis_export); + + this.w_agent.monitor.uvma_w_mon_port.connect(b_agent.sequencer.w_req_export.analysis_export); + + this.b_agent.monitor.uvma_b_mon2drv_port.connect(b_agent.sequencer.b_resp_export); + + this.ar_agent.monitor.uvma_ar_mon2drv_port.connect(ar_agent.sequencer.ar_req_export); + + this.ar_agent.monitor.uvma_ar_mon_port.connect(r_agent.sequencer.ar_req_export.analysis_export); + + this.r_agent.monitor.uvma_r_mon_port.connect(r_agent.sequencer.r_resp_export); + + endfunction: connect_mon_2_sqr + + function void assemble_vsequencer(); + + vsequencer.aw_sequencer = aw_agent.sequencer; + vsequencer.ar_sequencer = ar_agent.sequencer; + vsequencer.w_sequencer = w_agent.sequencer; + vsequencer.b_sequencer = b_agent.sequencer; + vsequencer.r_sequencer = r_agent.sequencer; + + endfunction: assemble_vsequencer + + endclass : uvma_axi_agent_c `endif //__UVMA_AXI_AGENT_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv index 41b056864..dfda8bea0 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_agent.sv @@ -16,9 +16,14 @@ class uvma_axi_ar_agent_c extends uvm_agent; uvma_axi_ar_mon_c monitor; + uvma_axi_ar_sqr_c sequencer; + uvma_axi_ar_drv_c driver; + uvma_axi_cfg_c cfg; `uvm_component_utils_begin(uvma_axi_ar_agent_c) `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_field_object(sequencer, UVM_ALL_ON) + `uvm_field_object(driver, UVM_ALL_ON) `uvm_component_utils_end function new(string name = "uvma_axi_ar_agent_c", uvm_component parent = null); @@ -27,9 +32,25 @@ class uvma_axi_ar_agent_c extends uvm_agent; function void build_phase(uvm_phase phase); super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + if( cfg.is_active == UVM_ACTIVE) begin + this.sequencer = uvma_axi_ar_sqr_c::type_id::create("sequencer", this); + this.driver = uvma_axi_ar_drv_c::type_id::create("driver", this); + end this.monitor = uvma_axi_ar_mon_c::type_id::create("monitor", this); endfunction + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + //connect sequencer to driver + if( cfg.is_active == UVM_ACTIVE) begin + driver.seq_item_port.connect(sequencer.seq_item_export); + end + endfunction + endclass `endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv new file mode 100644 index 000000000..670843c40 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv @@ -0,0 +1,81 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave driver for AR channel ****/ + +`ifndef __UVMA_AXI_AR_DRV_SV__ +`define __UVMA_AXI_AR_DRV_SV__ + +class uvma_axi_ar_drv_c extends uvm_driver #(uvma_axi_ar_item_c); + + `uvm_component_utils(uvma_axi_ar_drv_c) + + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + uvma_axi_ar_item_c ar_item; + // Handles to virtual interface modport + virtual uvma_axi_intf.slave slave_mp; + + function new(string name = "uvma_axi_ar_drv_c", uvm_component parent); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if(!uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)) begin + `uvm_fatal("build_phase", "driver reset cntxt class failed") + end + this.slave_mp = this.cntxt.axi_vi.slave; + ar_item = uvma_axi_ar_item_c::type_id::create("ar_item", this); + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + forever begin + case (cntxt.reset_state) + UVMA_AXI_RESET_STATE_PRE_RESET : drv_pre_reset (); + UVMA_AXI_RESET_STATE_IN_RESET : drv_in_reset (); + UVMA_AXI_RESET_STATE_POST_RESET: drv_post_reset(); + + default: `uvm_fatal("AXI_AR_DRV", $sformatf("Invalid reset_state: %0d", cntxt.reset_state)) + endcase + end + endtask: run_phase + + task drv_pre_reset(); + + this.slave_mp.slv_axi_cb.ar_ready <= 0; + @(slave_mp.slv_axi_cb); + + endtask: drv_pre_reset + + task drv_in_reset(); + + this.slave_mp.slv_axi_cb.ar_ready <= 0; + @(slave_mp.slv_axi_cb); + + endtask: drv_in_reset + + task drv_post_reset(); + seq_item_port.get_next_item(ar_item); + this.slave_mp.slv_axi_cb.ar_ready <= 1'b1; + `uvm_info(get_type_name(), $sformatf("read address, response by ar_ready"), UVM_LOW) + @(slave_mp.slv_axi_cb); + seq_item_port.item_done(); + endtask: drv_post_reset + +endclass: uvma_axi_ar_drv_c + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv index 42af17013..f9d81b746 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv @@ -17,15 +17,20 @@ class uvma_axi_ar_mon_c extends uvm_monitor; `uvm_component_utils(uvma_axi_ar_mon_c) uvma_axi_ar_item_c ar_item; + uvma_axi_ar_item_c ardrv_item; uvm_analysis_port#(uvma_axi_ar_item_c) uvma_ar_mon_port; + uvm_analysis_port#(uvma_axi_ar_item_c) uvma_ar_mon2drv_port; + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; + virtual uvma_axi_intf vif; function new(string name = "uvma_axi_ar_mon_c", uvm_component parent); super.new(name, parent); this.uvma_ar_mon_port = new("uvma_ar_mon_port", this); + this.uvma_ar_mon2drv_port = new("uvma_ar_mon2drv_port", this); endfunction function void build_phase(uvm_phase phase); @@ -37,8 +42,15 @@ class uvma_axi_ar_mon_c extends uvm_monitor; end passive_mp = cntxt.axi_vi.passive; + vif = cntxt.axi_vi; ar_item = uvma_axi_ar_item_c::type_id::create("ar_item", this); + ardrv_item = uvma_axi_ar_item_c::type_id::create("ardrv_item", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end endfunction @@ -78,6 +90,19 @@ class uvma_axi_ar_mon_c extends uvm_monitor; this.ar_item.ar_lock = 0; end end + if(cfg.is_active) begin + // collect AR signals + this.ardrv_item.ar_id = vif.ar_id; + this.ardrv_item.ar_addr = vif.ar_addr; + this.ardrv_item.ar_len = vif.ar_len; + this.ardrv_item.ar_size = vif.ar_size; + this.ardrv_item.ar_burst = vif.ar_burst; + this.ardrv_item.ar_user = vif.ar_user; + this.ardrv_item.ar_valid = vif.ar_valid; + this.ardrv_item.ar_ready = vif.ar_ready; + this.ardrv_item.ar_lock = vif.ar_lock; + this.uvma_ar_mon2drv_port.write(this.ardrv_item); + end this.uvma_ar_mon_port.write(this.ar_item); @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_sqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_sqr.sv new file mode 100644 index 000000000..4da5386e0 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_sqr.sv @@ -0,0 +1,52 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +/**** AXI4 master sequencer ****/ + +`ifndef __UVMA_AXI_AR_SQR_SV__ +`define __UVMA_AXI_AR_SQR_SV__ + +class uvma_axi_ar_sqr_c extends uvm_sequencer#(uvma_axi_ar_item_c); + + `uvm_component_utils(uvma_axi_ar_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvm_analysis_export #(uvma_axi_ar_item_c) ar_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_ar_item_c) ar_req_fifo; + + function new(string name = "uvma_axi_ar_sqr_c", uvm_component parent = null); + super.new(name, parent); + this.ar_req_export = new("ar_req_export", this); + this.ar_req_fifo = new("ar_req_fifo", this); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + this.ar_req_export.connect(this.ar_req_fifo.analysis_export); // Connect analysis export direct to fifo ar channels + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv index a7a904d04..7a4c2410d 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_agent.sv @@ -16,9 +16,14 @@ class uvma_axi_aw_agent_c extends uvm_agent; uvma_axi_aw_mon_c monitor; + uvma_axi_aw_sqr_c sequencer; + uvma_axi_aw_drv_c driver; + uvma_axi_cfg_c cfg; `uvm_component_utils_begin(uvma_axi_aw_agent_c) `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_field_object(sequencer, UVM_ALL_ON) + `uvm_field_object(driver, UVM_ALL_ON) `uvm_component_utils_end function new(string name = "uvma_axi_aw_agent_c", uvm_component parent = null); @@ -28,10 +33,28 @@ class uvma_axi_aw_agent_c extends uvm_agent; function void build_phase(uvm_phase phase); super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + if( cfg.is_active == UVM_ACTIVE) begin + this.sequencer = uvma_axi_aw_sqr_c::type_id::create("sequencer", this); + this.driver = uvma_axi_aw_drv_c::type_id::create("driver", this); + end this.monitor = uvma_axi_aw_mon_c::type_id::create("monitor", this); endfunction + function void connect_phase(uvm_phase phase); + + super.connect_phase(phase); + //connect sequencer to driver + if( cfg.is_active == UVM_ACTIVE) begin + driver.seq_item_port.connect(sequencer.seq_item_export); + end + + endfunction + endclass `endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv new file mode 100644 index 000000000..515959530 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv @@ -0,0 +1,95 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave AW driver ****/ + +`ifndef __UVMA_AXI_AW_DRV_SV__ +`define __UVMA_AXI_AW_DRV_SV__ + +class uvma_axi_aw_drv_c extends uvm_driver #(uvma_axi_aw_item_c); + + `uvm_component_utils(uvma_axi_aw_drv_c) + + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_aw_item_c aw_item; + + // Handles to virtual interface modport + virtual uvma_axi_intf.slave slave_mp; + + extern function new(string name = "uvma_axi_aw_drv_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task drv_pre_reset(); + extern task drv_in_reset(); + extern task drv_post_reset(); + +endclass: uvma_axi_aw_drv_c + +function uvma_axi_aw_drv_c::new(string name = "uvma_axi_aw_drv_c", uvm_component parent); + super.new(name, parent); +endfunction + +function void uvma_axi_aw_drv_c::build_phase(uvm_phase phase); + super.build_phase(phase); + if(!uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)) begin + `uvm_fatal("build_phase", "driver reset cntxt class failed") + end + this.slave_mp = this.cntxt.axi_vi.slave; + aw_item = uvma_axi_aw_item_c::type_id::create("aw_item", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end +endfunction + +task uvma_axi_aw_drv_c::run_phase(uvm_phase phase); + super.run_phase(phase); + forever begin + case (cntxt.reset_state) + UVMA_AXI_RESET_STATE_PRE_RESET : drv_pre_reset (); + UVMA_AXI_RESET_STATE_IN_RESET : drv_in_reset (); + UVMA_AXI_RESET_STATE_POST_RESET : drv_post_reset(); + + default: `uvm_fatal("AXI_Aw_DRV", $sformatf("Invalid reset_state: %0d", cntxt.reset_state)) + endcase + end +endtask: run_phase + +task uvma_axi_aw_drv_c::drv_pre_reset(); + + this.slave_mp.slv_axi_cb.aw_ready <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_pre_reset + +task uvma_axi_aw_drv_c::drv_in_reset(); + + this.slave_mp.slv_axi_cb.aw_ready <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_in_reset + +task uvma_axi_aw_drv_c::drv_post_reset(); + + `uvm_info(get_type_name(), $sformatf("write address driver start"), UVM_LOW) + seq_item_port.get_next_item(aw_item); + + this.slave_mp.slv_axi_cb.aw_ready <= 1'b1; + @(slave_mp.slv_axi_cb); + + seq_item_port.item_done(); + +endtask: drv_post_reset + +`endif + diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv index eaef23da1..e861b4b34 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv @@ -16,18 +16,23 @@ class uvma_axi_aw_mon_c extends uvm_monitor; `uvm_component_utils(uvma_axi_aw_mon_c) + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; uvma_axi_aw_item_c aw_item; + uvma_axi_aw_item_c awdrv_item; uvm_analysis_port #(uvma_axi_aw_item_c) uvma_aw_mon_port; + uvm_analysis_port #(uvma_axi_aw_item_c) uvma_aw_mon2drv_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; + virtual uvma_axi_intf vif; function new(string name = "uvma_axi_aw_mon_c", uvm_component parent); super.new(name, parent); this.uvma_aw_mon_port = new("uvma_aw_mon_port", this); + this.uvma_aw_mon2drv_port = new("uvma_aw_mon2drv_port", this); endfunction function void build_phase(uvm_phase phase); @@ -40,8 +45,15 @@ class uvma_axi_aw_mon_c extends uvm_monitor; end passive_mp = cntxt.axi_vi.passive; + vif = cntxt.axi_vi; this.aw_item = uvma_axi_aw_item_c::type_id::create("aw_item", this); + this.awdrv_item = uvma_axi_aw_item_c::type_id::create("awdrv_item", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end endfunction @@ -89,6 +101,22 @@ class uvma_axi_aw_mon_c extends uvm_monitor; this.aw_item.aw_atop = 0; end end + + if(cfg.is_active) begin + // collect AR signals + this.awdrv_item.aw_id = vif.aw_id; + this.awdrv_item.aw_addr = vif.aw_addr; + this.awdrv_item.aw_len = vif.aw_len; + this.awdrv_item.aw_size = vif.aw_size; + this.awdrv_item.aw_burst = vif.aw_burst; + this.awdrv_item.aw_user = vif.aw_user; + this.awdrv_item.aw_valid = vif.aw_valid; + this.awdrv_item.aw_ready = vif.aw_ready; + this.awdrv_item.aw_lock = vif.aw_lock; + this.awdrv_item.aw_atop = vif.aw_atop; + this.uvma_aw_mon2drv_port.write(this.awdrv_item); + end + this.uvma_aw_mon_port.write(this.aw_item); @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_sqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_sqr.sv new file mode 100644 index 000000000..304c0aca3 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_sqr.sv @@ -0,0 +1,56 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +/**** AXI4 master sequencer ****/ + +`ifndef __UVMA_AXI_AW_SQR_SV__ +`define __UVMA_AXI_AW_SQR_SV__ + +class uvma_axi_aw_sqr_c extends uvm_sequencer#(uvma_axi_aw_item_c); + + `uvm_component_utils(uvma_axi_aw_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvm_analysis_export #(uvma_axi_aw_item_c) aw_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_aw_item_c) aw_req_fifo; + + function new(string name = "uvma_axi_aw_sqr_c", uvm_component parent = null); + + super.new(name, parent); + + this.aw_req_export = new("aw_req_export", this); + this.aw_req_fifo = new("aw_req_fifo", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + this.aw_req_export.connect(this.aw_req_fifo.analysis_export); // Connect analysis export direct to fifo aw channels + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv index 3dde7702f..2e782a693 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_agent.sv @@ -16,9 +16,14 @@ class uvma_axi_b_agent_c extends uvm_agent; uvma_axi_b_mon_c monitor; + uvma_axi_b_sqr_c sequencer; + uvma_axi_b_drv_c driver; + uvma_axi_cfg_c cfg; `uvm_component_utils_begin(uvma_axi_b_agent_c) `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_field_object(sequencer, UVM_ALL_ON) + `uvm_field_object(driver, UVM_ALL_ON) `uvm_component_utils_end function new(string name = "uvma_axi_b_agent_c", uvm_component parent = null); @@ -26,13 +31,29 @@ class uvma_axi_b_agent_c extends uvm_agent; endfunction function void build_phase(uvm_phase phase); - super.build_phase(phase); + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + if( cfg.is_active == UVM_ACTIVE) begin + this.sequencer = uvma_axi_b_sqr_c::type_id::create("sequencer", this); + this.driver = uvma_axi_b_drv_c::type_id::create("driver", this); + end this.monitor = uvma_axi_b_mon_c::type_id::create("monitor", this); endfunction + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + //connect sequencer to driver + if( cfg.is_active == UVM_ACTIVE) begin + driver.seq_item_port.connect(sequencer.seq_item_export); + end + endfunction + endclass : uvma_axi_b_agent_c `endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_drv.sv new file mode 100644 index 000000000..dc2246723 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_drv.sv @@ -0,0 +1,100 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave B channel driver ****/ + +`ifndef __UVMA_AXI_B_DRV_SV__ +`define __UVMA_AXI_B_DRV_SV__ + +class uvma_axi_b_drv_c extends uvm_driver #(uvma_axi_b_item_c); + + `uvm_component_utils(uvma_axi_b_drv_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_b_item_c b_item; + + //Handles to virtual interface modport + virtual uvma_axi_intf.slave slave_mp; + + function new(string name = "uvma_axi_b_drv_c", uvm_component parent); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + + super.build_phase(phase); + + if(!uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", this.cntxt)) begin + `uvm_fatal("build_phase", "driver cntxt class failed") + end + + this.slave_mp = this.cntxt.axi_vi.slave; + b_item = uvma_axi_b_item_c::type_id::create("b_item", this); + + endfunction + + task run_phase(uvm_phase phase); + + super.run_phase(phase); + forever begin + case (cntxt.reset_state) + UVMA_AXI_RESET_STATE_PRE_RESET : drv_pre_reset (); + UVMA_AXI_RESET_STATE_IN_RESET : drv_in_reset (); + UVMA_AXI_RESET_STATE_POST_RESET : drv_post_reset(); + + default: `uvm_fatal("AXI_AR_DRV", $sformatf("Invalid reset_state: %0d", cntxt.reset_state)) + endcase + end + + endtask: run_phase + + task drv_pre_reset(); + + this.slave_mp.slv_axi_cb.b_id <= 0; + this.slave_mp.slv_axi_cb.b_resp <= 0; + this.slave_mp.slv_axi_cb.b_user <= 0; + this.slave_mp.slv_axi_cb.b_valid <= 0; + this.slave_mp.slv_axi_cb.b_user <= 0; + @(slave_mp.slv_axi_cb); + + endtask: drv_pre_reset + + task drv_in_reset(); + + this.slave_mp.slv_axi_cb.b_id <= 0; + this.slave_mp.slv_axi_cb.b_resp <= 0; + this.slave_mp.slv_axi_cb.b_user <= 0; + this.slave_mp.slv_axi_cb.b_valid <= 0; + this.slave_mp.slv_axi_cb.b_user <= 0; + @(slave_mp.slv_axi_cb); + + endtask: drv_in_reset + + task drv_post_reset(); + + seq_item_port.get_next_item(b_item); + + `uvm_info(get_type_name(),$sformatf("response, send resp to DUT"), UVM_LOW) + + this.slave_mp.slv_axi_cb.b_id <= this.b_item.b_id; + this.slave_mp.slv_axi_cb.b_resp <= this.b_item.b_resp; + this.slave_mp.slv_axi_cb.b_user <= this.b_item.b_user; + this.slave_mp.slv_axi_cb.b_user <= this.b_item.b_user; + this.slave_mp.slv_axi_cb.b_valid <= this.b_item.b_valid; + @(slave_mp.slv_axi_cb); + + seq_item_port.item_done(); + + endtask: drv_post_reset + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv index 12062c6e3..97b0212e6 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv @@ -17,14 +17,18 @@ class uvma_axi_b_mon_c extends uvm_monitor; `uvm_component_utils(uvma_axi_b_mon_c) + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; uvma_axi_b_item_c b_item; + uvma_axi_b_item_c bdrv_item; uvm_analysis_port #(uvma_axi_b_item_c) uvma_b_mon_port; + uvm_analysis_port #(uvma_axi_b_item_c) uvma_b_mon2drv_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; + virtual uvma_axi_intf vif; extern function new(string name = "uvma_axi_b_mon_c", uvm_component parent); extern virtual function void build_phase(uvm_phase phase); @@ -35,6 +39,7 @@ endclass:uvma_axi_b_mon_c function uvma_axi_b_mon_c::new(string name = "uvma_axi_b_mon_c", uvm_component parent); super.new(name, parent); this.uvma_b_mon_port = new("uvma_b_mon_port", this); + this.uvma_b_mon2drv_port = new("uvma_b_mon2drv_port", this); endfunction function void uvma_axi_b_mon_c::build_phase(uvm_phase phase); @@ -46,9 +51,16 @@ function void uvma_axi_b_mon_c::build_phase(uvm_phase phase); `uvm_fatal("build_phase", "monitor cntxt class failed") end + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + passive_mp = cntxt.axi_vi.passive; + vif = cntxt.axi_vi; this.b_item = uvma_axi_b_item_c::type_id::create("b_item", this); + this.bdrv_item = uvma_axi_b_item_c::type_id::create("bdrv_item", this); endfunction:build_phase @@ -69,6 +81,16 @@ task uvma_axi_b_mon_c::monitor_b_items(); this.b_item.b_valid = passive_mp.psv_axi_cb.b_valid; this.b_item.b_ready = passive_mp.psv_axi_cb.b_ready; this.uvma_b_mon_port.write(b_item); + + if(cfg.is_active) begin + // collect b signals + this.bdrv_item.b_id = vif.b_id; + this.bdrv_item.b_resp = vif.b_resp; + this.bdrv_item.b_user = vif.b_user; + this.bdrv_item.b_valid = vif.b_valid; + this.bdrv_item.b_ready = vif.b_ready; + this.uvma_b_mon2drv_port.write(this.bdrv_item); + end @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_sqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_sqr.sv new file mode 100644 index 000000000..ef10e7037 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_sqr.sv @@ -0,0 +1,61 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave sequencer ****/ + +`ifndef __UVMA_AXI_B_SQR_SV__ +`define __UVMA_AXI_B_SQR_SV__ + +class uvma_axi_b_sqr_c extends uvm_sequencer#(uvma_axi_b_item_c); + + `uvm_component_utils(uvma_axi_b_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvm_analysis_export #(uvma_axi_b_item_c) b_resp_export; + uvm_tlm_analysis_fifo #(uvma_axi_aw_item_c) aw_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_w_item_c) w_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_b_item_c) b_resp_fifo; + + function new(string name = "uvma_axi_b_sqr_c", uvm_component parent = null); + + super.new(name, parent); + + this.b_resp_export = new("b_resp_export", this); + this.aw_req_export = new("aw_req_export", this); + this.w_req_export = new("w_req_export", this); + this.b_resp_fifo = new("b_resp_fifo", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + this.b_resp_export.connect(this.b_resp_fifo.analysis_export); // Connect analysis export direct to fifo B channels + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv index e0651e5d9..e904d317f 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_agent.sv @@ -16,9 +16,14 @@ class uvma_axi_r_agent_c extends uvm_agent; uvma_axi_r_mon_c monitor; + uvma_axi_r_sqr_c sequencer; + uvma_axi_r_drv_c driver; + uvma_axi_cfg_c cfg; `uvm_component_utils_begin(uvma_axi_r_agent_c) `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_field_object(sequencer, UVM_ALL_ON) + `uvm_field_object(driver, UVM_ALL_ON) `uvm_component_utils_end function new(string name = "uvma_axi_r_agent_c", uvm_component parent = null); @@ -28,10 +33,30 @@ class uvma_axi_r_agent_c extends uvm_agent; function void build_phase(uvm_phase phase); super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + if( cfg.is_active == UVM_ACTIVE) begin + sequencer = uvma_axi_r_sqr_c::type_id::create("sequencer", this); + driver = uvma_axi_r_drv_c::type_id::create("driver", this); + end monitor = uvma_axi_r_mon_c::type_id::create("monitor", this); endfunction + function void connect_phase(uvm_phase phase); + + super.connect_phase(phase); + //connect sequencer to driver + if( cfg.is_active == UVM_ACTIVE) begin + this.driver.seq_item_port.connect(this.sequencer.seq_item_export); + end + + endfunction + endclass : uvma_axi_r_agent_c `endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_drv.sv new file mode 100644 index 000000000..e08c79f7c --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_drv.sv @@ -0,0 +1,106 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave driver for read ****/ + +`ifndef __UVMA_AXI_R_DRV_SV__ +`define __UVMA_AXI_R_DRV_SV__ + +class uvma_axi_r_drv_c extends uvm_driver #(uvma_axi_r_item_c); + + `uvm_component_utils(uvma_axi_r_drv_c) + + uvma_axi_cntxt_c cntxt; + + uvma_axi_r_item_c r_item; + + // Handles to virtual interface modport + virtual uvma_axi_intf.slave slave_mp; + + extern function new(string name = "uvma_axi_r_drv_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task drv_pre_reset(); + extern task drv_in_reset(); + extern task drv_post_reset(); + +endclass: uvma_axi_r_drv_c + +function uvma_axi_r_drv_c::new(string name = "uvma_axi_r_drv_c", uvm_component parent); + super.new(name, parent); +endfunction + +function void uvma_axi_r_drv_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + if(!uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)) begin + `uvm_fatal("build_phase", "driver cntxt class failed") + end + // uvm_config_db#(uvma_axi_cntxt_c)::set(this, "*", "cntxt", cntxt); + this.slave_mp = this.cntxt.axi_vi.slave; + r_item = uvma_axi_r_item_c::type_id::create("r_item"); + +endfunction + +task uvma_axi_r_drv_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + forever begin + case (cntxt.reset_state) + UVMA_AXI_RESET_STATE_PRE_RESET : drv_pre_reset (); + UVMA_AXI_RESET_STATE_IN_RESET : drv_in_reset (); + UVMA_AXI_RESET_STATE_POST_RESET : drv_post_reset(); + + default: `uvm_fatal("AXI_AR_DRV", $sformatf("Invalid reset_state: %0d", cntxt.reset_state)) + endcase + end + +endtask: run_phase + +task uvma_axi_r_drv_c::drv_pre_reset(); + + this.slave_mp.slv_axi_cb.r_id <= 0; + this.slave_mp.slv_axi_cb.r_resp <= 0; + this.slave_mp.slv_axi_cb.r_user <= 0; + this.slave_mp.slv_axi_cb.r_valid <= 0; + this.slave_mp.slv_axi_cb.r_user <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_pre_reset + +task uvma_axi_r_drv_c::drv_in_reset(); + + this.slave_mp.slv_axi_cb.r_id <= 0; + this.slave_mp.slv_axi_cb.r_resp <= 0; + this.slave_mp.slv_axi_cb.r_user <= 0; + this.slave_mp.slv_axi_cb.r_valid <= 0; + this.slave_mp.slv_axi_cb.r_user <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_in_reset + +task uvma_axi_r_drv_c::drv_post_reset(); + + seq_item_port.get_next_item(r_item); + + `uvm_info(get_type_name(),$sformatf("response, send data to DUT"), UVM_LOW) + this.slave_mp.slv_axi_cb.r_id <= this.r_item.r_id; + this.slave_mp.slv_axi_cb.r_resp <= this.r_item.r_resp; + this.slave_mp.slv_axi_cb.r_user <= this.r_item.r_user; + this.slave_mp.slv_axi_cb.r_last <= this.r_item.r_last; + this.slave_mp.slv_axi_cb.r_valid <= this.r_item.r_valid; + this.slave_mp.slv_axi_cb.r_data <= this.r_item.r_data; + @(slave_mp.slv_axi_cb); + + seq_item_port.item_done(); + +endtask: drv_post_reset + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv index 4d14c2766..14a4ae81e 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv @@ -17,14 +17,18 @@ class uvma_axi_r_mon_c extends uvm_monitor; `uvm_component_utils(uvma_axi_r_mon_c) + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; uvma_axi_r_item_c r_item; + uvma_axi_r_item_c rdrv_item; uvm_analysis_port #(uvma_axi_r_item_c) uvma_r_mon_port; + uvm_analysis_port #(uvma_axi_r_item_c) uvma_r_mon2drv_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; + virtual uvma_axi_intf vif; extern function new(string name = "uvma_axi_r_mon_c", uvm_component parent); extern virtual function void build_phase(uvm_phase phase); @@ -38,6 +42,7 @@ function uvma_axi_r_mon_c::new(string name = "uvma_axi_r_mon_c", uvm_component p super.new(name, parent); uvma_r_mon_port = new("uvma_r_mon_port", this); + uvma_r_mon2drv_port = new("uvma_r_mon2drv_port", this); endfunction @@ -49,9 +54,16 @@ function void uvma_axi_r_mon_c::build_phase(uvm_phase phase); `uvm_fatal("build_phase", "monitor cntxt class failed") end + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + passive_mp = cntxt.axi_vi.passive; + vif = cntxt.axi_vi; this.r_item = uvma_axi_r_item_c::type_id::create("r_item", this); + this.rdrv_item = uvma_axi_r_item_c::type_id::create("rdrv_item", this); endfunction @@ -79,6 +91,18 @@ task uvma_axi_r_mon_c::monitor_r_items(); this.r_item.r_ready = passive_mp.psv_axi_cb.r_ready; this.uvma_r_mon_port.write(r_item); + + if(cfg.is_active) begin + // collect AR signals + this.rdrv_item.r_id = vif.r_id; + this.rdrv_item.r_data = vif.r_data; + this.rdrv_item.r_resp = vif.r_resp; + this.rdrv_item.r_last = vif.r_last; + this.rdrv_item.r_user = vif.r_user; + this.rdrv_item.r_valid = vif.r_valid; + this.rdrv_item.r_ready = vif.r_ready; + this.uvma_r_mon2drv_port.write(this.rdrv_item); + end @(passive_mp.psv_axi_cb); end @@ -95,7 +119,6 @@ task uvma_axi_r_mon_c::observe_reset(); wait (cntxt.axi_vi.rst_n === 1); cntxt.reset_state = UVMA_AXI_RESET_STATE_POST_RESET; `uvm_info(get_type_name(), $sformatf("RESET_STATE_POST_RESET"), UVM_LOW) - end endtask : observe_reset diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_sqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_sqr.sv new file mode 100644 index 000000000..4ae686804 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_sqr.sv @@ -0,0 +1,58 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave sequencer for R channel ****/ + +`ifndef __UVMA_AXI_R_SQR_SV__ +`define __UVMA_AXI_R_SQR_SV__ + +class uvma_axi_r_sqr_c extends uvm_sequencer#(uvma_axi_r_item_c); + + `uvm_component_utils(uvma_axi_r_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvm_analysis_export #(uvma_axi_r_item_c) r_resp_export; + uvm_tlm_analysis_fifo #(uvma_axi_ar_item_c) ar_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_r_item_c) r_resp_fifo; + + function new(string name = "uvma_axi_r_sqr_c", uvm_component parent = null); + super.new(name, parent); + r_resp_export = new("r_resp_export", this); + ar_req_export = new("ar_req_export", this); + r_resp_fifo = new("r_resp_fifo", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + // Connect analysis export direct to fifo AR Channel + this.r_resp_export.connect(this.r_resp_fifo.analysis_export); + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vseq.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vseq.sv new file mode 100644 index 000000000..1f3850bb4 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vseq.sv @@ -0,0 +1,105 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + + +`ifndef __UVMA_AXI_VSEQ_SV__ +`define __UVMA_AXI_VSEQ_SV__ + +class uvma_axi_vseq_c extends uvm_sequence; + + // Environment handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + + `uvm_object_utils(uvma_axi_vseq_c) + `uvm_declare_p_sequencer(uvma_axi_vsqr_c) + + + /** + * Default constructor. + */ + extern function new(string name="uvma_axi_vseq"); + + /** + * Retrieve cfg and cntxt handles from p_sequencer. + */ + extern virtual task pre_start(); + + + extern virtual task body(); + +endclass : uvma_axi_vseq_c + + +function uvma_axi_vseq_c::new(string name="uvma_axi_vseq"); + + super.new(name); + +endfunction : new + + +task uvma_axi_vseq_c::pre_start(); + + cfg = p_sequencer.cfg ; + cntxt = p_sequencer.cntxt; + +endtask : pre_start + +task uvma_axi_vseq_c::body(); + + uvma_axi_fw_preload_seq_c axi_preload_seq; + axi_preload_seq = uvma_axi_fw_preload_seq_c::type_id::create("axi_preload_seq"); + axi_preload_seq.start(p_sequencer.r_sequencer); + fork + begin + if(cfg.is_active == UVM_ACTIVE) begin + uvma_axi_aw_seq_c aw_axi_seq; + aw_axi_seq = uvma_axi_aw_seq_c::type_id::create("aw_axi_seq"); + aw_axi_seq.start(p_sequencer.aw_sequencer); + end + end + + begin + if(cfg.is_active == UVM_ACTIVE) begin + uvma_axi_w_seq_c w_axi_seq; + w_axi_seq = uvma_axi_w_seq_c::type_id::create("w_axi_seq"); + w_axi_seq.start(p_sequencer.w_sequencer); + end + end + + begin + if(cfg.is_active == UVM_ACTIVE) begin + uvma_axi_ar_seq_c ar_axi_seq; + ar_axi_seq = uvma_axi_ar_seq_c::type_id::create("ar_axi_seq"); + ar_axi_seq.start(p_sequencer.ar_sequencer); + end + end + + begin + if(cfg.is_active == UVM_ACTIVE) begin + uvma_axi_r_seq_c r_axi_seq; + r_axi_seq = uvma_axi_r_seq_c::type_id::create("r_axi_seq"); + r_axi_seq.start(p_sequencer.r_sequencer); + end + end + + begin + if(cfg.is_active == UVM_ACTIVE) begin + uvma_axi_b_seq_c b_axi_seq; + b_axi_seq = uvma_axi_b_seq_c::type_id::create("b_axi_seq"); + b_axi_seq.start(p_sequencer.b_sequencer); + end + end + join_none + +endtask : body + +`endif // __uvma_axi_vseq_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vsqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vsqr.sv new file mode 100644 index 000000000..4f76b168e --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vsqr.sv @@ -0,0 +1,51 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave sequencer ****/ + +`ifndef __UVMA_AXI_SQR_SV__ +`define __UVMA_AXI_SQR_SV__ + +class uvma_axi_vsqr_c extends uvm_sequencer; + + `uvm_component_utils(uvma_axi_vsqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_aw_sqr_c aw_sequencer; + uvma_axi_ar_sqr_c ar_sequencer; + uvma_axi_w_sqr_c w_sequencer; + uvma_axi_b_sqr_c b_sequencer; + uvma_axi_r_sqr_c r_sequencer; + + function new(string name = "uvma_axi_vsqr_c", uvm_component parent = null); + super.new(name, parent); + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + endfunction + +endclass + +`endif + diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv index 9ba854017..aac481dfb 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_agent.sv @@ -16,9 +16,14 @@ class uvma_axi_w_agent_c extends uvm_agent; uvma_axi_w_mon_c monitor; + uvma_axi_w_sqr_c sequencer; + uvma_axi_w_drv_c driver; + uvma_axi_cfg_c cfg; `uvm_component_utils_begin(uvma_axi_w_agent_c) `uvm_field_object(monitor, UVM_ALL_ON) + `uvm_field_object(sequencer, UVM_ALL_ON) + `uvm_field_object(driver, UVM_ALL_ON) `uvm_component_utils_end function new(string name = "uvma_axi_w_agent_c", uvm_component parent = null); @@ -27,11 +32,32 @@ class uvma_axi_w_agent_c extends uvm_agent; function void build_phase(uvm_phase phase); + `uvm_info(get_type_name(), $sformatf("write address, 1"), UVM_HIGH) super.build_phase(phase); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + if( cfg.is_active == UVM_ACTIVE) begin + this.sequencer = uvma_axi_w_sqr_c::type_id::create("sequencer", this); + this.driver = uvma_axi_w_drv_c::type_id::create("driver", this); + end this.monitor = uvma_axi_w_mon_c::type_id::create("monitor", this); endfunction + function void connect_phase(uvm_phase phase); + + super.connect_phase(phase); + //connect sequencer to driver + if( cfg.is_active == UVM_ACTIVE) begin + driver.seq_item_port.connect(sequencer.seq_item_export); + end + + endfunction + endclass `endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv new file mode 100644 index 000000000..1b205d39d --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv @@ -0,0 +1,103 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +/**** AXI4 slave W channel driver ****/ + +`ifndef __UVMA_AXI_W_DRV_SV__ +`define __UVMA_AXI_W_DRV_SV__ + +class uvma_axi_w_drv_c extends uvm_driver #(uvma_axi_w_item_c); + + `uvm_component_utils(uvma_axi_w_drv_c) + + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_w_item_c w_item; + + // Handles to virtual interface modport + virtual uvma_axi_intf.slave slave_mp; + + extern function new(string name = "uvma_axi_w_drv_c", uvm_component parent); + extern virtual function void build_phase(uvm_phase phase); + extern virtual task run_phase(uvm_phase phase); + extern task drv_pre_reset(); + extern task drv_in_reset(); + extern task drv_post_reset(); + +endclass:uvma_axi_w_drv_c + +function uvma_axi_w_drv_c::new(string name = "uvma_axi_w_drv_c", uvm_component parent); + super.new(name, parent); +endfunction + +function void uvma_axi_w_drv_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + if(!uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)) begin + `uvm_fatal("build_phase", "w_driver cntxt class failed") + end + + this.slave_mp = this.cntxt.axi_vi.slave; + + w_item = uvma_axi_w_item_c::type_id::create("w_item", this); + + // get cfg handle to driver + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + +endfunction + +task uvma_axi_w_drv_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + forever begin + + case (cntxt.reset_state) + UVMA_AXI_RESET_STATE_PRE_RESET : drv_pre_reset (); + UVMA_AXI_RESET_STATE_IN_RESET : drv_in_reset (); + UVMA_AXI_RESET_STATE_POST_RESET : drv_post_reset(); + + default: `uvm_fatal("AXI_w_DRV", $sformatf("Invalid reset_state: %0d", cntxt.reset_state)) + endcase + + end + +endtask: run_phase + +task uvma_axi_w_drv_c::drv_pre_reset(); + + this.slave_mp.slv_axi_cb.w_ready <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_pre_reset + +task uvma_axi_w_drv_c::drv_in_reset(); + + this.slave_mp.slv_axi_cb.w_ready <= 0; + @(slave_mp.slv_axi_cb); + +endtask: drv_in_reset + +task uvma_axi_w_drv_c::drv_post_reset(); + + seq_item_port.get_next_item(w_item); + `uvm_info(get_type_name(), $sformatf("write data driver start"), UVM_LOW) + this.slave_mp.slv_axi_cb.w_ready <= 1'b1; + @(slave_mp.slv_axi_cb); + seq_item_port.item_done(); + +endtask: drv_post_reset + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv index eb1fb3c4c..4ee256077 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv @@ -17,14 +17,18 @@ class uvma_axi_w_mon_c extends uvm_monitor; `uvm_component_utils(uvma_axi_w_mon_c) + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; uvma_axi_w_item_c w_item; + uvma_axi_w_item_c wdrv_item; uvm_analysis_port #(uvma_axi_w_item_c) uvma_w_mon_port; + uvm_analysis_port #(uvma_axi_w_item_c) uvma_w_mon2drv_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; + virtual uvma_axi_intf vif; extern function new(string name = "uvma_axi_w_mon_c", uvm_component parent); extern virtual function void build_phase(uvm_phase phase); @@ -37,6 +41,7 @@ function uvma_axi_w_mon_c::new(string name = "uvma_axi_w_mon_c", uvm_component p super.new(name, parent); uvma_w_mon_port = new("uvma_w_mon_port", this); + uvma_w_mon2drv_port = new("uvma_w_mon2drv_port", this); endfunction @@ -50,8 +55,15 @@ function void uvma_axi_w_mon_c::build_phase(uvm_phase phase); end passive_mp = cntxt.axi_vi.passive; + vif = cntxt.axi_vi; w_item = uvma_axi_w_item_c::type_id::create("w_item", this); + wdrv_item = uvma_axi_w_item_c::type_id::create("wdrv_item", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end endfunction @@ -70,6 +82,16 @@ task uvma_axi_w_mon_c::monitor_w_items(); w_item.w_user = passive_mp.psv_axi_cb.w_user; w_item.w_valid = passive_mp.psv_axi_cb.w_valid; w_item.w_ready = passive_mp.psv_axi_cb.w_ready; + if(cfg.is_active) begin + // collect AR signals + this.wdrv_item.w_strb = vif.w_strb; + this.wdrv_item.w_data = vif.w_data; + this.wdrv_item.w_last = vif.w_last; + this.wdrv_item.w_user = vif.w_user; + this.wdrv_item.w_valid = vif.w_valid; + this.wdrv_item.w_ready = vif.w_ready; + this.uvma_w_mon2drv_port.write(this.wdrv_item); + end this.uvma_w_mon_port.write(this.w_item); @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_sqr.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_sqr.sv new file mode 100644 index 000000000..0c9589b61 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_sqr.sv @@ -0,0 +1,58 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +/**** AXI4 master sequencer ****/ + +`ifndef __UVMA_AXI_W_SQR_SV__ +`define __UVMA_AXI_W_SQR_SV__ + +class uvma_axi_w_sqr_c extends uvm_sequencer#(uvma_axi_w_item_c); + + `uvm_component_utils(uvma_axi_w_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvm_analysis_export #(uvma_axi_w_item_c) w_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_aw_item_c) aw_req_export; + uvm_tlm_analysis_fifo #(uvma_axi_w_item_c) w_req_fifo; + + function new(string name = "uvma_axi_w_sqr_c", uvm_component parent = null); + + super.new(name, parent); + + this.w_req_export = new("w_req_export", this); + this.aw_req_export = new("aw_req_export", this); + this.w_req_fifo = new("w_req_fifo", this); + + void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_axi_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + endfunction + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + this.w_req_export.connect(this.w_req_fifo.analysis_export); // Connect analysis export direct to fifo w channels + endfunction + +endclass + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv new file mode 100644 index 000000000..0f4e6ac16 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv @@ -0,0 +1,39 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + + +`ifndef __UVMA_AXI_CFG_SV__ +`define __UVMA_AXI_CFG_SV__ + +class uvma_axi_cfg_c extends uvm_object; + + rand uvm_active_passive_enum is_active; + + + `uvm_object_utils_begin(uvma_axi_cfg_c) + `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT); + `uvm_object_utils_end + + constraint defaults_config { + soft is_active == UVM_ACTIVE; + } + + extern function new(string name = "uvma_axi_cfg"); + +endclass : uvma_axi_cfg_c + + +function uvma_axi_cfg_c::new(string name = "uvma_axi_cfg"); + + super.new(name); + +endfunction : new + +`endif //__UVMA_AXI_CFG_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv index b11bbbb04..a1dba6b06 100644 --- a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv +++ b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cntxt.sv @@ -20,6 +20,9 @@ class uvma_axi_cntxt_c extends uvm_object; // Handle to agent interface virtual uvma_axi_intf axi_vi; + // Handle to memory storage for active slaves + uvml_mem_c mem; + uvma_axi_reset_state_enum reset_state = UVMA_AXI_RESET_STATE_PRE_RESET; `uvm_object_utils_begin(uvma_axi_cntxt_c) @@ -36,6 +39,7 @@ endclass : uvma_axi_cntxt_c function uvma_axi_cntxt_c::new(string name = "uvma_axi_cntxt"); super.new(name); + mem = uvml_mem_c#(64)::type_id::create("mem"); endfunction : new diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv new file mode 100644 index 000000000..d4fa0c652 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv @@ -0,0 +1,54 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +//============================================================================= +// Description: Sequence for agent axi_ar +//============================================================================= + +`ifndef UVMA_AXI_AR_SEQ_SV +`define UVMA_AXI_AR_SEQ_SV + +class uvma_axi_ar_seq_c extends uvm_sequence#(uvma_axi_ar_item_c); + + `uvm_object_utils(uvma_axi_ar_seq_c) + `uvm_declare_p_sequencer(uvma_axi_ar_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + uvma_axi_ar_item_c req_item; + + extern function new(string name = ""); + extern task body(); + +endclass : uvma_axi_ar_seq_c + + +function uvma_axi_ar_seq_c::new(string name = ""); + super.new(name); +endfunction : new + +task uvma_axi_ar_seq_c::body(); + forever begin + cfg = p_sequencer.cfg; + cntxt = p_sequencer.cntxt; + + req_item = uvma_axi_ar_item_c::type_id::create("req_item"); + p_sequencer.ar_req_fifo.get(req_item); + + start_item(req_item); + `uvm_info(get_type_name(), "READ ADDRESS sequence starting", UVM_LOW) + finish_item(req_item); + end + `uvm_info(get_type_name(), "Default sequence completed", UVM_LOW) + +endtask : body + +`endif + diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv new file mode 100644 index 000000000..04a0e6257 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv @@ -0,0 +1,56 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +//============================================================================= +// Description: Sequence for agent axi_aw +//============================================================================= + +`ifndef UVMA_AXI_AW_SEQ_SV +`define UVMA_AXI_AW_SEQ_SV + +class uvma_axi_aw_seq_c extends uvm_sequence#(uvma_axi_aw_item_c); + + `uvm_object_utils(uvma_axi_aw_seq_c) + `uvm_declare_p_sequencer(uvma_axi_aw_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_aw_item_c req_item; + + extern function new(string name = ""); + extern task body(); + +endclass : uvma_axi_aw_seq_c + + +function uvma_axi_aw_seq_c::new(string name = ""); + super.new(name); +endfunction : new + +task uvma_axi_aw_seq_c::body(); + forever begin + cfg = p_sequencer.cfg ; + cntxt = p_sequencer.cntxt; + + req_item = uvma_axi_aw_item_c::type_id::create("req_item"); + p_sequencer.aw_req_fifo.get(req_item); + + start_item(req_item); + `uvm_info(get_type_name(), "WRITE ADDRESS sequence starting", UVM_LOW) + finish_item(req_item); + + end + `uvm_info(get_type_name(), "Default sequence completed", UVM_LOW) + +endtask : body + +`endif + diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv new file mode 100644 index 000000000..8edb9d0fc --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv @@ -0,0 +1,187 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + + +//============================================================================= +// Description: Sequence for agent axi_b +//============================================================================= + +`ifndef UVMA_AXI_B_SEQ_SV +`define UVMA_AXI_B_SEQ_SV + +class uvma_axi_b_seq_c extends uvm_sequence#(uvma_axi_b_item_c); + + `uvm_object_utils(uvma_axi_b_seq_c) + `uvm_declare_p_sequencer(uvma_axi_b_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_b_item_c b_resp_item; + uvma_axi_b_item_c b_preresp_item; + uvma_axi_aw_item_c aw_req_item; + uvma_axi_aw_item_c req_requette[][]; + uvma_axi_w_item_c w_req_item; + + int aw_id_tr[]; + int req_status[][]; + int status[]; + int first_req = 0; + int selected_id; + int enable_change_id = 1; + + extern function new(string name = ""); + extern function void create_item(); + extern task body(); + extern function int check_tab(int tab[]); + +endclass : uvma_axi_b_seq_c + +function uvma_axi_b_seq_c::new(string name = ""); + super.new(name); +endfunction : new + +function void uvma_axi_b_seq_c::create_item(); + + b_resp_item = uvma_axi_b_item_c::type_id::create("b_resp_item"); + b_preresp_item = uvma_axi_b_item_c::type_id::create("b_preresp_item"); + aw_req_item = uvma_axi_aw_item_c::type_id::create("aw_req_item"); + w_req_item = uvma_axi_w_item_c::type_id::create("w_req_item"); + +endfunction : create_item + +task uvma_axi_b_seq_c::body(); + + create_item(); + + forever begin + + cfg = p_sequencer.cfg ; + cntxt = p_sequencer.cntxt; + + `uvm_info(get_type_name(), "WRITE RESPONSE sequence starting", UVM_LOW) + + p_sequencer.aw_req_export.get(aw_req_item); + p_sequencer.w_req_export.get(w_req_item); + p_sequencer.b_resp_fifo.get(b_preresp_item); + + start_item(b_resp_item); + + if(aw_req_item.aw_valid && aw_req_item.aw_ready) begin + + `uvm_info(get_type_name(), "read request registere", UVM_HIGH) + if(aw_req_item.aw_id >= aw_id_tr.size()) begin + + aw_id_tr = new[aw_req_item.aw_id+1] (aw_id_tr); + aw_id_tr[aw_req_item.aw_id] = 1; + req_requette = new[aw_req_item.aw_id + 1] (req_requette); + req_requette[aw_req_item.aw_id] = new[1]; + req_requette[aw_req_item.aw_id][0] = new aw_req_item; + + end else begin + + aw_id_tr[aw_req_item.aw_id]++; + req_requette[aw_req_item.aw_id] = new[aw_id_tr[aw_req_item.aw_id]] (req_requette[aw_req_item.aw_id]); + req_requette[aw_req_item.aw_id][aw_id_tr[aw_req_item.aw_id] - 1] = new aw_req_item; + + end + + req_status = new[req_status.size() + 1] (req_status); + req_status[req_status.size() - 1] = new[aw_req_item.aw_id + 1]; + req_status[req_status.size() - 1][aw_req_item.aw_id] = 1; + + `uvm_info(get_type_name(), "read request registred", UVM_HIGH) + end + + if((w_req_item.w_valid && w_req_item.w_ready && w_req_item.w_last) || (first_req == 1)) begin + + `uvm_info(get_type_name(), "write data registred", UVM_HIGH) + if(req_status.size() != 0) begin + + foreach(req_status[i,j]) begin + + if(req_status[0][j] == 1) begin + status = new[status.size() + 1] (status); + status[status.size() - 1] = j; + end + + end + + foreach(req_status[i,j]) begin + if(i < req_status.size()-1) begin + req_status[i] = req_status[i+1]; + end + end + req_status = new[req_status.size() - 1] (req_status); + first_req = 0; + + end else begin + first_req = 1; + end + `uvm_info(get_type_name(), "write data registred", UVM_HIGH) + end + + + if(enable_change_id == 1) begin + selected_id = check_tab(status); + end + + `uvm_info(get_type_name(), $sformatf("selected id = %d", selected_id), UVM_HIGH) + + if(selected_id != -1) begin + `uvm_info(get_type_name(), "send resp", UVM_HIGH) + + b_resp_item.b_id = req_requette[selected_id][0].aw_id; + b_resp_item.b_resp = 0; + b_resp_item.b_valid = 1; + b_resp_item.b_user = 0; + + if(b_preresp_item.b_ready) begin + + foreach(req_requette[i,j]) begin + req_requette[selected_id][j] = req_requette[selected_id][j+1]; + end + req_requette[selected_id] = new[aw_id_tr[selected_id] - 1] (req_requette[selected_id]); + aw_id_tr[selected_id]--; + + foreach(status[i]) begin + status[i] = status[i+1]; + end + status = new[status.size() - 1] (status); + + enable_change_id = 1; + end else begin + enable_change_id = 0; + end + + end else begin + + `uvm_info(get_type_name(), " No resp to send ", UVM_HIGH) + b_resp_item.b_valid = 0; + b_resp_item.b_id = 0; + b_resp_item.b_resp = 0; + b_resp_item.b_user = 0; + + end + + finish_item(b_resp_item); + `uvm_info(get_type_name(), "Default sequence completed", UVM_LOW) + end +endtask : body + +function int uvma_axi_b_seq_c::check_tab(int tab[]); + int j = -1; + if (status.size() != 0) begin + j = status[0]; + end + return j; +endfunction : check_tab + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_fw_preload_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_fw_preload_seq.sv new file mode 100644 index 000000000..8710bba08 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_fw_preload_seq.sv @@ -0,0 +1,91 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + + +`ifndef __UVMA_AXI_FW_PRELOAD_SEQ_SV__ +`define __UVMA_AXI_FW_PRELOAD_SEQ_SV__ + + +/** + * Virtual sequence implementing the cv32e40x virtual peripherals. + * TODO Move most of the functionality to a cv32e env base class. + */ +class uvma_axi_fw_preload_seq_c extends uvm_sequence; + + static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvml_mem_c mem; + + bit[63:0] value; + logic [7:0][7:0] mem_row; + string binary = ""; + longint address; + longint len; + byte buffer[]; + + `uvm_object_utils(uvma_axi_fw_preload_seq_c) + `uvm_declare_p_sequencer(uvma_axi_r_sqr_c) + + /** + * Default constructor. + */ + extern function new(string name="uvma_axi_fw_preload_seq"); + + + extern virtual task body(); + +endclass : uvma_axi_fw_preload_seq_c + +function uvma_axi_fw_preload_seq_c::new(string name="uvma_axi_fw_preload_seq"); + + super.new(name); + mem = uvml_mem_c::type_id::create("mem"); + +endfunction : new + +task uvma_axi_fw_preload_seq_c::body(); + + cfg = p_sequencer.cfg ; + void'(uvcl.get_arg_value("+PRELOAD=", binary)); + + if (binary != "") begin + void'(read_elf(binary)); + wait(p_sequencer.cntxt.axi_vi.clk); + // while there are more sections to process + while (get_section(address, len)) begin + automatic int num_words0 = (len+7)/8; + `uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len), UVM_HIGH) + buffer = new [num_words0*8]; + void'(read_section(address, buffer)); + // preload memories + // 64-bit + for (int i = 0; i < num_words0; i++) begin + mem_row = '0; + for (int j = 0; j < 8; j++) begin + mem_row[j] = buffer[i*8 + j]; + end + mem.write(address + i*8 + 0, mem_row[0]); + mem.write(address + i*8 + 1, mem_row[1]); + mem.write(address + i*8 + 2, mem_row[2]); + mem.write(address + i*8 + 3, mem_row[3]); + mem.write(address + i*8 + 4, mem_row[4]); + mem.write(address + i*8 + 5, mem_row[5]); + mem.write(address + i*8 + 6, mem_row[6]); + mem.write(address + i*8 + 7, mem_row[7]); + end + p_sequencer.cntxt.mem = mem; + end + end + +endtask : body + +`endif // __UVMA_AXI_FW_PRELOAD_SEQ_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv new file mode 100644 index 000000000..2cf7563ca --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv @@ -0,0 +1,213 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +//============================================================================= +// Description: Sequence for agent axi_r +//============================================================================= + +`ifndef UVMA_AXI_R_SEQ_SV +`define UVMA_AXI_R_SEQ_SV + +class uvma_axi_r_seq_c extends uvm_sequence#(uvma_axi_r_item_c); + + + int i = 0; + + `uvm_object_utils(uvma_axi_r_seq_c) + `uvm_declare_p_sequencer(uvma_axi_r_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_r_item_c resp_item; + uvma_axi_r_item_c pre_resp; + uvma_axi_ar_item_c req_item; + uvma_axi_ar_item_c req_requette[][]; + + int selected_id; + int ar_id_tr[]; + int enable_change_id = 1; + bit[1:0] inject_error; + int selected_indice = 0; + int status[]; + int r_latency; + + + extern function new(string name = ""); + extern function void create_item(); + extern task body(); + extern function int check_tab(int tab[]); + extern function void prepare_resp(uvma_axi_ar_item_c req_item, uvma_axi_r_item_c resp_item, int error); + extern function int select_first_id(int tab[], int id); + +endclass : uvma_axi_r_seq_c + +function uvma_axi_r_seq_c::new(string name = ""); + + super.new(name); + +endfunction : new + +function void uvma_axi_r_seq_c::create_item(); + + resp_item = uvma_axi_r_item_c::type_id::create("resp_item"); + pre_resp = uvma_axi_r_item_c::type_id::create("pre_resp"); + req_item = uvma_axi_ar_item_c::type_id::create("req_item"); + +endfunction : create_item + +task uvma_axi_r_seq_c::body(); + + create_item(); + + forever begin + + cfg = p_sequencer.cfg ; + cntxt = p_sequencer.cntxt; + + `uvm_info(get_type_name(), "READ DATA sequence starting", UVM_LOW) + + p_sequencer.ar_req_export.get(req_item); + p_sequencer.r_resp_fifo.get(pre_resp); + + start_item(resp_item); + + if(req_item.ar_valid && req_item.ar_ready) begin + + `uvm_info(get_type_name(), "Read request registere", UVM_LOW) + if(req_item.ar_id >= ar_id_tr.size()) begin + + ar_id_tr = new[req_item.ar_id+1] (ar_id_tr); + ar_id_tr[req_item.ar_id] = 1; + req_requette = new[req_item.ar_id + 1] (req_requette); + req_requette[req_item.ar_id] = new[1]; + req_requette[req_item.ar_id][0] = new req_item; + + end else begin + + ar_id_tr[req_item.ar_id]++; + req_requette[req_item.ar_id] = new[ar_id_tr[req_item.ar_id]] (req_requette[req_item.ar_id]); + req_requette[req_item.ar_id][ar_id_tr[req_item.ar_id] - 1] = new req_item; + + end + `uvm_info(get_type_name(), "Read request registred", UVM_LOW) + status = new[status.size() + 1] (status); + status[status.size() - 1] = req_item.ar_id; + end + + if(enable_change_id == 1) begin + selected_id = check_tab(status); + r_latency = -1; + end + + `uvm_info(get_type_name(), $sformatf("r_ready id = %d || LATENCY = %d",pre_resp.r_ready, r_latency), UVM_LOW) + if(r_latency > -1 && pre_resp.r_ready && selected_id != -1) begin + + `uvm_info(get_type_name(), "transfert termine", UVM_LOW) + if(ar_id_tr[selected_id] > 0) begin + if(resp_item.r_last == 1'b1) begin + + foreach(req_requette[i,j]) begin + req_requette[selected_id][j] = req_requette[selected_id][j+1]; + end + req_requette[selected_id] = new[ar_id_tr[selected_id] - 1] (req_requette[selected_id]); + + ar_id_tr[selected_id]--; + + selected_indice = select_first_id(status, selected_id); + foreach(status[j]) begin + status[selected_indice + j] = status[selected_indice + j + 1]; + end + status = new[status.size() - 1] (status); + + end + end + + selected_id = check_tab(status); + inject_error = 1'b0; + r_latency = -1; + + if(selected_id == -1) begin + enable_change_id = 1; + end else begin + enable_change_id = 0; + end + + end + + `uvm_info(get_type_name(), $sformatf("selected id = %d || LATENCY = %d",selected_id, r_latency), UVM_LOW) + + if(selected_id != -1) begin + if(r_latency == -1) begin + + `uvm_info(get_type_name(), "read item", UVM_LOW) + prepare_resp(req_requette[selected_id][0], resp_item, inject_error); + if(req_requette[selected_id][0].ar_len == 0) begin + `uvm_info(get_type_name()," last will be asserted ",UVM_HIGH) + resp_item.r_last = 1'b1; + end else begin + req_requette[selected_id][0].ar_len--; + resp_item.r_last = 1'b0; + req_requette[selected_id][0].ar_addr = req_requette[selected_id][0].ar_addr + 2**req_requette[selected_id][0].ar_size; + end + enable_change_id = 0; + + end + r_latency++; + end else begin + resp_item.r_id = 0; + resp_item.r_data = 0; + resp_item.r_resp = 0; + resp_item.r_valid = 1'b0; + resp_item.r_user = 1'b0; + resp_item.r_last = 1'b0; + end + + finish_item(resp_item); + end + `uvm_info(get_type_name(), "Default sequence completed", UVM_LOW) + +endtask : body + +function void uvma_axi_r_seq_c::prepare_resp(uvma_axi_ar_item_c req_item, uvma_axi_r_item_c resp_item, int error); + + resp_item.r_id = req_item.ar_id; + for(int i = 0; i < 2**req_item.ar_size; i++) begin + resp_item.r_data [((i+1)*8-1)-:8] = cntxt.mem.read(req_item.ar_addr + i); + if($isunknown(resp_item.r_data[((i+1)*8-1)-:8])) begin + resp_item.r_data[((i+1)*8-1)-:8] = 2'h00; + end + end + resp_item.r_resp = error; + resp_item.r_valid = 1'b1; + resp_item.r_user = 1'b0; + +endfunction : prepare_resp + +function int uvma_axi_r_seq_c::check_tab(int tab[]); + int j = -1; + if (status.size() != 0) begin + j = status[0]; + end + return j; +endfunction : check_tab + +function int uvma_axi_r_seq_c::select_first_id(int tab[], int id); + int j = -1; + foreach(tab[i]) begin + if(tab[i] == id) begin + j = i; + return j; + end + end + return j; +endfunction : select_first_id + +`endif diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_seq_lib.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_seq_lib.sv new file mode 100644 index 000000000..706ae2491 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_seq_lib.sv @@ -0,0 +1,47 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + + +`ifndef __UVMA_AXI_SEQ_LIB_SV__ +`define __UVMA_AXI_SEQ_LIB_SV__ + + +`include "uvma_axi_fw_preload_seq.sv" +`include "uvma_axi_ar_seq.sv" +`include "uvma_axi_aw_seq.sv" +`include "uvma_axi_w_seq.sv" +`include "uvma_axi_r_seq.sv" +`include "uvma_axi_b_seq.sv" +`include "uvma_axi_vseq.sv" + +/** + * Object holding sequence library for Open Bus Interface agent. + */ +class uvma_axi_seq_lib_c extends uvm_sequence_library; + + `uvm_object_utils (uvma_axi_seq_lib_c) + `uvm_sequence_library_utils(uvma_axi_seq_lib_c) + + /** + * Initializes sequence library + */ + extern function new(string name="uvma_axi_seq_lib"); + +endclass : uvma_axi_seq_lib_c + + +function uvma_axi_seq_lib_c::new(string name="uvma_axi_seq_lib"); + + super.new(name); + init_sequence_library(); + +endfunction : new + +`endif // __UVMA_AXI_SEQ_LIB_SV__ + diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv new file mode 100644 index 000000000..e5c9489c7 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv @@ -0,0 +1,145 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +//============================================================================= +// Description: Sequence for agent axi_w +//============================================================================= + +`ifndef UVMA_AXI_W_SEQ_SV +`define UVMA_AXI_W_SEQ_SV + +class uvma_axi_w_seq_c extends uvm_sequence#(uvma_axi_w_item_c); + + `uvm_object_utils(uvma_axi_w_seq_c) + `uvm_declare_p_sequencer(uvma_axi_w_sqr_c) + + // Agent handles + uvma_axi_cfg_c cfg; + uvma_axi_cntxt_c cntxt; + + uvma_axi_aw_item_c aw_req_item; + uvma_axi_aw_item_c req_requette[]; + uvma_axi_w_item_c write_data_req[]; + uvma_axi_w_item_c w_req_item; + + int latency; + int w_ready_latency; + int status = 0; + bit write_status = 0; + int check_ready = 0; + int aw_latency[]; + + extern function new(string name = ""); + extern function void add_latencies(uvma_axi_w_item_c master_req); + extern task body(); + +endclass : uvma_axi_w_seq_c + + +function uvma_axi_w_seq_c::new(string name = ""); + super.new(name); +endfunction : new + +task uvma_axi_w_seq_c::body(); + + aw_req_item = uvma_axi_aw_item_c::type_id::create("aw_req_item"); + w_req_item = uvma_axi_w_item_c::type_id::create("w_req_item"); + + forever begin + + cfg = p_sequencer.cfg; + cntxt = p_sequencer.cntxt; + + `uvm_info(get_type_name(), "WRITE DATA sequence starting", UVM_LOW) + + p_sequencer.aw_req_export.get(aw_req_item); + p_sequencer.w_req_fifo.get(w_req_item); + + if(aw_req_item.aw_valid || check_ready == 1) begin + + if(aw_req_item.aw_valid) begin + req_requette = new[req_requette.size() + 1] (req_requette); + req_requette[req_requette.size() - 1] = new aw_req_item; + end + + if(!check_ready) begin + aw_latency = new[aw_latency.size() + 1] (aw_latency); + aw_latency[aw_latency.size() - 1] = -2; + end + + aw_latency[aw_latency.size() - 1]++; + check_ready = 1; + + if(aw_req_item.aw_ready && aw_latency[aw_latency.size() - 1] != -1) begin + check_ready = 0; + status = 1; + if(aw_req_item.aw_valid) begin + check_ready = 1; + aw_latency = new[aw_latency.size() + 1] (aw_latency); + aw_latency[aw_latency.size() - 1] = -1; + end + end + end + + start_item(w_req_item); + `uvm_info(get_type_name(), $sformatf("req_requette size = %d", req_requette.size()), UVM_LOW) + if(w_req_item.w_valid) begin + + write_data_req = new[write_data_req.size() + 1] (write_data_req); + write_data_req[write_data_req.size() - 1] = new w_req_item; + write_status = 1; + + end + + `uvm_info(get_type_name(), $sformatf("status = %d et write_status = %d", status, write_status), UVM_LOW) + if(status == 1 && write_status == 1) begin + + longint aligned_addr; + `uvm_info(get_type_name(), $sformatf("AXI_ADDR_WIDTH = %d et AXI_ADDR_WIDTH_BYTE = %d", AXI_ADDR_WIDTH, AXI_ADDR_WIDTH/8), UVM_LOW) + aligned_addr = req_requette[0].aw_addr - req_requette[0].aw_addr % (AXI_ADDR_WIDTH/8); + if(write_data_req[0].w_strb[0]) cntxt.mem.write(aligned_addr+0, write_data_req[0].w_data[07:00]); + if(write_data_req[0].w_strb[1]) cntxt.mem.write(aligned_addr+1, write_data_req[0].w_data[15:08]); + if(write_data_req[0].w_strb[2]) cntxt.mem.write(aligned_addr+2, write_data_req[0].w_data[23:16]); + if(write_data_req[0].w_strb[3]) cntxt.mem.write(aligned_addr+3, write_data_req[0].w_data[31:24]); + if(write_data_req[0].w_strb[4]) cntxt.mem.write(aligned_addr+4, write_data_req[0].w_data[39:32]); + if(write_data_req[0].w_strb[5]) cntxt.mem.write(aligned_addr+5, write_data_req[0].w_data[47:40]); + if(write_data_req[0].w_strb[6]) cntxt.mem.write(aligned_addr+6, write_data_req[0].w_data[55:48]); + if(write_data_req[0].w_strb[7]) cntxt.mem.write(aligned_addr+7, write_data_req[0].w_data[63:56]); + + if(write_data_req[0].w_last) begin + foreach(req_requette[i]) begin + req_requette[i] = req_requette[(i + aw_latency[0]) +1]; + end + req_requette = new[req_requette.size() - (1 + aw_latency[0])] (req_requette); + + foreach(aw_latency[i]) begin + aw_latency[i] = aw_latency[i + 1]; + end + aw_latency = new[aw_latency.size() - 1] (aw_latency); + + status =0; + end + + foreach(write_data_req[i]) begin + write_data_req[i] = write_data_req[i+1]; + end + write_data_req = new[write_data_req.size() - 1] (write_data_req); + if(write_data_req.size() == 0) begin + write_status =0; + end + + end + finish_item(w_req_item); + end + `uvm_info(get_type_name(), "Write data sequence completed", UVM_LOW) + +endtask : body + +`endif + diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv index ddcd92d1d..b06dc1b7b 100644 --- a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv @@ -24,6 +24,10 @@ package uvma_axi_pkg; import uvm_pkg::*; + import uvml_mem_pkg ::*; + import "DPI-C" function read_elf(input string filename); + import "DPI-C" function byte get_section(output longint address, output longint len); + import "DPI-C" context function void read_section(input longint address, inout byte buffer[]); localparam NrSlaves = 2; // actually masters, but slaves on the crossbar localparam IdWidth = 4; // 4 is recommended by AXI standard, so lets stick to it, do not change @@ -37,6 +41,7 @@ package uvma_axi_pkg; `include "uvma_axi_tdefs.sv" // Objects + `include "uvma_axi_cfg.sv" `include "uvma_axi_cntxt.sv" `include "uvma_axi_aw_item.sv" @@ -45,12 +50,22 @@ package uvma_axi_pkg; `include "uvma_axi_ar_item.sv" `include "uvma_axi_r_item.sv" + `include "uvma_axi_aw_drv.sv" + `include "uvma_axi_w_drv.sv" + `include "uvma_axi_b_drv.sv" + `include "uvma_axi_ar_drv.sv" + `include "uvma_axi_r_drv.sv" `include "uvma_axi_aw_mon.sv" `include "uvma_axi_w_mon.sv" `include "uvma_axi_b_mon.sv" `include "uvma_axi_ar_mon.sv" `include "uvma_axi_r_mon.sv" + `include "uvma_axi_aw_sqr.sv" + `include "uvma_axi_w_sqr.sv" + `include "uvma_axi_b_sqr.sv" + `include "uvma_axi_ar_sqr.sv" + `include "uvma_axi_r_sqr.sv" `include "uvma_axi_aw_agent.sv" `include "uvma_axi_w_agent.sv" @@ -58,7 +73,11 @@ package uvma_axi_pkg; `include "uvma_axi_ar_agent.sv" `include "uvma_axi_r_agent.sv" + `include "uvma_axi_vsqr.sv" + `include "uvma_axi_agent.sv" + // Sequences + `include "uvma_axi_seq_lib.sv" endpackage : uvma_axi_pkg From 305de5f168059735896cd2a487d6f587c6c3199c Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 7 Dec 2022 17:34:44 +0100 Subject: [PATCH 039/183] axi_agent: connect the axi agent to CVA6 in order to make the agent work in active mode Signed-off-by: Alae Eddine Ez zejjari --- cva6/env/uvme/uvme_cva6_cfg.sv | 5 + cva6/env/uvme/uvme_cva6_cntxt.sv | 8 ++ cva6/env/uvme/uvme_cva6_env.sv | 15 +++ cva6/env/uvme/uvme_cva6_pkg.sv | 1 + cva6/env/uvme/uvme_cva6_vsqr.sv | 1 + cva6/sim/Makefile | 1 + cva6/tb/uvmt/cva6_tb_wrapper.sv | 178 +++++++++---------------------- cva6/tb/uvmt/uvmt_cva6.flist | 1 + 8 files changed, 81 insertions(+), 129 deletions(-) diff --git a/cva6/env/uvme/uvme_cva6_cfg.sv b/cva6/env/uvme/uvme_cva6_cfg.sv index 24da1779d..6065c43e8 100644 --- a/cva6/env/uvme/uvme_cva6_cfg.sv +++ b/cva6/env/uvme/uvme_cva6_cfg.sv @@ -40,6 +40,7 @@ class uvme_cva6_cfg_c extends uvm_object; // Agent cfg handles rand uvma_clknrst_cfg_c clknrst_cfg; rand uvma_cvxif_cfg_c cvxif_cfg; + rand uvma_axi_cfg_c axi_cfg; `uvm_object_utils_begin(uvme_cva6_cfg_c) `uvm_field_int ( enabled , UVM_DEFAULT ) @@ -53,6 +54,8 @@ class uvme_cva6_cfg_c extends uvm_object; `uvm_field_object(cvxif_cfg, UVM_DEFAULT) + `uvm_field_object(axi_cfg, UVM_DEFAULT) + `uvm_object_utils_end @@ -71,6 +74,7 @@ class uvme_cva6_cfg_c extends uvm_object; } if (is_active == UVM_ACTIVE) { clknrst_cfg.is_active == UVM_ACTIVE; + axi_cfg.is_active == UVM_ACTIVE; } if (trn_log_enabled) { @@ -97,6 +101,7 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg"); clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); cvxif_cfg = uvma_cvxif_cfg_c::type_id::create("cvxif_cfg"); + axi_cfg = uvma_axi_cfg_c::type_id::create("axi_cfg"); endfunction : new diff --git a/cva6/env/uvme/uvme_cva6_cntxt.sv b/cva6/env/uvme/uvme_cva6_cntxt.sv index 7973f1869..5a4433661 100644 --- a/cva6/env/uvme/uvme_cva6_cntxt.sv +++ b/cva6/env/uvme/uvme_cva6_cntxt.sv @@ -32,6 +32,9 @@ class uvme_cva6_cntxt_c extends uvm_object; uvma_cvxif_cntxt_c cvxif_cntxt; uvma_axi_cntxt_c axi_cntxt; +// Memory modelling + rand uvml_mem_c mem; + // Events uvm_event sample_cfg_e; uvm_event sample_cntxt_e; @@ -42,8 +45,12 @@ class uvme_cva6_cntxt_c extends uvm_object; `uvm_field_object(axi_cntxt, UVM_DEFAULT) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) + `uvm_field_object(mem, UVM_DEFAULT) `uvm_object_utils_end + constraint mem_cfg_cons { + mem.mem_default == MEM_DEFAULT_0; + } /** * Builds events and sub-context objects. @@ -59,6 +66,7 @@ function uvme_cva6_cntxt_c::new(string name="uvme_cva6_cntxt"); clknrst_cntxt = uvma_clknrst_cntxt_c::type_id::create("clknrst_cntxt"); axi_cntxt = uvma_axi_cntxt_c::type_id::create("axi_cntxt"); + mem = uvml_mem_c::type_id::create("mem"); sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); diff --git a/cva6/env/uvme/uvme_cva6_env.sv b/cva6/env/uvme/uvme_cva6_env.sv index ed22eba52..008abaa12 100644 --- a/cva6/env/uvme/uvme_cva6_env.sv +++ b/cva6/env/uvme/uvme_cva6_env.sv @@ -203,6 +203,8 @@ function void uvme_cva6_env_c::assign_cfg(); uvm_config_db#(uvma_cvxif_cfg_c)::set(this, "*cvxif_agent", "cfg", cfg.cvxif_cfg); + uvm_config_db#(uvma_axi_cfg_c)::set(this, "*axi_agent", "cfg", cfg.axi_cfg); + endfunction: assign_cfg @@ -269,16 +271,29 @@ function void uvme_cva6_env_c::assemble_vsequencer(); vsequencer.clknrst_sequencer = clknrst_agent.sequencer; vsequencer.cvxif_sequencer = cvxif_agent.sequencer; + vsequencer.axi_vsequencer = axi_agent.vsequencer; endfunction: assemble_vsequencer task uvme_cva6_env_c::run_phase(uvm_phase phase); + fork + + begin uvma_cvxif_seq_c cvxif_seq; cvxif_seq = uvma_cvxif_seq_c::type_id::create("cvxif_seq"); cvxif_seq.start(cvxif_agent.sequencer); + end + begin + if(cfg.axi_cfg.is_active == UVM_ACTIVE) begin + uvma_axi_vseq_c axi_vseq; + axi_vseq = uvma_axi_vseq_c::type_id::create("axi_vseq"); + axi_vseq.start(axi_agent.vsequencer); + end + end + join_none endtask function void uvme_cva6_env_c::connect_coverage_model(); diff --git a/cva6/env/uvme/uvme_cva6_pkg.sv b/cva6/env/uvme/uvme_cva6_pkg.sv index ea93a206e..52876c643 100644 --- a/cva6/env/uvme/uvme_cva6_pkg.sv +++ b/cva6/env/uvme/uvme_cva6_pkg.sv @@ -44,6 +44,7 @@ package uvme_cva6_pkg; import uvma_clknrst_pkg::*; import uvma_cvxif_pkg::*; import uvma_axi_pkg::*; + import uvml_mem_pkg ::*; // Constants / Structs / Enums `include "uvme_cva6_constants.sv" diff --git a/cva6/env/uvme/uvme_cva6_vsqr.sv b/cva6/env/uvme/uvme_cva6_vsqr.sv index 89b058374..d51e98c87 100644 --- a/cva6/env/uvme/uvme_cva6_vsqr.sv +++ b/cva6/env/uvme/uvme_cva6_vsqr.sv @@ -37,6 +37,7 @@ class uvme_cva6_vsqr_c extends uvm_sequencer#( // Sequencer handles uvma_clknrst_sqr_c clknrst_sequencer; uvma_cvxif_sqr_c cvxif_sequencer; + uvma_axi_vsqr_c axi_vsequencer; `uvm_component_utils_begin(uvme_cva6_vsqr_c) diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index bb8bd4231..08a0c2b99 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -145,6 +145,7 @@ export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug export DV_UVMA_OBI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi export DV_UVML_TRN_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_trn +export DV_UVML_MEM_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_mem export DV_UVML_LOGS_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_logs export DV_UVML_SB_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_sb export CV_CORE_PKG = $(CORE_V_VERIF)/core-v-cores/$(CV_CORE_LC) diff --git a/cva6/tb/uvmt/cva6_tb_wrapper.sv b/cva6/tb/uvmt/cva6_tb_wrapper.sv index f1d740430..c94be22f1 100644 --- a/cva6/tb/uvmt/cva6_tb_wrapper.sv +++ b/cva6/tb/uvmt/cva6_tb_wrapper.sv @@ -105,138 +105,58 @@ module cva6_tb_wrapper #( logic [AXI_DATA_WIDTH-1:0] rdata; logic [AXI_USER_WIDTH-1:0] ruser; - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) cva6_axi_bus(); - - axi_master_connect #( - ) i_axi_master_connect_cva6_to_mem ( - .axi_req_i (axi_ariane_req), - .axi_resp_o (axi_ariane_resp), - .master (cva6_axi_bus) - ); - - axi2mem #( - .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), - .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) i_cva6_axi2mem ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slave ( cva6_axi_bus ), - .req_o ( req ), - .we_o ( we ), - .addr_o ( addr ), - .be_o ( be ), - .user_o ( wuser ), - .data_o ( wdata ), - .user_i ( ruser ), - .data_i ( rdata ) - ); - - sram #( - .USER_WIDTH ( AXI_USER_WIDTH ), - .DATA_WIDTH ( AXI_DATA_WIDTH ), - .USER_EN ( AXI_USER_EN ), - .SIM_INIT ( "zeros" ), - .NUM_WORDS ( NUM_WORDS ) - ) i_sram ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( req ), - .we_i ( we ), - .addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ), - .wuser_i ( wuser ), - .wdata_i ( wdata ), - .be_i ( be ), - .ruser_o ( ruser ), - .rdata_o ( rdata ) - ); - - // AW Channel - assign axi_slave.aw_valid = cva6_axi_bus.aw_valid; - assign axi_slave.aw_ready = cva6_axi_bus.aw_ready; - assign axi_slave.aw_id = cva6_axi_bus.aw_id; - assign axi_slave.aw_addr = cva6_axi_bus.aw_addr; - assign axi_slave.aw_len = cva6_axi_bus.aw_len; - assign axi_slave.aw_size = cva6_axi_bus.aw_size; - assign axi_slave.aw_burst = cva6_axi_bus.aw_burst; - assign axi_slave.aw_lock = cva6_axi_bus.aw_lock; - assign axi_slave.aw_cache = cva6_axi_bus.aw_cache; - assign axi_slave.aw_prot = cva6_axi_bus.aw_prot; - assign axi_slave.aw_qos = cva6_axi_bus.aw_qos; - assign axi_slave.aw_region = cva6_axi_bus.aw_region; - assign axi_slave.aw_user = cva6_axi_bus.aw_user; - assign axi_slave.aw_atop = cva6_axi_bus.aw_atop; - // W Channel - assign axi_slave.w_valid = cva6_axi_bus.w_valid; - assign axi_slave.w_ready = cva6_axi_bus.w_ready; - assign axi_slave.w_data = cva6_axi_bus.w_data; - assign axi_slave.w_strb = cva6_axi_bus.w_strb; - assign axi_slave.w_last = cva6_axi_bus.w_last; - assign axi_slave.w_user = cva6_axi_bus.w_user; + //Response structs + assign axi_ariane_resp.aw_ready = axi_slave.aw_ready; + assign axi_ariane_resp.ar_ready = axi_slave.ar_ready; + assign axi_ariane_resp.w_ready = axi_slave.w_ready; + assign axi_ariane_resp.b_valid = axi_slave.b_valid; + assign axi_ariane_resp.r_valid = axi_slave.r_valid; // B Channel - assign axi_slave.b_valid = cva6_axi_bus.b_valid; - assign axi_slave.b_ready = cva6_axi_bus.b_ready; - assign axi_slave.b_id = cva6_axi_bus.b_id; - assign axi_slave.b_resp = cva6_axi_bus.b_resp; - assign axi_slave.b_user = cva6_axi_bus.b_user; - // AR Channel - assign axi_slave.ar_valid = cva6_axi_bus.ar_valid; - assign axi_slave.ar_ready = cva6_axi_bus.ar_ready; - assign axi_slave.ar_id = cva6_axi_bus.ar_id; - assign axi_slave.ar_addr = cva6_axi_bus.ar_addr; - assign axi_slave.ar_len = cva6_axi_bus.ar_len; - assign axi_slave.ar_size = cva6_axi_bus.ar_size; - assign axi_slave.ar_burst = cva6_axi_bus.ar_burst; - assign axi_slave.ar_lock = cva6_axi_bus.ar_lock; - assign axi_slave.ar_cache = cva6_axi_bus.ar_cache; - assign axi_slave.ar_prot = cva6_axi_bus.ar_prot; - assign axi_slave.ar_qos = cva6_axi_bus.ar_qos; - assign axi_slave.ar_region = cva6_axi_bus.ar_region; - assign axi_slave.ar_user = cva6_axi_bus.ar_user; + assign axi_ariane_resp.b.id = axi_slave.b_id; + assign axi_ariane_resp.b.resp = axi_slave.b_resp; + assign axi_ariane_resp.b.user = axi_slave.b_user; // R Channel - assign axi_slave.r_valid = cva6_axi_bus.r_valid; - assign axi_slave.r_ready = cva6_axi_bus.r_ready; - assign axi_slave.r_id = cva6_axi_bus.r_id; - assign axi_slave.r_data = cva6_axi_bus.r_data; - assign axi_slave.r_resp = cva6_axi_bus.r_resp; - assign axi_slave.r_last = cva6_axi_bus.r_last; - assign axi_slave.r_user = cva6_axi_bus.r_user; - initial begin - automatic logic [7:0][7:0] mem_row; - longint address; - longint len; - byte buffer[]; - void'(uvcl.get_arg_value("+PRELOAD=", binary)); + assign axi_ariane_resp.r.id = axi_slave.r_id; + assign axi_ariane_resp.r.data = axi_slave.r_data; + assign axi_ariane_resp.r.resp = axi_slave.r_resp; + assign axi_ariane_resp.r.last = axi_slave.r_last; + assign axi_ariane_resp.r.user = axi_slave.r_user; - if (binary != "") begin + // Request structs + assign axi_slave.aw_valid = axi_ariane_req.aw_valid; + assign axi_slave.w_valid = axi_ariane_req.w_valid; + assign axi_slave.b_ready = axi_ariane_req.b_ready; + assign axi_slave.ar_valid = axi_ariane_req.ar_valid; + assign axi_slave.r_ready = axi_ariane_req.r_ready; + // AW Channel + assign axi_slave.aw_id = axi_ariane_req.aw.id; + assign axi_slave.aw_addr = axi_ariane_req.aw.addr; + assign axi_slave.aw_len = axi_ariane_req.aw.len; + assign axi_slave.aw_size = axi_ariane_req.aw.size; + assign axi_slave.aw_burst = axi_ariane_req.aw.burst; + assign axi_slave.aw_lock = axi_ariane_req.aw.lock; + assign axi_slave.aw_cache = axi_ariane_req.aw.cache; + assign axi_slave.aw_prot = axi_ariane_req.aw.prot; + assign axi_slave.aw_qos = axi_ariane_req.aw.qos; + assign axi_slave.aw_region = axi_ariane_req.aw.region; + assign axi_slave.aw_user = 0; + // W Channel + assign axi_slave.w_data = axi_ariane_req.w.data; + assign axi_slave.w_strb = axi_ariane_req.w.strb; + assign axi_slave.w_last = axi_ariane_req.w.last; + assign axi_slave.w_user = 0; + // AR Channel + assign axi_slave.ar_id = axi_ariane_req.ar.id; + assign axi_slave.ar_addr = axi_ariane_req.ar.addr; + assign axi_slave.ar_len = axi_ariane_req.ar.len; + assign axi_slave.ar_size = axi_ariane_req.ar.size; + assign axi_slave.ar_burst = axi_ariane_req.ar.burst; + assign axi_slave.ar_lock = axi_ariane_req.ar.lock; + assign axi_slave.ar_cache = axi_ariane_req.ar.cache; + assign axi_slave.ar_prot = axi_ariane_req.ar.prot; + assign axi_slave.ar_qos = axi_ariane_req.ar.qos; + assign axi_slave.ar_region = axi_ariane_req.ar.region; + assign axi_slave.ar_user = 0; - void'(read_elf(binary)); - - wait(clk_i); - - // while there are more sections to process - while (get_section(address, len)) begin - automatic int num_words0 = (len+7)/8; - `uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len), UVM_LOW) - buffer = new [num_words0*8]; - void'(read_section(address, buffer)); - // preload memories - // 64-bit - for (int i = 0; i < num_words0; i++) begin - mem_row = '0; - for (int j = 0; j < 8; j++) begin - mem_row[j] = buffer[i*8 + j]; - end - `MAIN_MEM((address[23:0] >> 3) + i) = mem_row; - end - end - end - end endmodule diff --git a/cva6/tb/uvmt/uvmt_cva6.flist b/cva6/tb/uvmt/uvmt_cva6.flist index d70c0ab92..0c04c48ad 100644 --- a/cva6/tb/uvmt/uvmt_cva6.flist +++ b/cva6/tb/uvmt/uvmt_cva6.flist @@ -18,6 +18,7 @@ -f ${DV_UVML_HRTBT_PATH}/uvml_hrtbt_pkg.flist -f ${DV_UVML_TRN_PATH}/uvml_trn_pkg.flist -f ${DV_UVML_LOGS_PATH}/uvml_logs_pkg.flist +-f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist -f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist // Agents From a51df638a938ee7a0ff710d5f46c8b74675ea587 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 28 Dec 2022 10:11:52 +0100 Subject: [PATCH 040/183] axi_agent : Add function to randomize response error and the ready latency Signed-off-by: Alae Eddine Ez zejjari --- .../uvma_axi_ar_agent/uvma_axi_ar_drv.sv | 8 +- .../uvma_axi_aw_agent/uvma_axi_aw_drv.sv | 9 +- .../comps/uvma_axi_w_agent/uvma_axi_w_drv.sv | 2 +- .../uvma_axi/src/obj/uvma_axi_cfg.sv | 97 +++++++++++++++++++ .../uvma_axi/src/seq/uvma_axi_ar_item.sv | 2 + .../uvma_axi/src/seq/uvma_axi_ar_seq.sv | 8 ++ .../uvma_axi/src/seq/uvma_axi_aw_item.sv | 2 + .../uvma_axi/src/seq/uvma_axi_aw_seq.sv | 8 ++ .../uvma_axi/src/seq/uvma_axi_b_seq.sv | 4 +- .../uvma_axi/src/seq/uvma_axi_r_seq.sv | 3 +- .../uvma_axi/src/seq/uvma_axi_w_item.sv | 2 + .../uvma_axi/src/seq/uvma_axi_w_seq.sv | 33 ++++++- lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv | 11 +++ 13 files changed, 180 insertions(+), 9 deletions(-) diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv index 670843c40..9e9af3bbf 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_drv.sv @@ -70,9 +70,15 @@ class uvma_axi_ar_drv_c extends uvm_driver #(uvma_axi_ar_item_c); task drv_post_reset(); seq_item_port.get_next_item(ar_item); - this.slave_mp.slv_axi_cb.ar_ready <= 1'b1; + if(ar_item.ar_valid) begin + repeat (ar_item.ar_latency) begin + @(slave_mp.slv_axi_cb); + end + this.slave_mp.slv_axi_cb.ar_ready <= 1'b1; + end `uvm_info(get_type_name(), $sformatf("read address, response by ar_ready"), UVM_LOW) @(slave_mp.slv_axi_cb); + this.slave_mp.slv_axi_cb.ar_ready <= 1'b0; seq_item_port.item_done(); endtask: drv_post_reset diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv index 515959530..815b68184 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_drv.sv @@ -84,7 +84,14 @@ task uvma_axi_aw_drv_c::drv_post_reset(); `uvm_info(get_type_name(), $sformatf("write address driver start"), UVM_LOW) seq_item_port.get_next_item(aw_item); - this.slave_mp.slv_axi_cb.aw_ready <= 1'b1; + this.slave_mp.slv_axi_cb.aw_ready <= 1'b0; + + if(aw_item.aw_valid) begin + repeat (aw_item.aw_latency) begin + @(slave_mp.slv_axi_cb); + end + this.slave_mp.slv_axi_cb.aw_ready <= 1'b1; + end @(slave_mp.slv_axi_cb); seq_item_port.item_done(); diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv index 1b205d39d..95cb3ff44 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_drv.sv @@ -94,7 +94,7 @@ task uvma_axi_w_drv_c::drv_post_reset(); seq_item_port.get_next_item(w_item); `uvm_info(get_type_name(), $sformatf("write data driver start"), UVM_LOW) - this.slave_mp.slv_axi_cb.w_ready <= 1'b1; + this.slave_mp.slv_axi_cb.w_ready <= w_item.w_ready; @(slave_mp.slv_axi_cb); seq_item_port.item_done(); diff --git a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv index 0f4e6ac16..033a56682 100644 --- a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv +++ b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv @@ -15,18 +15,61 @@ class uvma_axi_cfg_c extends uvm_object; rand uvm_active_passive_enum is_active; + rand uvma_axi_drv_slv_mode_enum drv_slv_mode; + rand uvma_axi_drv_slv_err_mode_enum drv_slv_err_mode; + rand int unsigned drv_slv_fixed_latency; + rand int unsigned drv_slv_random_latency_min; + rand int unsigned drv_slv_random_latency_max; + + rand int unsigned drv_slv_err_ok; + rand int unsigned drv_slv_err_dec; + rand int unsigned drv_slv_err_slv; + rand bit drv_slv_err_one_shot_mode; + rand bit drv_slv_err_one_shot_flag; + bit directed_slv_err_valid; + bit[1:0] drv_slv_fixed_resp = 2'b10; `uvm_object_utils_begin(uvma_axi_cfg_c) `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT); + `uvm_field_int (directed_slv_err_valid, UVM_DEFAULT) + `uvm_field_int (drv_slv_fixed_latency, UVM_DEFAULT) + `uvm_field_int (drv_slv_random_latency_min, UVM_DEFAULT) + `uvm_field_int (drv_slv_random_latency_max, UVM_DEFAULT) + `uvm_field_int (drv_slv_err_one_shot_mode, UVM_DEFAULT) + `uvm_field_int (drv_slv_err_one_shot_flag, UVM_DEFAULT) + `uvm_field_int (drv_slv_err_ok, UVM_DEFAULT | UVM_DEC) + `uvm_field_int (drv_slv_err_dec, UVM_DEFAULT | UVM_DEC) + `uvm_field_int (drv_slv_err_slv, UVM_DEFAULT | UVM_DEC) + `uvm_field_int (drv_slv_fixed_resp, UVM_DEFAULT | UVM_DEC) + `uvm_field_enum(uvma_axi_drv_slv_mode_enum, drv_slv_mode, UVM_DEFAULT) + `uvm_field_enum(uvma_axi_drv_slv_err_mode_enum, drv_slv_err_mode, UVM_DEFAULT) `uvm_object_utils_end constraint defaults_config { soft is_active == UVM_ACTIVE; + soft drv_slv_err_one_shot_mode == 0; + soft drv_slv_mode == UVMA_AXI_DRV_SLV_MODE_RANDOM_LATENCY; + soft drv_slv_fixed_latency == 3; + soft drv_slv_random_latency_min == 0; + soft drv_slv_random_latency_max == 4; + soft directed_slv_err_valid == 0; + soft drv_slv_err_mode == UVMA_AXI_DRV_SLV_ERR_MODE_RANDOM; } + constraint err_wgts_cons { + // Keep the weights for errors within some bounds + drv_slv_err_ok inside {[0:1000]}; + drv_slv_err_dec inside {[0:1000]}; + drv_slv_err_slv inside {[0:1000]}; + } + extern function new(string name = "uvma_axi_cfg"); + extern function int unsigned calc_random_latency(); + + extern function bit[1:0] random_err(); + endclass : uvma_axi_cfg_c @@ -36,4 +79,58 @@ function uvma_axi_cfg_c::new(string name = "uvma_axi_cfg"); endfunction : new +function int unsigned uvma_axi_cfg_c::calc_random_latency(); + int unsigned effective_latency; + + case (drv_slv_mode) + UVMA_AXI_DRV_SLV_MODE_CONSTANT : effective_latency = 0; + UVMA_AXI_DRV_SLV_MODE_FIXED_LATENCY : effective_latency = drv_slv_fixed_latency; + UVMA_AXI_DRV_SLV_MODE_RANDOM_LATENCY: begin + effective_latency = $urandom_range(drv_slv_random_latency_min, drv_slv_random_latency_max); + end + endcase + + return effective_latency; + +endfunction : calc_random_latency + +function bit[1:0] uvma_axi_cfg_c::random_err(); + + bit[1:0] err; + + // If we are in "one-shot" mode and have already calculated an error, + // then skip any new errors (until the code resets the flag) + if (drv_slv_err_one_shot_mode && drv_slv_err_one_shot_flag) begin + return 0; + end + + // Check for a directed error reponse first + if (directed_slv_err_valid) begin + + if (drv_slv_err_one_shot_mode) begin + drv_slv_err_one_shot_flag = 1; + end + + return drv_slv_fixed_resp; + end + + case (drv_slv_err_mode) + UVMA_AXI_DRV_SLV_ERR_MODE_OK : err = 2'b00; + UVMA_AXI_DRV_SLV_ERR_MODE_RANDOM : begin + randcase + drv_slv_err_ok : err = 2'b00; + drv_slv_err_dec: err = 2'b11; + drv_slv_err_slv: err = 2'b10; + endcase + end + endcase + + if (err != 0 && drv_slv_err_one_shot_mode) begin + drv_slv_err_one_shot_flag = 1; + end + + return err; + +endfunction : random_err + `endif //__UVMA_AXI_CFG_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv index e4a2baec8..3f740b051 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_item.sv @@ -25,6 +25,7 @@ class uvma_axi_ar_item_c extends uvm_sequence_item; rand logic ar_valid; rand logic ar_ready; rand logic ar_lock; + int ar_latency; `uvm_object_utils_begin(uvma_axi_ar_item_c) `uvm_field_int(ar_id, UVM_ALL_ON | UVM_NOPACK); @@ -36,6 +37,7 @@ class uvma_axi_ar_item_c extends uvm_sequence_item; `uvm_field_int(ar_valid, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(ar_ready, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(ar_lock, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE); `uvm_object_utils_end function new(string name = "uvma_axi_ar_item_c"); diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv index d4fa0c652..3bfdcfff8 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_ar_seq.sv @@ -25,6 +25,7 @@ class uvma_axi_ar_seq_c extends uvm_sequence#(uvma_axi_ar_item_c); uvma_axi_ar_item_c req_item; extern function new(string name = ""); + extern function void add_latencies(uvma_axi_ar_item_c master_req); extern task body(); endclass : uvma_axi_ar_seq_c @@ -34,6 +35,12 @@ function uvma_axi_ar_seq_c::new(string name = ""); super.new(name); endfunction : new +function void uvma_axi_ar_seq_c::add_latencies(uvma_axi_ar_item_c master_req); + + master_req.ar_latency = cfg.calc_random_latency(); + +endfunction : add_latencies + task uvma_axi_ar_seq_c::body(); forever begin cfg = p_sequencer.cfg; @@ -44,6 +51,7 @@ task uvma_axi_ar_seq_c::body(); start_item(req_item); `uvm_info(get_type_name(), "READ ADDRESS sequence starting", UVM_LOW) + add_latencies(req_item); finish_item(req_item); end `uvm_info(get_type_name(), "Default sequence completed", UVM_LOW) diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv index a6b757bdc..86b45ffa3 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_item.sv @@ -30,6 +30,7 @@ class uvma_axi_aw_item_c extends uvm_sequence_item; rand logic [3:0] aw_qos; rand logic [3:0] aw_region; rand logic [5:0] aw_atop; + int aw_latency; `uvm_object_utils_begin(uvma_axi_aw_item_c) `uvm_field_int(aw_id, UVM_ALL_ON | UVM_NOPACK); @@ -46,6 +47,7 @@ class uvma_axi_aw_item_c extends uvm_sequence_item; `uvm_field_int(aw_qos, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(aw_region, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(aw_atop, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE); `uvm_object_utils_end function new(string name = "uvma_axi_aw_item_c"); diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv index 04a0e6257..976b0be1e 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_aw_seq.sv @@ -26,6 +26,7 @@ class uvma_axi_aw_seq_c extends uvm_sequence#(uvma_axi_aw_item_c); uvma_axi_aw_item_c req_item; extern function new(string name = ""); + extern function void add_latencies(uvma_axi_aw_item_c master_req); extern task body(); endclass : uvma_axi_aw_seq_c @@ -35,6 +36,12 @@ function uvma_axi_aw_seq_c::new(string name = ""); super.new(name); endfunction : new +function void uvma_axi_aw_seq_c::add_latencies(uvma_axi_aw_item_c master_req); + + master_req.aw_latency = cfg.calc_random_latency(); + +endfunction : add_latencies + task uvma_axi_aw_seq_c::body(); forever begin cfg = p_sequencer.cfg ; @@ -45,6 +52,7 @@ task uvma_axi_aw_seq_c::body(); start_item(req_item); `uvm_info(get_type_name(), "WRITE ADDRESS sequence starting", UVM_LOW) + add_latencies(req_item); finish_item(req_item); end diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv index 8edb9d0fc..907acbdb2 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_b_seq.sv @@ -36,6 +36,7 @@ class uvma_axi_b_seq_c extends uvm_sequence#(uvma_axi_b_item_c); int first_req = 0; int selected_id; int enable_change_id = 1; + bit[1:0] inject_error; extern function new(string name = ""); extern function void create_item(); @@ -131,6 +132,7 @@ task uvma_axi_b_seq_c::body(); if(enable_change_id == 1) begin selected_id = check_tab(status); + inject_error = cfg.random_err(); end `uvm_info(get_type_name(), $sformatf("selected id = %d", selected_id), UVM_HIGH) @@ -139,7 +141,7 @@ task uvma_axi_b_seq_c::body(); `uvm_info(get_type_name(), "send resp", UVM_HIGH) b_resp_item.b_id = req_requette[selected_id][0].aw_id; - b_resp_item.b_resp = 0; + b_resp_item.b_resp = inject_error; b_resp_item.b_valid = 1; b_resp_item.b_user = 0; diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv index 2cf7563ca..c1684189f 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_r_seq.sv @@ -104,6 +104,7 @@ task uvma_axi_r_seq_c::body(); if(enable_change_id == 1) begin selected_id = check_tab(status); + inject_error = cfg.random_err(); r_latency = -1; end @@ -131,7 +132,7 @@ task uvma_axi_r_seq_c::body(); end selected_id = check_tab(status); - inject_error = 1'b0; + inject_error = cfg.random_err(); r_latency = -1; if(selected_id == -1) begin diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv index 76e23da1d..1424838ba 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_item.sv @@ -21,6 +21,7 @@ class uvma_axi_w_item_c extends uvm_sequence_item; rand logic w_user; rand logic w_valid; rand logic w_ready; + int w_latency; `uvm_object_param_utils_begin(uvma_axi_w_item_c) `uvm_field_int(w_strb, UVM_ALL_ON | UVM_NOPACK); @@ -29,6 +30,7 @@ class uvma_axi_w_item_c extends uvm_sequence_item; `uvm_field_int(w_user, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(w_valid, UVM_ALL_ON | UVM_NOPACK); `uvm_field_int(w_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE); `uvm_object_utils_end function new(string name = "uvma_axi_w_item_c"); diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv index e5c9489c7..5aba1d7c3 100644 --- a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_w_seq.sv @@ -6,6 +6,7 @@ // You may obtain a copy of the License at https://solderpad.org/licenses/ // // Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi //============================================================================= // Description: Sequence for agent axi_w @@ -46,6 +47,12 @@ function uvma_axi_w_seq_c::new(string name = ""); super.new(name); endfunction : new +function void uvma_axi_w_seq_c::add_latencies(uvma_axi_w_item_c master_req); + + master_req.w_latency = cfg.calc_random_latency(); + +endfunction : add_latencies + task uvma_axi_w_seq_c::body(); aw_req_item = uvma_axi_aw_item_c::type_id::create("aw_req_item"); @@ -91,10 +98,28 @@ task uvma_axi_w_seq_c::body(); `uvm_info(get_type_name(), $sformatf("req_requette size = %d", req_requette.size()), UVM_LOW) if(w_req_item.w_valid) begin - write_data_req = new[write_data_req.size() + 1] (write_data_req); - write_data_req[write_data_req.size() - 1] = new w_req_item; - write_status = 1; - + if(latency == 0) begin + add_latencies(w_req_item); + w_ready_latency = w_req_item.w_latency; + end + + w_req_item.w_ready = 0; + + if(latency == w_ready_latency) begin + w_req_item.w_ready = 1; + latency = 0; + end else begin + latency++; + end + + if(w_req_item.w_ready) begin + write_data_req = new[write_data_req.size() + 1] (write_data_req); + write_data_req[write_data_req.size() - 1] = new w_req_item; + write_status = 1; + end + + end else begin + w_req_item.w_ready = 0; end `uvm_info(get_type_name(), $sformatf("status = %d et write_status = %d", status, write_status), UVM_LOW) diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv index 0b996ce01..dea9a4f2b 100644 --- a/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_tdefs.sv @@ -18,4 +18,15 @@ UVMA_AXI_RESET_STATE_POST_RESET } uvma_axi_reset_state_enum; + typedef enum { + UVMA_AXI_DRV_SLV_MODE_CONSTANT , + UVMA_AXI_DRV_SLV_MODE_FIXED_LATENCY , + UVMA_AXI_DRV_SLV_MODE_RANDOM_LATENCY + } uvma_axi_drv_slv_mode_enum; + + typedef enum { + UVMA_AXI_DRV_SLV_ERR_MODE_OK, + UVMA_AXI_DRV_SLV_ERR_MODE_RANDOM + } uvma_axi_drv_slv_err_mode_enum; + `endif // __UVMA_AXI_TDEFS_SV__ From 3b6d8fd077d718d832ed6f052a1bb14a83310477 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Thu, 8 Dec 2022 10:22:59 +0100 Subject: [PATCH 041/183] axi_agent: add assertion modules Signed-off-by: Alae Eddine Ez zejjari --- .../uvma_axi/src/uvma_axi_ar_assert.sv | 316 +++++++++++++++++ .../uvma_axi/src/uvma_axi_aw_assert.sv | 318 ++++++++++++++++++ .../uvma_axi/src/uvma_axi_b_assert.sv | 109 ++++++ lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv | 5 + .../uvma_axi/src/uvma_axi_r_assert.sv | 141 ++++++++ .../uvma_axi/src/uvma_axi_w_assert.sv | 125 +++++++ 6 files changed, 1014 insertions(+) create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_ar_assert.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_aw_assert.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_b_assert.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_r_assert.sv create mode 100644 lib/uvm_agents/uvma_axi/src/uvma_axi_w_assert.sv diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_ar_assert.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_ar_assert.sv new file mode 100644 index 000000000..6fe7157d1 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_ar_assert.sv @@ -0,0 +1,316 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// *************************** READ ADDRESS CHANNEL ************************** // + +module uvma_axi_ar_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + + +// *************************** Check if control information Signals are not equal to X or Z when ARVALID is HIGH (Section A3.2.2) ************************** // + + property AXI4_ARID_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_id)); + endproperty + + property AXI4_ARADDR_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_addr)); + endproperty + + property AXI4_ARLEN_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_len)); + endproperty + + property AXI4_ARSIZE_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_size)); + endproperty + + property AXI4_ARBURST_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_burst)); + endproperty + + property AXI4_ARLOCK_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_lock)); + endproperty + + property AXI4_ARCACHE_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_cache)); + endproperty + + property AXI4_ARPROT_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_prot)); + endproperty + + property AXI4_ARUSER_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_user)); + endproperty + + property AXI4_ARQOS_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_qos)); + endproperty + + property AXI4_ARREGION_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!$isunknown(axi_assert.psv_axi_cb.ar_region)); + endproperty + + // A value of X on ARVALID is not permitted when not in reset (Section A3.1.2) + property AXI4_ARVALID_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.ar_valid)); + endproperty + + // A value of X on ARREADY is not permitted when not in reset (Section A3.1.2) + property AXI4_ARREADY_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.ar_ready)); + endproperty + +// *************************** Check if control information Signals are stable when ARVALID is HIGH (Section A3.2.1) ************************** // + + property AXI4_ARID_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_id))); + endproperty + + property AXI4_ARADDR_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_addr))); + endproperty + + property AXI4_ARLEN_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_len))); + endproperty + + property AXI4_ARSIZE_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_size))); + endproperty + + property AXI4_ARBURST_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_burst))); + endproperty + + property AXI4_ARLOCK_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_lock))); + endproperty + + property AXI4_ARCACHE_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_cache))); + endproperty + + property AXI4_ARPROT_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_prot))); + endproperty + + property AXI4_ARUSER_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_user))); + endproperty + + property AXI4_ARQOS_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_qos))); + endproperty + + property AXI4_ARREGION_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (!axi_assert.psv_axi_cb.ar_ready |=> ($stable(axi_assert.psv_axi_cb.ar_region))); + endproperty + + // Check if, Once asserted, ar_valid must remain asserted until ar_ready is HIGH (Section A3.2.1) + property AXI4_AR_VALID_READY ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (axi_assert.psv_axi_cb.ar_valid throughout (axi_assert.psv_axi_cb.ar_ready [->1])); + endproperty + + // check if a read transaction with burst type WRAP has an aligned address (Section A3.4.1) + property AXI_ARADDR_WRAP_ALIGN; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.ar_valid && axi_assert.psv_axi_cb.ar_burst == 2'b10) |-> !((axi_assert.psv_axi_cb.ar_addr) % (2**axi_assert.psv_axi_cb.ar_size)); + endproperty + + // check if The size of a read transfer does not exceed the width of the data interface (Section A3.4.1) + property AXI_ERRM_ARSIZE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (8*(2**axi_assert.psv_axi_cb.ar_size) <= `UVMA_AXI_DATA_MAX_WIDTH); + endproperty + + // check if burst crosses 4KB boundaries (Section A3.4.1) + property AXI4_ERRM_ARADDR_BOUNDARY; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (((axi_assert.psv_axi_cb.ar_addr + (axi_assert.psv_axi_cb.ar_len + 1)*(2**axi_assert.psv_axi_cb.ar_size)) % 4096) > (axi_assert.psv_axi_cb.ar_addr % 4096)) || !((axi_assert.psv_axi_cb.ar_addr+(axi_assert.psv_axi_cb.ar_len + 1) * (2**axi_assert.psv_axi_cb.ar_size)) % 4096) ; + endproperty + + // Check if the burst length equal to 2, 4, 8, or 16, for wrapping bursts (Section A3.4.1) + property AXI_ARLEN_WRAPP_BURST; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.ar_valid && axi_assert.psv_axi_cb.ar_burst == 2'b10) |-> (axi_assert.psv_axi_cb.ar_len == 1) || (axi_assert.psv_axi_cb.ar_len == 3) || (axi_assert.psv_axi_cb.ar_len == 7) || (axi_assert.psv_axi_cb.ar_len == 15); + endproperty + + // Check if ar_burst can’t be 2’b11 (Table A3-3) + property AXI4_AR_BURST_CANT_2b11; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_valid |-> (axi_assert.psv_axi_cb.ar_burst != 2'b11); + endproperty + + // Check if ARVALID is LOW for the first cycle after ARESETn goes HIGH (Figure A3-1) + property AXI4_ARVALID_RESET; + @(posedge clk) $rose(rst_n) |=> !(axi_assert.psv_axi_cb.ar_valid); + endproperty + + // Check if the length of an exclusive access transaction don't pass 16 beats (Section A7.2.4) + property AXI4_ARLEN_LOCK; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.ar_lock |-> (signed' (axi_assert.psv_axi_cb.ar_len)) <= 16; + endproperty + + // Check if ARCACHE[3:2] are LOW, When ARVALID is HIGH and ARCACHE[1] is LOW (Table A4-5) + property AXI4_ARCACHE_LOW; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.ar_valid) && !(axi_assert.psv_axi_cb.ar_cache[1]) |-> !(axi_assert.psv_axi_cb.ar_cache[3:2]); + endproperty + + // Check if a transactions of burst type FIXED don't have a length greater than 16 beats (Section A3.4.1) + property AXI4_ARLEN_FIXED; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.ar_burst == 2'b00) |-> (axi_assert.psv_axi_cb.ar_len <= 15); + endproperty + +/********************************************** Assert Property ******************************************************/ + + ar_valid_ready : assert property (AXI4_AR_VALID_READY) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AR_VALID_READY"); + + arlen_wrapp_burst : assert property (AXI_ARLEN_WRAPP_BURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_ARLEN_WRAPP_BURST"); + + araddr_wrap_align : assert property (AXI_ARADDR_WRAP_ALIGN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_ARADDR_WRAP_ALIGN"); + + assert_arsize : assert property (AXI_ERRM_ARSIZE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_ERRM_ARSIZE"); + + ar_burst_cant_2b11 : assert property (AXI4_AR_BURST_CANT_2b11) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AR_BURST_CANT_2b11"); + + araddr_boundary : assert property (AXI4_ERRM_ARADDR_BOUNDARY) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ERRM_ARADDR_BOUNDARY"); + + arvalid_reset : assert property (AXI4_ARVALID_RESET) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARVALID_RESET"); + + arlen_lock : assert property (AXI4_ARLEN_LOCK) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLEN_LOCK"); + + arcahce_low : assert property (AXI4_ARCACHE_LOW) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARCACHE_LOW"); + + arlen_fixed : assert property (AXI4_ARLEN_FIXED) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLEN_FIXED"); + + arid_x : assert property (AXI4_ARID_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARID_X"); + + araddr_x : assert property (AXI4_ARADDR_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARADDR_X"); + + arlen_x : assert property (AXI4_ARLEN_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLEN_X"); + + arsize_x : assert property (AXI4_ARSIZE_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARSIZE_X"); + + arburst_x : assert property (AXI4_ARBURST_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARBURST_X"); + + arlock_x : assert property (AXI4_ARLOCK_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLOCK_X"); + + arcache_x : assert property (AXI4_ARCACHE_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARCACHE_X"); + + arprot_x : assert property (AXI4_ARPROT_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARPROT_X"); + + arqos_x : assert property (AXI4_ARQOS_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARQOS_X"); + + arregion_x : assert property (AXI4_ARREGION_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARREGION_X"); + + arvalid_x : assert property (AXI4_ARVALID_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARVALID_X"); + + arready_x : assert property (AXI4_ARREADY_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARREADY_X"); + + arid_stable : assert property (AXI4_ARID_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARID_STABLE"); + + araddr_stable : assert property (AXI4_ARADDR_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARADDR_STABLE"); + + arlen_stable : assert property (AXI4_ARLEN_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLEN_STABLE"); + + arsize_stable : assert property (AXI4_ARSIZE_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARSIZE_STABLE"); + + arburst_stable : assert property (AXI4_ARBURST_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARBURST_STABLE"); + + arlock_stable : assert property (AXI4_ARLOCK_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARLOCK_STABLE"); + + arcache_stable : assert property (AXI4_ARCACHE_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARCACHE_STABLE"); + + arprot_stable : assert property (AXI4_ARPROT_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARPROT_STABLE"); + + aruser_stable : assert property (AXI4_ARUSER_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARUSER_STABLE"); + + arqos_stable : assert property (AXI4_ARQOS_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARQOS_STABLE"); + + arregion_stable : assert property (AXI4_ARREGION_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ARREGION_STABLE"); + +/********************************************** Cover Property ******************************************************/ + + cov_ar_valid_ar_ready : cover property(AXI4_AR_VALID_READY); + + cov_araddr_wrap_align : cover property(AXI_ARADDR_WRAP_ALIGN); + + cov_arlen_wrapp_burst : cover property(AXI_ARLEN_WRAPP_BURST); + + cov_arsize : cover property(AXI_ERRM_ARSIZE); + + cov_arvalid_reset : cover property(AXI4_ARVALID_RESET); + + cov_ar_burst_cant_2b11 : cover property(AXI4_AR_BURST_CANT_2b11); + + cov_errm_ARaddr_boundary : cover property(AXI4_ERRM_ARADDR_BOUNDARY); + + cov_arlen_lock : cover property(AXI4_ARLEN_LOCK); + + cov_arcache_low : cover property(AXI4_ARCACHE_LOW); + + cov_arlen_fixed : cover property(AXI4_ARLEN_FIXED); + + cov_arid_stable : cover property(AXI4_ARID_STABLE); + + cov_araddr_stable : cover property(AXI4_ARADDR_STABLE); + + cov_arlen_stable : cover property(AXI4_ARLEN_STABLE); + + cov_arsize_stable : cover property(AXI4_ARSIZE_STABLE); + + cov_arburst_stable : cover property(AXI4_ARBURST_STABLE); + + cov_arlock_stable : cover property(AXI4_ARLOCK_STABLE); + + cov_arcache_stable : cover property(AXI4_ARCACHE_STABLE); + + cov_arprot_stable : cover property(AXI4_ARPROT_STABLE); + + cov_aruser_stable : cover property(AXI4_ARUSER_STABLE); + + cov_arqos_stable : cover property(AXI4_ARQOS_STABLE); + + cov_arregion_stable : cover property(AXI4_ARREGION_STABLE); + + +endmodule : uvma_axi_ar_assert diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_aw_assert.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_aw_assert.sv new file mode 100644 index 000000000..8bab3da9c --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_aw_assert.sv @@ -0,0 +1,318 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// ***************************WRITE ADDRESS CHANNEL ************************** // + +module uvma_axi_aw_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + +// *************************** Check if control information Signals are not equal to X or Z when WVALID is HIGH (Section A3.2.2) ************************** // + + property AXI4_AWID_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_id)); + endproperty + + property AXI4_AWADDR_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_addr)); + endproperty + + property AXI4_AWLEN_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_len)); + endproperty + + property AXI4_AWSIZE_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_size)); + endproperty + + property AXI4_AWBURST_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_burst)); + endproperty + + property AXI4_AWLOCK_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_lock)); + endproperty + + property AXI4_AWCACHE_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_cache)); + endproperty + + property AXI4_AWPROT_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_prot)); + endproperty + + property AXI4_AWUSER_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_user)); + endproperty + + property AXI4_AWQOS_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_qos)); + endproperty + + property AXI4_AWREGION_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!$isunknown(axi_assert.psv_axi_cb.aw_region)); + endproperty + + // A value of X on AWVALID is not permitted when not in reset (Section A3.1.2) + property AXI4_AWVALID_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.aw_valid)); + endproperty + + // A value of X on AWREADY is not permitted when not in reset (Section A3.1.2) + property AXI4_AWREADY_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.aw_ready)); + endproperty + +// *************************** Check if control information Signals are stable when AWVALID is HIGH (Section A3.2.1) ************************** // + + property AXI4_AWID_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_id))); + endproperty + + property AXI4_AWADDR_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_addr))); + endproperty + + property AXI4_AWLEN_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_len))); + endproperty + + property AXI4_AWSIZE_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_size))); + endproperty + + property AXI4_AWBURST_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_burst))); + endproperty + + property AXI4_AWLOCK_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_lock))); + endproperty + + property AXI4_AWCACHE_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_cache))); + endproperty + + property AXI4_AWPROT_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_prot))); + endproperty + + property AXI4_AWUSER_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_user))); + endproperty + + property AXI4_AWQOS_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_qos))); + endproperty + + property AXI4_AWREGION_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (!axi_assert.psv_axi_cb.aw_ready |=> ($stable(axi_assert.psv_axi_cb.aw_region))); + endproperty + + // Check if, Once asserted, aw_valid must remain asserted until aw_ready is HIGH (Section A3.2.1) + property AXI4_AW_VALID_READY; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> ( axi_assert.psv_axi_cb.aw_valid throughout (axi_assert.psv_axi_cb.aw_ready [->1])); + endproperty + + // check if a write transaction with burst type WRAP has an aligned address (Section A3.4.1) + property AXI_AWADDR_WRAP_ALIGN; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.aw_valid && axi_assert.psv_axi_cb.aw_burst == 2'b10) |-> !((axi_assert.psv_axi_cb.aw_addr) % (2**axi_assert.psv_axi_cb.aw_size)); + endproperty + + // check if The size of a write transfer does not exceed the width of the data interface (Section A3.4.1) + property AXI_ERRM_AWSIZE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (8 * (2**axi_assert.psv_axi_cb.aw_size) <= `UVMA_AXI_DATA_MAX_WIDTH); + endproperty + + // check if burst crosses 4KB boundaries (Section A3.4.1) + property AXI4_ERRM_AWADDR_BOUNDARY; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (((axi_assert.psv_axi_cb.aw_addr + (axi_assert.psv_axi_cb.aw_len + 1) * (2**axi_assert.psv_axi_cb.aw_size)) % 4096) > (axi_assert.psv_axi_cb.aw_addr % 4096)) || !((axi_assert.psv_axi_cb.aw_addr + (axi_assert.psv_axi_cb.aw_len + 1) * (2**axi_assert.psv_axi_cb.aw_size)) % 4096); + endproperty + + // Check if the burst length equal to 2, 4, 8, or 16, for wrapping bursts (Section A3.4.1) + property AXI_AWLEN_WRAPP_BURST; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.aw_valid && axi_assert.psv_axi_cb.aw_burst == 2'b10) |-> (axi_assert.psv_axi_cb.aw_len == 1) || (axi_assert.psv_axi_cb.aw_len == 3) || (axi_assert.psv_axi_cb.aw_len == 7) || (axi_assert.psv_axi_cb.aw_len == 15); + endproperty + + // Check if aw_burst can’t be 2’b11 (Table A3-3) + property AXI4_AW_BURST_CANT_2b11; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_valid |-> (axi_assert.psv_axi_cb.aw_burst != 2'b11); + endproperty + + // Check if AWVALID is LOW for the first cycle after ARESETn goes HIGH (Figure A3-1) + property AXI4_AWVALID_RESET; + @(posedge clk) $rose(rst_n) |=> !(axi_assert.psv_axi_cb.aw_valid); + endproperty + + // Check if the length of an exclusive access transaction don't pass 16 beats (Section A7.2.4) + property AXI4_AWLEN_LOCK; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.aw_lock |-> (signed'(axi_assert.psv_axi_cb.aw_len)) <= 16; + endproperty + + // Check if AWCACHE[3:2] are LOW, When AWVALID is HIGH and AWCACHE[1] is LOW (Table A4-5) + property AXI4_AWCACHE_LOW; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.aw_valid) && !(axi_assert.psv_axi_cb.aw_cache[1]) |-> !(axi_assert.psv_axi_cb.aw_cache[3:2]); + endproperty + + // Check if a transactions of burst type FIXED don't have a length greater than 16 beats (Section A3.4.1) + property AXI4_AWLEN_FIXED; + @(posedge clk) disable iff (!rst_n) (axi_assert.psv_axi_cb.aw_burst == 2'b00) |-> (axi_assert.psv_axi_cb.aw_len <= 15); + endproperty + +/********************************************** Assert Property ******************************************************/ + + aw_valid_aw_ready : assert property (AXI4_AW_VALID_READY) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AW_VALID_READY"); + + awaddr_wrap_align : assert property (AXI_AWADDR_WRAP_ALIGN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_AWADDR_WRAP_ALIGN"); + + assert_awsize : assert property (AXI_ERRM_AWSIZE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_ERRM_AWSIZE"); + + awlen_wrapp_burst : assert property (AXI_AWLEN_WRAPP_BURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI_AWLEN_WRAPP_BURST"); + + aw_burst_cant_2b11 : assert property (AXI4_AW_BURST_CANT_2b11) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AW_BURST_CANT_2b11"); + + errm_awaddr_boundary : assert property (AXI4_ERRM_AWADDR_BOUNDARY) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_ERRM_AWADDR_BOUNDARY"); + + awvalid_reset : assert property (AXI4_AWVALID_RESET) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWVALID_RESET"); + + awlen_lock : assert property (AXI4_AWLEN_LOCK) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLEN_LOCK"); + + awcahce_low : assert property (AXI4_AWCACHE_LOW) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWCACHE_LOW"); + + awlen_fixed : assert property (AXI4_AWLEN_FIXED) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLEN_FIXED"); + + awid_x : assert property (AXI4_AWID_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWID_X"); + + awaddr_x : assert property (AXI4_AWADDR_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWADDR_X"); + + awlen_x : assert property (AXI4_AWLEN_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLEN_X"); + + awsize_x : assert property (AXI4_AWSIZE_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWSIZE_X"); + + awburst_x : assert property (AXI4_AWBURST_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWBURST_X"); + + awlock_x : assert property (AXI4_AWLOCK_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLOCK_X"); + + awcache_x : assert property (AXI4_AWCACHE_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWCACHE_X"); + + awprot_x : assert property (AXI4_AWPROT_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWPROT_X"); + + awuser_x : assert property (AXI4_AWUSER_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWUSER_X"); + + awqos_x : assert property (AXI4_AWQOS_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWQOS_X"); + + awregion_x : assert property (AXI4_AWREGION_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWREGION_X"); + + awvalid_x : assert property (AXI4_AWVALID_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWVALID_X"); + + awready_x : assert property (AXI4_AWREADY_X) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWREADY_X"); + + awid_stable : assert property (AXI4_AWID_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWID_STABLE"); + + awaddr_stable : assert property (AXI4_AWADDR_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWADDR_STABLE"); + + awlen_stable : assert property (AXI4_AWLEN_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLEN_STABLE"); + + awsize_stable : assert property (AXI4_AWSIZE_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWSIZE_STABLE"); + + awburst_stable : assert property (AXI4_AWBURST_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWBURST_STABLE"); + + awlock_stable : assert property (AXI4_AWLOCK_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWLOCK_STABLE"); + + awcache_stable : assert property (AXI4_AWCACHE_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWCACHE_STABLE"); + + awprot_stable : assert property (AXI4_AWPROT_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWPROT_STABLE"); + + awuser_stable : assert property (AXI4_AWUSER_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWUSER_STABLE"); + + awqos_stable : assert property (AXI4_AWQOS_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWQOS_STABLE"); + + awregion_stable : assert property (AXI4_AWREGION_STABLE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_AWREGION_STABLE"); + +/********************************************** Cover Property ******************************************************/ + + cov_aw_valid_aw_ready : cover property(AXI4_AW_VALID_READY); + + cov_awaddr_wrap_align : cover property(AXI_AWADDR_WRAP_ALIGN); + + cov_awsize : cover property(AXI_ERRM_AWSIZE); + + cov_awvalid_reset : cover property(AXI4_AWVALID_RESET); + + cov_awlen_wrapp_burst : cover property(AXI_AWLEN_WRAPP_BURST); + + cov_aw_burst_cant_2b11 : cover property(AXI4_AW_BURST_CANT_2b11); + + cov_errm_awaddr_boundary : cover property(AXI4_ERRM_AWADDR_BOUNDARY); + + cov_awlen_lock : cover property(AXI4_AWLEN_LOCK); + + cov_awcache_low : cover property(AXI4_AWCACHE_LOW); + + cov_awlen_fixed : cover property(AXI4_AWLEN_FIXED); + + cov_awid_stable : cover property(AXI4_AWID_STABLE); + + cov_awaddr_stable : cover property(AXI4_AWADDR_STABLE); + + cov_awlen_stable : cover property(AXI4_AWLEN_STABLE); + + cov_awsize_stable : cover property(AXI4_AWSIZE_STABLE); + + cov_awburst_stable : cover property(AXI4_AWBURST_STABLE); + + cov_awlock_stable : cover property(AXI4_AWLOCK_STABLE); + + cov_awcache_stable : cover property(AXI4_AWCACHE_STABLE); + + cov_awprot_stable : cover property(AXI4_AWPROT_STABLE); + + cov_awuser_stable : cover property(AXI4_AWUSER_STABLE); + + cov_awqos_stable : cover property(AXI4_AWQOS_STABLE); + + cov_awregion_stable : cover property(AXI4_AWREGION_STABLE); + + +endmodule : uvma_axi_aw_assert diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_b_assert.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_b_assert.sv new file mode 100644 index 000000000..381fd3ae9 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_b_assert.sv @@ -0,0 +1,109 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// *************************** Write response CHANNEL ************************** // + +module uvma_axi_b_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + +// *************************** Check if Write Response Signals are not equal to X or Z when WVALID is HIGH (Section A3.2.2) ************************** // + + property AXI4_BID_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!$isunknown(axi_assert.psv_axi_cb.b_id)); + endproperty + + property AXI4_BRESP_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!$isunknown(axi_assert.psv_axi_cb.b_resp)); + endproperty + + property AXI4_BUSER_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!$isunknown(axi_assert.psv_axi_cb.b_user)); + endproperty + + // A value of X on BVALID is not permitted when not in reset (Section A3.2.2) + property AXI4_BVALID_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.b_valid)); + endproperty + + // A value of X on BVALID is not permitted when not in reset (Section A3.1.2) + property AXI4_BREADY_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.b_ready)); + endproperty + +// *************************** Check if Write Response Signals are stable when AWVALID is HIGH (Section A3.2.1) ************************** // + + property AXI4_BID_STABLE ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!axi_assert.psv_axi_cb.b_ready |=> ($stable(axi_assert.psv_axi_cb.b_id))); + endproperty + + property AXI4_BRESP_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!axi_assert.psv_axi_cb.b_ready |=> ($stable(axi_assert.psv_axi_cb.b_resp))); + endproperty + + property AXI4_BUSER_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> (!axi_assert.psv_axi_cb.b_ready |=> ($stable(axi_assert.psv_axi_cb.b_user))); + endproperty + + // Check if, Once asserted, r_valid must remain asserted until r_ready is HIGH (Section A3.2.2) + property AXI4_BVALID_STABLE ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.b_valid |-> ( axi_assert.psv_axi_cb.b_valid throughout (axi_assert.psv_axi_cb.b_ready [->1])); + endproperty + + // Check if RVALID is LOW for the first cycle after ARESETn goes HIGH (Figure A3-1) + property AXI4_BVALID_RESET; + @(posedge clk) $rose(rst_n) |=> !(axi_assert.psv_axi_cb.b_valid); + endproperty + +/********************************************** Assert Property ******************************************************/ + + rvalid_reset : assert property (AXI4_BVALID_RESET) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BVALID_RESET"); + + bid_x : assert property (AXI4_BID_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BID_X"); + + bresp_x : assert property (AXI4_BRESP_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BRESP_X"); + + buser_x : assert property (AXI4_BUSER_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BUSER_X"); + + bvalid_x : assert property (AXI4_BVALID_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BVALID_X"); + + bready_x : assert property (AXI4_BREADY_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BREADY_X"); + + bvalid_stable : assert property (AXI4_BVALID_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BVALID_STABLE"); + + bid_stable : assert property (AXI4_BID_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BID_STABLE"); + + bresp_stable : assert property (AXI4_BRESP_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BRESP_STABLE"); + + buser_stable : assert property (AXI4_BUSER_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_BUSER_STABLE"); + +/********************************************** Cover Property ******************************************************/ + + cov_bvalid_reset : cover property(AXI4_BVALID_RESET); + + cov_bvalid_stable : cover property(AXI4_BVALID_STABLE); + + cov_bid_stable : cover property(AXI4_BID_STABLE); + + cov_bresp_stable : cover property(AXI4_BRESP_STABLE); + + cov_buser_stable : cover property(AXI4_BUSER_STABLE); + +endmodule : uvma_axi_b_assert diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv index b06dc1b7b..5941d1fc8 100644 --- a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv @@ -20,6 +20,11 @@ // Interfaces / Modules / Checkers `include "uvma_axi_intf.sv" +`include "uvma_axi_aw_assert.sv" +`include "uvma_axi_w_assert.sv" +`include "uvma_axi_ar_assert.sv" +`include "uvma_axi_r_assert.sv" +`include "uvma_axi_b_assert.sv" package uvma_axi_pkg; diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_r_assert.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_r_assert.sv new file mode 100644 index 000000000..c475f0429 --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_r_assert.sv @@ -0,0 +1,141 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// *************************** READ DATA CHANNEL ************************** // + +module uvma_axi_r_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + +// *************************** Check if Read Signals are not equal X or Z when RVALID is HIGH (Section A3.2.2) ************************** // + + property AXI4_RID_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!$isunknown(axi_assert.psv_axi_cb.r_id)); + endproperty + + property AXI4_RDATA_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!$isunknown(axi_assert.psv_axi_cb.r_data)); + endproperty + + property AXI4_RRESP_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!$isunknown(axi_assert.psv_axi_cb.r_resp)); + endproperty + + property AXI4_RLAST_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!$isunknown(axi_assert.psv_axi_cb.r_last)); + endproperty + + property AXI4_RUSEr_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!$isunknown(axi_assert.psv_axi_cb.r_user)); + endproperty + +//A value of X on RVALID is not permitted when not in reset (Section A3.1.2) + property AXI4_RVALID_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.r_valid)); + endproperty + +//A value of X on RREADY is not permitted when not in reset (Section A3.1.2) + property AXI4_RREADY_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.r_ready)); + endproperty + +// *************************** Check if Read Signals are stable when AWVALID is HIGH (Section A3.2.1) ************************** // + property AXI4_RID_STABLE ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!axi_assert.psv_axi_cb.r_ready |=> ($stable(axi_assert.psv_axi_cb.r_id))); + endproperty + + property AXI4_RDATA_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!axi_assert.psv_axi_cb.r_ready |=> ($stable(axi_assert.psv_axi_cb.r_data))); + endproperty + + property AXI4_RRESP_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!axi_assert.psv_axi_cb.r_ready |=> ($stable(axi_assert.psv_axi_cb.r_resp))); + endproperty + + property AXI4_RLAST_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!axi_assert.psv_axi_cb.r_ready |=> ($stable(axi_assert.psv_axi_cb.r_last))); + endproperty + + property AXI4_RUSER_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> (!axi_assert.psv_axi_cb.r_ready |=> ($stable(axi_assert.psv_axi_cb.r_user))); + endproperty + + // Check if, Once asserted, r_valid must remain asserted until r_ready is HIGH (Section A3.2.1) + property AXI4_RVALID_STABLE ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.r_valid |-> ( axi_assert.psv_axi_cb.r_valid throughout (axi_assert.psv_axi_cb.r_ready [->1])); + endproperty + + // Check if RVALID is LOW for the first cycle after RESET goes HIGH (Figure A3-1) + property AXI4_RVALID_RESET; + @(posedge clk) $rose(rst_n) |=> !(axi_assert.psv_axi_cb.r_valid); + endproperty + +/********************************************** Assert Property ******************************************************/ + + rvalid_reset : assert property (AXI4_RVALID_RESET) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RVALID_RESET"); + + rid_x : assert property (AXI4_RID_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RID_X"); + + rdata_x : assert property (AXI4_RDATA_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RDATA_X"); + + rresp_x : assert property (AXI4_RRESP_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RRESP_X"); + + rlast_x : assert property (AXI4_RLAST_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RLAST_X"); + + rvalid_x : assert property (AXI4_RVALID_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RVALID_X"); + + rready_x : assert property (AXI4_RREADY_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RREADY_X"); + + rvalid_stable : assert property (AXI4_RVALID_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RVALID_STABLE"); + + rid_stable : assert property (AXI4_RID_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RID_STABLE"); + + rdata_stable : assert property (AXI4_RDATA_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RDATA_STABLE"); + + rresp_stable : assert property (AXI4_RRESP_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RRESP_STABLE"); + + rlast_stable : assert property (AXI4_RLAST_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RLAST_STABLE"); + + ruser_stable : assert property (AXI4_RUSER_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RUSEr_STABLE"); + +/********************************************** FAILED ******************************************************/ + /* ruser_x : assert property (AXI4_RUSEr_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_RUSEr_X");*/ + +/********************************************** Cover Property ******************************************************/ + + cov_rvalid_reset : cover property(AXI4_RVALID_RESET); + + cov_rvalid_stable : cover property(AXI4_RVALID_STABLE); + + cov_rid_stable : cover property(AXI4_RID_STABLE); + + cov_rdata_stable : cover property(AXI4_RDATA_STABLE); + + cov_rresp_stable : cover property(AXI4_RRESP_STABLE); + + cov_ruser_stable : cover property(AXI4_RUSER_STABLE); + + cov_rlast_stable : cover property(AXI4_RLAST_STABLE); + +endmodule : uvma_axi_r_assert diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_w_assert.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_w_assert.sv new file mode 100644 index 000000000..6aa5320bf --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_w_assert.sv @@ -0,0 +1,125 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) +// Co-Author: Abdelaali Khardazi + +// *************************** WRITE DATA CHANNEL ************************** // + +module uvma_axi_w_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + +// *************************** Check if Write Signals are not equal to X or Z when WVALID is HIGH (Section A3.2.2)************************** // + + property AXI4_WDATA_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!$isunknown(axi_assert.psv_axi_cb.w_data)); + endproperty + + property AXI4_WSTRB_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!$isunknown(axi_assert.psv_axi_cb.w_strb)); + endproperty + + property AXI4_WLAST_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!$isunknown(axi_assert.psv_axi_cb.w_last)); + endproperty + + property AXI4_WUSER_X; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!$isunknown(axi_assert.psv_axi_cb.w_user)); + endproperty + + // A value of X on WVALID is not permitted when not in reset (Section A3.1.2) + property AXI4_WVALID_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.w_valid)); + endproperty + + // A value of X on WREADY is not permitted when not in reset (Section A3.1.2) + property AXI4_WREADY_X; + @(posedge clk) disable iff (!rst_n) (!$isunknown(axi_assert.psv_axi_cb.w_ready)); + endproperty + +// *************************** Check if Write Signals are stable when AWVALID is HIGH (Section A3.2.1) ************************** // + + property AXI4_WDATA_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!axi_assert.psv_axi_cb.w_ready |=> ($stable(axi_assert.psv_axi_cb.w_data))); + endproperty + + property AXI4_WSTRB_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!axi_assert.psv_axi_cb.w_ready |=> ($stable(axi_assert.psv_axi_cb.w_strb))); + endproperty + + property AXI4_WLAST_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!axi_assert.psv_axi_cb.w_ready |=> ($stable(axi_assert.psv_axi_cb.w_last))); + endproperty + + property AXI4_WUSER_STABLE; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> (!axi_assert.psv_axi_cb.w_ready |=> ($stable(axi_assert.psv_axi_cb.w_user))); + endproperty + + // Check if, Once asserted, w_valid must remain asserted until w_ready is HIGH (Section A3.2.1) + property AXI4_WVALID_STABLE ; + @(posedge clk) disable iff (!rst_n) axi_assert.psv_axi_cb.w_valid |-> ( axi_assert.psv_axi_cb.w_valid throughout (axi_assert.psv_axi_cb.w_ready [->1])); + endproperty + + //Check if WVALID is LOW for the first cycle after ARESETn goes HIGH (Figure A3-1) + property AXI4_WVALID_RESET; + @(posedge clk) $rose(rst_n) |=> !(axi_assert.psv_axi_cb.w_valid); + endproperty + +/********************************************** Assert Property ******************************************************/ + + wvalid_reset : assert property (AXI4_WVALID_RESET) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WVALID_RESET"); + + wdata_x : assert property (AXI4_WDATA_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WDATA_X"); + + wstrb_x : assert property (AXI4_WSTRB_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WSTRB_X"); + + wlast_x : assert property (AXI4_WLAST_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WLAST_X"); + + wuser_x : assert property (AXI4_WUSER_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WUSER_X"); + + wvalid_x : assert property (AXI4_WVALID_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WVALID_X"); + + wready_x : assert property (AXI4_WREADY_X) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WREADY_X"); + + wvalid_stable : assert property (AXI4_WVALID_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WVALID_STABLE"); + + wdata_stable : assert property (AXI4_WDATA_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WDATA_STABLE"); + + wstrb_stable : assert property (AXI4_WSTRB_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WSTRB_STABLE"); + + wlast_stable : assert property (AXI4_WLAST_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WLAST_STABLE"); + + wuser_stable : assert property (AXI4_WUSER_STABLE) + else `uvm_error (" AXI4 protocol ckecks assertion ", "Violation of AXI4_WUSER_STABLE"); + +/********************************************** Cover Property ******************************************************/ + + cov_wvalid_reset : cover property(AXI4_WVALID_RESET); + + cov_wvalid_stable : cover property(AXI4_WVALID_STABLE); + + cov_wdata_stable : cover property(AXI4_WDATA_STABLE); + + cov_wstrb_stable : cover property(AXI4_WSTRB_STABLE); + + cov_wuser_stable : cover property(AXI4_WUSER_STABLE); + + cov_wlast_stable : cover property(AXI4_WLAST_STABLE); + +endmodule : uvma_axi_w_assert From aac24f0652782479c0982043de7f42f79854e721 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 1 Feb 2023 10:41:00 +0100 Subject: [PATCH 042/183] axi_agent: Bind assertions to the AXI interface in testbench Signed-off-by: Alae Eddine Ez zejjari --- cva6/tb/uvmt/uvmt_axi_assert.sv | 46 +++++++++++++++++++++++++++++++++ cva6/tb/uvmt/uvmt_cva6.flist | 2 ++ cva6/tb/uvmt/uvmt_cva6_tb.sv | 6 +++++ 3 files changed, 54 insertions(+) create mode 100644 cva6/tb/uvmt/uvmt_axi_assert.sv diff --git a/cva6/tb/uvmt/uvmt_axi_assert.sv b/cva6/tb/uvmt/uvmt_axi_assert.sv new file mode 100644 index 000000000..d61c27a78 --- /dev/null +++ b/cva6/tb/uvmt/uvmt_axi_assert.sv @@ -0,0 +1,46 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +module uvmt_axi_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + + + bind uvmt_axi_assert + uvma_axi_aw_assert axi_aw_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_ar_assert axi_ar_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_w_assert axi_w_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_r_assert axi_r_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_b_assert axi_b_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + +endmodule : uvmt_axi_assert diff --git a/cva6/tb/uvmt/uvmt_cva6.flist b/cva6/tb/uvmt/uvmt_cva6.flist index 0c04c48ad..f81101869 100644 --- a/cva6/tb/uvmt/uvmt_cva6.flist +++ b/cva6/tb/uvmt/uvmt_cva6.flist @@ -45,3 +45,5 @@ ${CVA6_UVMT_DIR}/uvmt_cva6_tb_ifs.sv ${CVA6_UVMT_DIR}/uvmt_cva6_tb.sv ${CVA6_UVMT_DIR}/uvmt_cva6_dut_wrap.sv ${CVA6_UVMT_DIR}/cva6_tb_wrapper.sv + +${CVA6_UVMT_DIR}/uvmt_axi_assert.sv diff --git a/cva6/tb/uvmt/uvmt_cva6_tb.sv b/cva6/tb/uvmt/uvmt_cva6_tb.sv index 8fedee7c1..393c2bf9c 100644 --- a/cva6/tb/uvmt/uvmt_cva6_tb.sv +++ b/cva6/tb/uvmt/uvmt_cva6_tb.sv @@ -58,6 +58,12 @@ module uvmt_cva6_tb; .clk(clknrst_if.clk), .reset_n(clknrst_if.reset_n) ); + //bind assertion module for axi interface + bind uvmt_cva6_dut_wrap + uvmt_axi_assert axi_assert(.axi_assert(axi_if.passive), + .clk(clknrst_if.clk), + .rst_n(clknrst_if.reset_n) + ); // DUT Wrapper Interfaces uvmt_rvfi_if rvfi_if( .rvfi_o() From 94fba13d3b31664ba531c8033ece86f728b17a92 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 1 Feb 2023 10:43:03 +0100 Subject: [PATCH 043/183] axi_agent: add assertions for CVA6 Signed-off-by: Alae Eddine Ez zejjari --- cva6/tb/uvmt/uvmt_axi_assert.sv | 6 + cva6/tb/uvmt/uvmt_cva6.flist | 1 + cva6/tb/uvmt/uvmt_cva6_axi_assert.sv | 187 +++++++++++++++++++++++++++ 3 files changed, 194 insertions(+) create mode 100644 cva6/tb/uvmt/uvmt_cva6_axi_assert.sv diff --git a/cva6/tb/uvmt/uvmt_axi_assert.sv b/cva6/tb/uvmt/uvmt_axi_assert.sv index d61c27a78..843153cdf 100644 --- a/cva6/tb/uvmt/uvmt_axi_assert.sv +++ b/cva6/tb/uvmt/uvmt_axi_assert.sv @@ -42,5 +42,11 @@ module uvmt_axi_assert (uvma_axi_intf.passive axi_assert, input bit clk, input .rst_n(rst_n) ); + bind uvmt_axi_assert + uvmt_cva6_axi_assert cva6_axi_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + endmodule : uvmt_axi_assert diff --git a/cva6/tb/uvmt/uvmt_cva6.flist b/cva6/tb/uvmt/uvmt_cva6.flist index f81101869..a805b6b3a 100644 --- a/cva6/tb/uvmt/uvmt_cva6.flist +++ b/cva6/tb/uvmt/uvmt_cva6.flist @@ -47,3 +47,4 @@ ${CVA6_UVMT_DIR}/uvmt_cva6_dut_wrap.sv ${CVA6_UVMT_DIR}/cva6_tb_wrapper.sv ${CVA6_UVMT_DIR}/uvmt_axi_assert.sv +${CVA6_UVMT_DIR}/uvmt_cva6_axi_assert.sv diff --git a/cva6/tb/uvmt/uvmt_cva6_axi_assert.sv b/cva6/tb/uvmt/uvmt_cva6_axi_assert.sv new file mode 100644 index 000000000..749d79d38 --- /dev/null +++ b/cva6/tb/uvmt/uvmt_cva6_axi_assert.sv @@ -0,0 +1,187 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +// *************************** AXI features supported by CVA6 ************************** // + +module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + + + //check if the CVA6 identify read transaction with an ID equal to 0 or 1 + property AXI4_CVA6_ARID; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_id == 0 || axi_assert.ar_id == 1; + endproperty + + //check if the CVA6 identify write transaction with an ID equal to 0 or 1 + property AXI4_CVA6_AWID; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_id == 1; + endproperty + + //Check if user-defined extension for read address channel is equal to 0b00 + property AXI4_CVA6_ARUSER; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_user == 0; + endproperty + + //Check if user-defined extension for write address channel is equal to 0b00 + property AXI4_CVA6_AWUSER; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_user == 0; + endproperty + + //Check if Quality of Service identifier for write transaction is equal to 0b0000 + property AXI4_CVA6_AWQOS; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_qos == 0; + endproperty + + //Check if Quality of Service identifier for read transaction is equal to 0b0000 + property AXI4_CVA6_ARQOS; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_qos == 0; + endproperty + + //Check if Region indicator for write transaction is equal to 0b0000 + property AXI4_CVA6_AWREGION; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_region == 0; + endproperty + + //Check if Region indicator for read transaction is equal to 0b0000 + property AXI4_CVA6_ARREGION; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_region == 0; + endproperty + + //Check if AWCACHE is always equal to 0b0000 + property AXI4_CVA6_AWCACHE; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_cache == 0; + endproperty + + //Check if ARCACHE is always equal to 0b0000 + property AXI4_CVA6_ARCACHE; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_cache == 0; + endproperty + + //Check if Protection attributes for write transaction always take the 0b000 + property AXI4_CVA6_AWPROT; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_prot == 0; + endproperty + + //Check if Protection attributes for read transaction always take the 0b000 + property AXI4_CVA6_ARPROT; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_prot == 0; + endproperty + + //Check if all write transaction performed by CVA6 are of type INCR + property AXI4_CVA6_AWBURST; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_burst == 1; + endproperty + + //Check if all read transaction performed by CVA6 are of type INCR + property AXI4_CVA6_ARBURST; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_burst == 1; + endproperty + + //Check if all write transaction performed by CVA6 are equal to 0 or 1 + property AXI4_CVA6_AWLEN; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_len == 0; + endproperty + + //Check if all Read transaction performed by CVA6 are equal to 0 or 1 + property AXI4_CVA6_ARLEN; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_len == 1; + endproperty + +/********************************************** Assert Property ******************************************************/ + + cva6_arid : assert property (AXI4_CVA6_ARID) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARID"); + + cva6_awid : assert property (AXI4_CVA6_AWID) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWID"); + + cva6_aruser : assert property (AXI4_CVA6_ARUSER) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARUSER"); + + cva6_awuser : assert property (AXI4_CVA6_AWUSER) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWUSER"); + + cva6_arqos : assert property (AXI4_CVA6_ARQOS) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARQOS"); + + cva6_awqos : assert property (AXI4_CVA6_AWQOS) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWQOS"); + + cva6_arregion : assert property (AXI4_CVA6_ARREGION) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARREGION"); + + cva6_awregion : assert property (AXI4_CVA6_AWREGION) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWREGION"); + + cva6_arcache : assert property (AXI4_CVA6_ARCACHE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARCAHCE"); + + cva6_awcache : assert property (AXI4_CVA6_AWCACHE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWCAHCE"); + + cva6_arprot : assert property (AXI4_CVA6_ARPROT) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARPROT"); + + cva6_awprot : assert property (AXI4_CVA6_AWPROT) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWPROT"); + + cva6_arburst : assert property (AXI4_CVA6_ARBURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARBURST"); + + cva6_awburst : assert property (AXI4_CVA6_AWBURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWBURST"); + + cva6_arlen : assert property (AXI4_CVA6_ARLEN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARLEN"); + + cva6_awlen : assert property (AXI4_CVA6_AWLEN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWLEN"); + +/********************************************** Cover Property ******************************************************/ + + + cov_cva6_arid : cover property(AXI4_CVA6_ARID); + + cov_cva6_awid : cover property(AXI4_CVA6_AWID); + + cov_cva6_aruser : cover property(AXI4_CVA6_ARUSER); + + cov_cva6_awuser : cover property(AXI4_CVA6_AWUSER); + + cov_cva6_arqos : cover property(AXI4_CVA6_ARQOS); + + cov_cva6_awqos : cover property(AXI4_CVA6_AWQOS); + + cov_cva6_arregion : cover property(AXI4_CVA6_ARREGION); + + cov_cva6_awregion : cover property(AXI4_CVA6_AWREGION); + + cov_cva6_arcache : cover property(AXI4_CVA6_ARCACHE); + + cov_cva6_awcache : cover property(AXI4_CVA6_AWCACHE); + + cov_cva6_arprot : cover property(AXI4_CVA6_ARPROT); + + cov_cva6_awprot : cover property(AXI4_CVA6_AWPROT); + + cov_cva6_arburst : cover property(AXI4_CVA6_ARBURST); + + cov_cva6_awburst : cover property(AXI4_CVA6_AWBURST); + + cov_cva6_arlen : cover property(AXI4_CVA6_ARLEN); + + cov_cva6_awlen : cover property(AXI4_CVA6_AWLEN); + + + + +endmodule : uvmt_cva6_axi_assert + + From 89897bd8a95436088deed9f8e56a46cdaac9627d Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Thu, 8 Dec 2022 16:32:10 +0100 Subject: [PATCH 044/183] axi_agent: Add transaction logger module Signed-off-by: Alae Eddine Ez zejjari --- .../uvma_axi/src/comps/uvma_axi_agent.sv | 16 ++ .../uvma_axi_ar_agent/uvma_axi_ar_mon.sv | 14 + .../uvma_axi_aw_agent/uvma_axi_aw_mon.sv | 14 + .../comps/uvma_axi_b_agent/uvma_axi_b_mon.sv | 13 + .../comps/uvma_axi_r_agent/uvma_axi_r_mon.sv | 15 ++ .../src/comps/uvma_axi_seq_item_logger.sv | 246 ++++++++++++++++++ .../comps/uvma_axi_w_agent/uvma_axi_w_mon.sv | 14 + .../uvma_axi/src/obj/uvma_axi_cfg.sv | 1 + .../src/seq/uvma_axi_base_seq_item.sv | 94 +++++++ lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv | 6 + 10 files changed, 433 insertions(+) create mode 100644 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_seq_item_logger.sv create mode 100644 lib/uvm_agents/uvma_axi/src/seq/uvma_axi_base_seq_item.sv diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv index b3652b533..cc3630b27 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_agent.sv @@ -24,6 +24,8 @@ class uvma_axi_agent_c extends uvm_agent; uvma_axi_r_agent_c r_agent; uvma_axi_vsqr_c vsequencer; + uvma_axi_seq_item_logger_c seq_item_logger; + uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; @@ -83,6 +85,7 @@ class uvma_axi_agent_c extends uvm_agent; this.b_agent = uvma_axi_b_agent_c :: type_id :: create("b_agent", this); this.ar_agent = uvma_axi_ar_agent_c :: type_id :: create("ar_agent", this); this.r_agent = uvma_axi_r_agent_c :: type_id :: create("r_agent", this); + this.seq_item_logger = uvma_axi_seq_item_logger_c::type_id::create("seq_item_logger", this); if( cfg.is_active == UVM_ACTIVE) begin vsequencer = uvma_axi_vsqr_c::type_id::create("sequencer", this); end @@ -99,6 +102,10 @@ class uvma_axi_agent_c extends uvm_agent; `uvm_info(get_type_name(), $sformatf("PASSIVE MODE"), UVM_LOW) end + if (cfg.trn_log_enabled) begin + connect_trn_loggers(); + end + endfunction function void connect_mon_2_sqr(); @@ -133,6 +140,15 @@ class uvma_axi_agent_c extends uvm_agent; endfunction: assemble_vsequencer + function void connect_trn_loggers(); + + this.aw_agent.monitor.aw_mon2log_port.connect(seq_item_logger.analysis_export); + this.w_agent.monitor.w_mon2log_port.connect(seq_item_logger.analysis_export); + this.b_agent.monitor.b_mon2log_port.connect(seq_item_logger.analysis_export); + this.ar_agent.monitor.ar_mon2log_port.connect(seq_item_logger.analysis_export); + this.r_agent.monitor.r_mon2log_port.connect(seq_item_logger.analysis_export); + + endfunction : connect_trn_loggers endclass : uvma_axi_agent_c diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv index f9d81b746..482b44884 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_ar_agent/uvma_axi_ar_mon.sv @@ -18,8 +18,10 @@ class uvma_axi_ar_mon_c extends uvm_monitor; uvma_axi_ar_item_c ar_item; uvma_axi_ar_item_c ardrv_item; + uvma_axi_base_seq_item_c transaction; uvm_analysis_port#(uvma_axi_ar_item_c) uvma_ar_mon_port; uvm_analysis_port#(uvma_axi_ar_item_c) uvma_ar_mon2drv_port; + uvm_analysis_port#(uvma_axi_base_seq_item_c) ar_mon2log_port; uvma_axi_cfg_c cfg; uvma_axi_cntxt_c cntxt; @@ -31,6 +33,7 @@ class uvma_axi_ar_mon_c extends uvm_monitor; super.new(name, parent); this.uvma_ar_mon_port = new("uvma_ar_mon_port", this); this.uvma_ar_mon2drv_port = new("uvma_ar_mon2drv_port", this); + this.ar_mon2log_port = new("ar_mon2log_port", this); endfunction function void build_phase(uvm_phase phase); @@ -46,6 +49,7 @@ class uvma_axi_ar_mon_c extends uvm_monitor; ar_item = uvma_axi_ar_item_c::type_id::create("ar_item", this); ardrv_item = uvma_axi_ar_item_c::type_id::create("ardrv_item", this); + transaction = uvma_axi_base_seq_item_c::type_id::create("transaction", this); void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin @@ -104,6 +108,16 @@ class uvma_axi_ar_mon_c extends uvm_monitor; this.uvma_ar_mon2drv_port.write(this.ardrv_item); end this.uvma_ar_mon_port.write(this.ar_item); + + this.transaction.ar_id = passive_mp.psv_axi_cb.ar_id; + this.transaction.ar_addr = passive_mp.psv_axi_cb.ar_addr; + this.transaction.ar_valid = passive_mp.psv_axi_cb.ar_valid; + this.transaction.ar_ready = passive_mp.psv_axi_cb.ar_ready; + this.transaction.ar_lock = passive_mp.psv_axi_cb.ar_lock; + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.ar_mon2log_port.write(transaction); + end + @(passive_mp.psv_axi_cb); end endtask: monitor_ar_items diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv index e861b4b34..e9c2ada2e 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_aw_agent/uvma_axi_aw_mon.sv @@ -21,9 +21,11 @@ class uvma_axi_aw_mon_c extends uvm_monitor; uvma_axi_aw_item_c aw_item; uvma_axi_aw_item_c awdrv_item; + uvma_axi_base_seq_item_c transaction; uvm_analysis_port #(uvma_axi_aw_item_c) uvma_aw_mon_port; uvm_analysis_port #(uvma_axi_aw_item_c) uvma_aw_mon2drv_port; + uvm_analysis_port#(uvma_axi_base_seq_item_c) aw_mon2log_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; @@ -33,6 +35,7 @@ class uvma_axi_aw_mon_c extends uvm_monitor; super.new(name, parent); this.uvma_aw_mon_port = new("uvma_aw_mon_port", this); this.uvma_aw_mon2drv_port = new("uvma_aw_mon2drv_port", this); + this.aw_mon2log_port = new("aw_mon2log_port", this); endfunction function void build_phase(uvm_phase phase); @@ -49,6 +52,7 @@ class uvma_axi_aw_mon_c extends uvm_monitor; this.aw_item = uvma_axi_aw_item_c::type_id::create("aw_item", this); this.awdrv_item = uvma_axi_aw_item_c::type_id::create("awdrv_item", this); + this.transaction = uvma_axi_base_seq_item_c::type_id::create("transaction", this); void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin @@ -118,6 +122,16 @@ class uvma_axi_aw_mon_c extends uvm_monitor; end this.uvma_aw_mon_port.write(this.aw_item); + + this.transaction.aw_id = passive_mp.psv_axi_cb.aw_id; + this.transaction.aw_addr = passive_mp.psv_axi_cb.aw_addr; + this.transaction.aw_valid = passive_mp.psv_axi_cb.aw_valid; + this.transaction.aw_ready = passive_mp.psv_axi_cb.aw_ready; + this.transaction.aw_lock = passive_mp.psv_axi_cb.aw_lock; + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.aw_mon2log_port.write(this.transaction); + end + @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv index 97b0212e6..39159b94b 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_b_agent/uvma_axi_b_mon.sv @@ -22,9 +22,11 @@ class uvma_axi_b_mon_c extends uvm_monitor; uvma_axi_b_item_c b_item; uvma_axi_b_item_c bdrv_item; + uvma_axi_base_seq_item_c transaction; uvm_analysis_port #(uvma_axi_b_item_c) uvma_b_mon_port; uvm_analysis_port #(uvma_axi_b_item_c) uvma_b_mon2drv_port; + uvm_analysis_port#(uvma_axi_base_seq_item_c) b_mon2log_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; @@ -40,6 +42,7 @@ function uvma_axi_b_mon_c::new(string name = "uvma_axi_b_mon_c", uvm_component p super.new(name, parent); this.uvma_b_mon_port = new("uvma_b_mon_port", this); this.uvma_b_mon2drv_port = new("uvma_b_mon2drv_port", this); + this.b_mon2log_port = new("b_mon2log_port", this); endfunction function void uvma_axi_b_mon_c::build_phase(uvm_phase phase); @@ -61,6 +64,7 @@ function void uvma_axi_b_mon_c::build_phase(uvm_phase phase); this.b_item = uvma_axi_b_item_c::type_id::create("b_item", this); this.bdrv_item = uvma_axi_b_item_c::type_id::create("bdrv_item", this); + this.transaction = uvma_axi_base_seq_item_c::type_id::create("transaction", this); endfunction:build_phase @@ -91,6 +95,15 @@ task uvma_axi_b_mon_c::monitor_b_items(); this.bdrv_item.b_ready = vif.b_ready; this.uvma_b_mon2drv_port.write(this.bdrv_item); end + + this.transaction.b_id = passive_mp.psv_axi_cb.b_id; + this.transaction.b_resp = passive_mp.psv_axi_cb.b_resp; + this.transaction.b_valid = passive_mp.psv_axi_cb.b_valid; + this.transaction.b_ready = passive_mp.psv_axi_cb.b_ready; + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.b_mon2log_port.write(transaction); + end + @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv index 14a4ae81e..34a14a3a9 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_r_agent/uvma_axi_r_mon.sv @@ -22,9 +22,11 @@ class uvma_axi_r_mon_c extends uvm_monitor; uvma_axi_r_item_c r_item; uvma_axi_r_item_c rdrv_item; + uvma_axi_base_seq_item_c transaction; uvm_analysis_port #(uvma_axi_r_item_c) uvma_r_mon_port; uvm_analysis_port #(uvma_axi_r_item_c) uvma_r_mon2drv_port; + uvm_analysis_port#(uvma_axi_base_seq_item_c) r_mon2log_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; @@ -43,6 +45,7 @@ function uvma_axi_r_mon_c::new(string name = "uvma_axi_r_mon_c", uvm_component p super.new(name, parent); uvma_r_mon_port = new("uvma_r_mon_port", this); uvma_r_mon2drv_port = new("uvma_r_mon2drv_port", this); + r_mon2log_port = new("r_mon2log_port", this); endfunction @@ -64,6 +67,7 @@ function void uvma_axi_r_mon_c::build_phase(uvm_phase phase); this.r_item = uvma_axi_r_item_c::type_id::create("r_item", this); this.rdrv_item = uvma_axi_r_item_c::type_id::create("rdrv_item", this); + this.transaction = uvma_axi_base_seq_item_c::type_id::create("transaction", this); endfunction @@ -103,6 +107,17 @@ task uvma_axi_r_mon_c::monitor_r_items(); this.rdrv_item.r_ready = vif.r_ready; this.uvma_r_mon2drv_port.write(this.rdrv_item); end + + this.transaction.r_id = passive_mp.psv_axi_cb.r_id; + this.transaction.r_data = passive_mp.psv_axi_cb.r_data; + this.transaction.r_valid = passive_mp.psv_axi_cb.r_valid; + this.transaction.r_ready = passive_mp.psv_axi_cb.r_ready; + this.transaction.r_resp = passive_mp.psv_axi_cb.r_resp; + this.transaction.r_last = passive_mp.psv_axi_cb.r_last; + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + this.r_mon2log_port.write(transaction); + end + @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_seq_item_logger.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_seq_item_logger.sv new file mode 100644 index 000000000..4748c276e --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_seq_item_logger.sv @@ -0,0 +1,246 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + + +`ifndef __UVMA_AXI_SEQ_ITEM_LOGGER_SV__ +`define __UVMA_AXI_SEQ_ITEM_LOGGER_SV__ + + +/** + * Component writing Open Bus Interface sequence items debug data to disk as plain text. + */ +class uvma_axi_seq_item_logger_c extends uvml_logs_seq_item_logger_c #( + .T_TRN (uvma_axi_base_seq_item_c), + .T_CFG (uvma_axi_cfg_c ), + .T_CNTXT(uvma_axi_cntxt_c ) +); + + `uvm_component_utils(uvma_axi_seq_item_logger_c) + + + /** + * Default constructor. + */ + function new(string name="uvma_axi_seq_item_logger", uvm_component parent=null); + super.new(name, parent); + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_axi_base_seq_item_c trs); + if(cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET)begin + + string write_address_access = ""; + string aw_access_type = ""; + string aw_address = ""; + string aw_id_str = ""; + + string write_data_access = ""; + string w_data = ""; + string w_access_complet = ""; + + string write_response_access = ""; + string b_err = ""; + string b_id_str = ""; + + string read_address_access = ""; + string ar_access_type = ""; + string ar_address = ""; + string ar_id_str = ""; + + string read_data_access = ""; + string r_err = ""; + string r_data = ""; + string r_id_str = ""; + string r_access_complet = ""; + + if(trs.aw_valid && trs.aw_ready) begin + + write_address_access = "write_address_access"; + if(trs.aw_lock) begin + aw_access_type = "Exclusive_access"; + end else begin + aw_access_type = "Normal_access"; + end + aw_address = $sformatf("%h", trs.aw_addr); + aw_id_str = $sformatf("%b", trs.aw_id); + fwrite($sformatf("----> %t | %s | %s | %s | %s", $realtime(), write_address_access, aw_address, aw_access_type, aw_id_str)); + + end else begin + + write_address_access = ""; + aw_access_type = ""; + aw_address = ""; + aw_id_str = ""; + + end + + if(trs.w_valid && trs.w_ready) begin + + write_data_access = "write_data_access"; + w_data = $sformatf("%h", trs.w_data); + if(trs.w_last) begin + w_access_complet = "Yes"; + end else begin + w_access_complet = "No"; + end + fwrite($sformatf("----> %t | %s | %s | %s", $realtime(), write_data_access, w_data, w_access_complet)); + + end else begin + + write_data_access = ""; + w_data = ""; + w_access_complet = ""; + + end + + if(trs.b_valid && trs.b_ready) begin + + write_response_access = "write_response_access"; + case (trs.b_resp) + 00 : b_err = "No Err"; + 01 : b_err = "Err"; + 10 : b_err = "Err"; + 11 : b_err = "Err"; + default : b_err = " ? "; + endcase + b_id_str = $sformatf("%b", trs.b_id); + fwrite($sformatf("----> %t | %s | __ | %s | __ | %s", $realtime(), write_response_access, b_id_str, b_err)); + + end else begin + + write_response_access = ""; + b_err = ""; + b_id_str = ""; + + end + + if(trs.ar_valid && trs.ar_ready) begin + + read_address_access = "read_address_access"; + if(trs.ar_lock) begin + ar_access_type = "Exclusive_access"; + end else begin + ar_access_type = "Normal_access"; + end + ar_address = $sformatf("%h", trs.ar_addr); + ar_id_str = $sformatf("%b", trs.ar_id); + fwrite($sformatf("----> %t | %s | %s | %s | %s", $realtime(), read_address_access, ar_address, ar_access_type, ar_id_str)); + + end else begin + + read_address_access = ""; + ar_address = ""; + ar_access_type = ""; + ar_id_str = ""; + + end + + if(trs.r_valid && trs.r_ready) begin + + read_data_access = "read_data_access"; + r_data = $sformatf("%h", trs.r_data); + r_id_str = $sformatf("%b", trs.r_id); + if(trs.r_last) begin + r_access_complet = "Yes"; + end else begin + r_access_complet = "No"; + end + case (trs.r_resp) + 00 : r_err = "No Err"; + 01 : r_err = "Err"; + 10 : r_err = "Err"; + 11 : r_err = "Err"; + default : r_err = " ? "; + endcase + fwrite($sformatf("----> %t | %s | %s | %s | %s | %s", $realtime(), read_data_access, r_data, r_access_complet, r_id_str, r_err)); + + end else begin + + read_data_access = ""; + r_data = ""; + r_access_complet = ""; + r_err = ""; + r_id_str = ""; + + end + end + endfunction : write + +// A significant chunk of the write_mstr method is common between this +// sequence item logger and the monitor transaction logger. Given that +// much of this code is template generated, and is not expected to be edited +// further, the duplicated code has a lint waiver. +// +//@DVT_LINTER_WAIVER_START "MT20210901_2" disable SVTB.33.1.0, SVTB.33.2.0 + /** + * Writes contents of mstr t to disk. + */ + + /** + * Writes log header to disk. + */ + virtual function void print_header(); + + fwrite("-------------------------------------------------------------------------------------------"); + fwrite(" TIME | AW/W/B/AR/R | ADDRESS : AW/AR | ACCESS TYPE : AW/AR | ID | ERR : B/R "); + fwrite(" TIME | ACCESS | DATA : W/R | LAST DATA : W/R | | "); + fwrite("-------------------------------------------------------------------------------------------"); + + endfunction : print_header + +endclass : uvma_axi_seq_item_logger_c + +/** + * Component writing Open Bus Interface monitor transactions debug data to disk as JavaScript Object Notation (JSON). + */ +class uvma_axi_seq_item_logger_json_c extends uvma_axi_seq_item_logger_c; + + `uvm_component_utils(uvma_axi_seq_item_logger_json_c) + + /** + * Set file extension to '.json'. + */ + function new(string name="uvma_axi_seq_item_logger_json", uvm_component parent=null); + + super.new(name, parent); + fextension = "json"; + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_axi_base_seq_item_c t); + + // TODO Implement uvma_obi_memory_seq_item_logger_json_c::write() + // Ex: fwrite({"{", + // $sformatf("\"time\":\"%0t\",", $realtime()), + // $sformatf("\"a\":%h," , t.a ), + // $sformatf("\"b\":%b," , t.b ), + // $sformatf("\"c\":%d," , t.c ), + // $sformatf("\"d\":%h," , t.c ), + // "},"}); + + endfunction : write + + /** + * Empty function. + */ + virtual function void print_header(); + + // Do nothing: JSON files do not use headers. + + endfunction : print_header + +endclass : uvma_axi_seq_item_logger_json_c + + +`endif // __UVMA_AXI_SEQ_ITEM_LOGGER_SV__ diff --git a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv index 4ee256077..055add481 100644 --- a/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv +++ b/lib/uvm_agents/uvma_axi/src/comps/uvma_axi_w_agent/uvma_axi_w_mon.sv @@ -22,9 +22,11 @@ class uvma_axi_w_mon_c extends uvm_monitor; uvma_axi_w_item_c w_item; uvma_axi_w_item_c wdrv_item; + uvma_axi_base_seq_item_c transaction; uvm_analysis_port #(uvma_axi_w_item_c) uvma_w_mon_port; uvm_analysis_port #(uvma_axi_w_item_c) uvma_w_mon2drv_port; + uvm_analysis_port#(uvma_axi_base_seq_item_c) w_mon2log_port; // Handles to virtual interface modport virtual uvma_axi_intf.passive passive_mp; @@ -42,6 +44,7 @@ function uvma_axi_w_mon_c::new(string name = "uvma_axi_w_mon_c", uvm_component p super.new(name, parent); uvma_w_mon_port = new("uvma_w_mon_port", this); uvma_w_mon2drv_port = new("uvma_w_mon2drv_port", this); + w_mon2log_port = new("w_mon2log_port", this); endfunction @@ -59,6 +62,7 @@ function void uvma_axi_w_mon_c::build_phase(uvm_phase phase); w_item = uvma_axi_w_item_c::type_id::create("w_item", this); wdrv_item = uvma_axi_w_item_c::type_id::create("wdrv_item", this); + transaction = uvma_axi_base_seq_item_c::type_id::create("transaction", this); void'(uvm_config_db#(uvma_axi_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin @@ -82,6 +86,7 @@ task uvma_axi_w_mon_c::monitor_w_items(); w_item.w_user = passive_mp.psv_axi_cb.w_user; w_item.w_valid = passive_mp.psv_axi_cb.w_valid; w_item.w_ready = passive_mp.psv_axi_cb.w_ready; + if(cfg.is_active) begin // collect AR signals this.wdrv_item.w_strb = vif.w_strb; @@ -93,6 +98,15 @@ task uvma_axi_w_mon_c::monitor_w_items(); this.uvma_w_mon2drv_port.write(this.wdrv_item); end this.uvma_w_mon_port.write(this.w_item); + + this.transaction.w_valid = passive_mp.psv_axi_cb.w_valid; + this.transaction.w_ready = passive_mp.psv_axi_cb.w_ready; + this.transaction.w_data = passive_mp.psv_axi_cb.w_data; + this.transaction.w_last = passive_mp.psv_axi_cb.w_last; + if( cntxt.reset_state == UVMA_AXI_RESET_STATE_POST_RESET) begin + w_mon2log_port.write(transaction); + end + @(passive_mp.psv_axi_cb); end diff --git a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv index 033a56682..ac2c7d253 100644 --- a/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv +++ b/lib/uvm_agents/uvma_axi/src/obj/uvma_axi_cfg.sv @@ -15,6 +15,7 @@ class uvma_axi_cfg_c extends uvm_object; rand uvm_active_passive_enum is_active; + rand bit trn_log_enabled; rand uvma_axi_drv_slv_mode_enum drv_slv_mode; rand uvma_axi_drv_slv_err_mode_enum drv_slv_err_mode; diff --git a/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_base_seq_item.sv b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_base_seq_item.sv new file mode 100644 index 000000000..33941fb7a --- /dev/null +++ b/lib/uvm_agents/uvma_axi/src/seq/uvma_axi_base_seq_item.sv @@ -0,0 +1,94 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + + +`ifndef __UVMA_AXI_BASE_SEQ_ITEM_SV__ +`define __UVMA_AXI_BASE_SEQ_ITEM_SV__ + + +/** + * Object created by Open Bus Interface agent sequences extending uvma_obi_memory_seq_base_c. + */ +class uvma_axi_base_seq_item_c extends uvml_trn_seq_item_c; + + rand logic ar_valid; + rand logic ar_ready; + rand logic ar_lock; + rand logic [AXI_ID_WIDTH-1:0] ar_id; + rand logic [AXI_ADDR_WIDTH-1:0] ar_addr; + rand logic [AXI_ID_WIDTH-1:0] r_id; + rand logic [AXI_ADDR_WIDTH-1:0] r_data; + rand logic r_last; + rand logic r_valid; + logic r_ready; + rand logic [1:0] r_resp; + + rand logic aw_valid; + rand logic aw_ready; + rand logic aw_lock; + rand logic [AXI_ID_WIDTH-1:0] aw_id; + rand logic [AXI_ADDR_WIDTH-1:0] aw_addr; + rand logic [AXI_DATA_WIDTH-1:0] w_data; + rand logic w_last; + rand logic w_valid; + rand logic w_ready; + rand logic [AXI_ID_WIDTH-1:0] b_id; + rand logic [1:0] b_resp; + rand logic b_valid; + rand logic b_ready; + + + // Metadata + uvma_axi_cfg_c cfg; ///< Handle to agent's configuration object + + `uvm_object_utils_begin(uvma_axi_base_seq_item_c) + `uvm_field_int(aw_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_addr, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(aw_lock, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_data, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_last, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(w_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_resp, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(b_ready, UVM_ALL_ON | UVM_NOPACK); + + `uvm_field_int(ar_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_addr, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(ar_lock, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_id, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_data, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_resp, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_last, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_valid, UVM_ALL_ON | UVM_NOPACK); + `uvm_field_int(r_ready, UVM_ALL_ON | UVM_NOPACK); + `uvm_object_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_axi_base_seq_item"); + +endclass : uvma_axi_base_seq_item_c + + +function uvma_axi_base_seq_item_c::new(string name="uvma_axi_base_seq_item"); + + super.new(name); + +endfunction : new + + +`endif // __UVMA_AXI_BASE_SEQ_ITEM_SV__ + diff --git a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv index 5941d1fc8..2d748b14c 100644 --- a/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv +++ b/lib/uvm_agents/uvma_axi/src/uvma_axi_pkg.sv @@ -30,6 +30,9 @@ package uvma_axi_pkg; import uvm_pkg::*; import uvml_mem_pkg ::*; + import uvml_trn_pkg ::*; + import uvml_logs_pkg ::*; + import "DPI-C" function read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function void read_section(input longint address, inout byte buffer[]); @@ -49,6 +52,7 @@ package uvma_axi_pkg; `include "uvma_axi_cfg.sv" `include "uvma_axi_cntxt.sv" + `include "uvma_axi_base_seq_item.sv" `include "uvma_axi_aw_item.sv" `include "uvma_axi_w_item.sv" `include "uvma_axi_b_item.sv" @@ -72,6 +76,8 @@ package uvma_axi_pkg; `include "uvma_axi_ar_sqr.sv" `include "uvma_axi_r_sqr.sv" + `include "uvma_axi_seq_item_logger.sv" + `include "uvma_axi_aw_agent.sv" `include "uvma_axi_w_agent.sv" `include "uvma_axi_b_agent.sv" From 5bf7d87205c4422b76f4ab397312a53785826358 Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Wed, 1 Feb 2023 10:46:37 +0100 Subject: [PATCH 045/183] axi_agent: activation of the transaction log Signed-off-by: Alae Eddine Ez zejjari --- cva6/env/uvme/uvme_cva6_cfg.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/cva6/env/uvme/uvme_cva6_cfg.sv b/cva6/env/uvme/uvme_cva6_cfg.sv index 6065c43e8..726de70ea 100644 --- a/cva6/env/uvme/uvme_cva6_cfg.sv +++ b/cva6/env/uvme/uvme_cva6_cfg.sv @@ -79,6 +79,7 @@ class uvme_cva6_cfg_c extends uvm_object; if (trn_log_enabled) { clknrst_cfg.trn_log_enabled == 1; + axi_cfg.trn_log_enabled == 1; } if (cov_model_enabled) { From bc1cd9cd9933c2af56277ad5063f136bb1209588 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Tue, 21 Feb 2023 10:42:56 +0100 Subject: [PATCH 046/183] Core cntrl Agent : Add a constraint related to boot_addr value Signed-off-by: Ayoub Jalali --- lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv index 6f660257f..afb160d1d 100644 --- a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv +++ b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv @@ -205,6 +205,10 @@ } } + constraint boot_addr_cons { //boot addr should be half-word aligned + boot_addr % 2 == 0; + } + /** * Creates sub-configuration objects. */ From 1a995eee8e3dacbf1510df5ae372fe684fd78516 Mon Sep 17 00:00:00 2001 From: ajalali Date: Thu, 23 Feb 2023 17:37:20 +0100 Subject: [PATCH 047/183] Re-use Core control Agent Signed-off-by: ajalali --- cva6/env/uvme/uvma_cva6_core_cntrl_agent.sv | 114 ++++++++++++++++++++ cva6/env/uvme/uvma_cva6_core_cntrl_cntxt.sv | 51 +++++++++ cva6/env/uvme/uvma_cva6_core_cntrl_drv.sv | 62 +++++++++++ cva6/env/uvme/uvme_cva6_cfg.sv | 94 +++++++++++++++- cva6/env/uvme/uvme_cva6_cntxt.sv | 3 + cva6/env/uvme/uvme_cva6_constants.sv | 2 + cva6/env/uvme/uvme_cva6_core_cntrl_if.sv | 31 ++++++ cva6/env/uvme/uvme_cva6_env.sv | 5 +- cva6/env/uvme/uvme_cva6_pkg.sv | 7 +- cva6/sim/Makefile | 1 + cva6/tb/uvmt/cva6_tb_wrapper.sv | 7 +- cva6/tb/uvmt/uvmt_cva6.flist | 1 + cva6/tb/uvmt/uvmt_cva6_constants.sv | 1 + cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv | 2 + cva6/tb/uvmt/uvmt_cva6_tb.sv | 5 + 15 files changed, 378 insertions(+), 8 deletions(-) create mode 100644 cva6/env/uvme/uvma_cva6_core_cntrl_agent.sv create mode 100644 cva6/env/uvme/uvma_cva6_core_cntrl_cntxt.sv create mode 100644 cva6/env/uvme/uvma_cva6_core_cntrl_drv.sv create mode 100644 cva6/env/uvme/uvme_cva6_core_cntrl_if.sv diff --git a/cva6/env/uvme/uvma_cva6_core_cntrl_agent.sv b/cva6/env/uvme/uvma_cva6_core_cntrl_agent.sv new file mode 100644 index 000000000..21e3c0dcf --- /dev/null +++ b/cva6/env/uvme/uvma_cva6_core_cntrl_agent.sv @@ -0,0 +1,114 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ +`define __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ + +/** + * Core control agent defined for the CVA6 + */ +class uvma_cva6_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; + + + string log_tag = "CVA6CORECTRLAGT"; + + `uvm_component_utils_begin(uvma_cva6_core_cntrl_agent_c) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_cva6_core_cntrl_agent", uvm_component parent=null); + + /** + * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. + */ + extern virtual function void get_and_set_cntxt(); + + /** + * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this + * agent. + */ + extern virtual function void retrieve_vif(); + + /** + * Spawn active sequnces + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Spawn fetch enable control sequence + */ + extern virtual task start_fetch_toggle_seq(); + +endclass : uvma_cva6_core_cntrl_agent_c + +function uvma_cva6_core_cntrl_agent_c::new(string name="uvma_cva6_core_cntrl_agent", uvm_component parent=null); + + super.new(name, parent); + + set_inst_override_by_type("driver", uvma_core_cntrl_drv_c::get_type(), uvma_cva6_core_cntrl_drv_c::get_type()); + +endfunction : new + +function void uvma_cva6_core_cntrl_agent_c::retrieve_vif(); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + $cast(cva6_cntxt, cntxt); + + // Core control interface + if (!uvm_config_db#(virtual uvme_cva6_core_cntrl_if)::get(this, "", $sformatf("core_cntrl_vif"), cva6_cntxt.core_cntrl_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", + $typename(cva6_cntxt.core_cntrl_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", + $typename(cva6_cntxt.core_cntrl_vif)), UVM_DEBUG) + end +endfunction : retrieve_vif + +function void uvma_cva6_core_cntrl_agent_c::get_and_set_cntxt(); + + void'(uvm_config_db#(uvma_core_cntrl_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_info(log_tag, "Context handle is null; creating", UVM_LOW); + cntxt = uvma_cva6_core_cntrl_cntxt_c::type_id::create("cntxt"); + end + + uvm_config_db#(uvma_core_cntrl_cntxt_c)::set(this, "*", "cntxt", cntxt); + +endfunction : get_and_set_cntxt + +task uvma_cva6_core_cntrl_agent_c::run_phase(uvm_phase phase); + + if (cfg.is_active) begin + fork + start_fetch_toggle_seq(); + join_none + end + +endtask : run_phase + +task uvma_cva6_core_cntrl_agent_c::start_fetch_toggle_seq(); + + `uvm_error(log_tag, "fetch toggle not supported in CVA6"); + +endtask : start_fetch_toggle_seq + +`endif // __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ diff --git a/cva6/env/uvme/uvma_cva6_core_cntrl_cntxt.sv b/cva6/env/uvme/uvma_cva6_core_cntrl_cntxt.sv new file mode 100644 index 000000000..0973c58e3 --- /dev/null +++ b/cva6/env/uvme/uvma_cva6_core_cntrl_cntxt.sv @@ -0,0 +1,51 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ +`define __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ + + +/** + * Object encapsulating all state variables for all Rvvi agent + * (uvma_core_cntrl_agent_c) components. + */ + class uvma_cva6_core_cntrl_cntxt_c extends uvma_core_cntrl_cntxt_c; + + virtual uvme_cva6_core_cntrl_if core_cntrl_vif; + + `uvm_object_utils_begin(uvma_cva6_core_cntrl_cntxt_c) + `uvm_object_utils_end + + /** + * Builds events. + */ + extern function new(string name="uvma_cva6_core_cntrl_cntxt"); + +endclass : uvma_cva6_core_cntrl_cntxt_c + +`pragma protect begin + +function uvma_cva6_core_cntrl_cntxt_c::new(string name="uvma_cva6_core_cntrl_cntxt"); + + super.new(name); + +endfunction : new + +`pragma protect end + + +`endif // __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ diff --git a/cva6/env/uvme/uvma_cva6_core_cntrl_drv.sv b/cva6/env/uvme/uvma_cva6_core_cntrl_drv.sv new file mode 100644 index 000000000..5c6a37bd9 --- /dev/null +++ b/cva6/env/uvme/uvma_cva6_core_cntrl_drv.sv @@ -0,0 +1,62 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`ifndef __UVMA_CVA6_CORE_CNTRL_DRV_SV__ +`define __UVMA_CVA6_CORE_CNTRL_DRV_SV__ + +/** + * Component driving bootstrap pins and other misecllaneous I/O for cva6 core + */ +class uvma_cva6_core_cntrl_drv_c extends uvma_core_cntrl_drv_c; + + `uvm_component_utils_begin(uvma_cva6_core_cntrl_drv_c) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_cva6_core_cntrl_drv", uvm_component parent=null); + + extern task drive_bootstrap(); + +endclass : uvma_cva6_core_cntrl_drv_c + +function uvma_cva6_core_cntrl_drv_c::new(string name="uvma_cva6_core_cntrl_drv", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + +task uvma_cva6_core_cntrl_drv_c::drive_bootstrap(); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + $cast(cva6_cntxt, cntxt); + + cva6_cntxt.core_cntrl_vif.boot_addr = cfg.boot_addr; + cva6_cntxt.core_cntrl_vif.nmi_addr = cfg.nmi_addr; + cva6_cntxt.core_cntrl_vif.mtvec_addr = cfg.mtvec_addr; + cva6_cntxt.core_cntrl_vif.dm_halt_addr = cfg.dm_halt_addr; + cva6_cntxt.core_cntrl_vif.dm_exception_addr = cfg.dm_exception_addr; + cva6_cntxt.core_cntrl_vif.mhartid = cfg.mhartid; + cva6_cntxt.core_cntrl_vif.mimpid = cfg.mimpid; + cva6_cntxt.core_cntrl_vif.fetch_en = 1'b0; + cva6_cntxt.core_cntrl_vif.scan_cg_en = 1'b0; + +endtask : drive_bootstrap + +`endif // __UVMA_CVA6_CORE_CNTRL_DRV_SV__ diff --git a/cva6/env/uvme/uvme_cva6_cfg.sv b/cva6/env/uvme/uvme_cva6_cfg.sv index 726de70ea..36a0e7c18 100644 --- a/cva6/env/uvme/uvme_cva6_cfg.sv +++ b/cva6/env/uvme/uvme_cva6_cfg.sv @@ -26,11 +26,10 @@ * Object encapsulating all parameters for creating, connecting and running * CVA6 environment (uvme_cva6_env_c) components. */ -class uvme_cva6_cfg_c extends uvm_object; +class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; // Integrals rand bit enabled; - rand uvm_active_passive_enum is_active; rand bit scoreboarding_enabled; rand bit cov_model_enabled; @@ -61,13 +60,68 @@ class uvme_cva6_cfg_c extends uvm_object; constraint defaults_cons { soft enabled == 0; - soft is_active == UVM_PASSIVE; + soft is_active == UVM_ACTIVE; soft scoreboarding_enabled == 1; soft cov_model_enabled == 1; soft trn_log_enabled == 1; soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv } + constraint cva6_riscv_cons { + xlen == uvma_core_cntrl_pkg::MXL_32; + ilen == 32; + + ext_i_supported == 1; + ext_a_supported == 0; + ext_m_supported == 1; + ext_c_supported == 1; + ext_p_supported == 0; + ext_v_supported == 0; + ext_f_supported == 0; + ext_d_supported == 0; + ext_zba_supported == 0; + ext_zbb_supported == 0; + ext_zbc_supported == 0; + ext_zbe_supported == 0; + ext_zbf_supported == 0; + ext_zbm_supported == 0; + ext_zbp_supported == 0; + ext_zbr_supported == 0; + ext_zbs_supported == 0; + ext_zbt_supported == 0; + ext_zifencei_supported == 1; + ext_zicsr_supported == 1; + + mode_s_supported == 0; + mode_u_supported == 0; + + pmp_supported == 0; + debug_supported == 1; + + unaligned_access_supported == 1; + unaligned_access_amo_supported == 0; + + bitmanip_version == BITMANIP_VERSION_1P00; + priv_spec_version == PRIV_VERSION_MASTER; + endianness == ENDIAN_LITTLE; + + boot_addr_valid == 1; + mtvec_addr_valid == 1; + dm_halt_addr_valid == 1; + dm_exception_addr_valid == 1; + nmi_addr_valid == 1; + } + + constraint default_cva6_boot_cons { + (!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000); + (!mimpid_plusarg_valid) -> (mimpid == 'h0000_0000); + (!boot_addr_plusarg_valid) -> (boot_addr == 'h8000_0000); + (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); + (!nmi_addr_plusarg_valid) -> (nmi_addr == 'h0000_0000); + (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h0000_0000); + (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h0000_0000); + } + constraint agent_cfg_cons { if (enabled) { clknrst_cfg.enabled == 1; @@ -93,6 +147,11 @@ class uvme_cva6_cfg_c extends uvm_object; */ extern function new(string name="uvme_cva6_cfg"); + /** + * Sample the parameters of the DUT via the virtual interface in a context + */ + extern virtual function void sample_parameters(uvma_core_cntrl_cntxt_c cntxt); + endclass : uvme_cva6_cfg_c @@ -106,5 +165,34 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg"); endfunction : new +function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + if (!$cast(cva6_cntxt, cntxt)) begin + `uvm_fatal("SAMPLECNTXT", "Could not cast cntxt to uvma_cva6_core_cntrl_cntxt_c"); + end + + + num_mhpmcounters = cva6_cntxt.core_cntrl_vif.num_mhpmcounters; + // TODO : Check PMA + //~ pma_regions = new[cva6_cntxt.core_cntrl_vif.pma_cfg.size()]; + + //~ foreach (pma_regions[i]) begin + //~ pma_regions[i] = uvma_core_cntrl_pma_region_c::type_id::create($sformatf("pma_region%0d", i)); + //~ pma_regions[i].word_addr_low = cva6_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_low; + //~ pma_regions[i].word_addr_high = cva6_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_high; + //~ pma_regions[i].main = cva6_cntxt.core_cntrl_vif.pma_cfg[i].main; + //~ pma_regions[i].bufferable = core_cntrl_vif.pma_cfg[i].bufferable; + //~ pma_regions[i].cacheable = core_cntrl_vif.pma_cfg[i].cacheable; + //~ pma_regions[i].atomic = core_cntrl_vif.pma_cfg[i].atomic; + //~ end + + //~ // Copy to the pma_configuration + //~ pma_cfg.regions = new[pma_regions.size()]; + //~ foreach (pma_cfg.regions[i]) + //~ pma_cfg.regions[i] = pma_regions[i]; + +endfunction : sample_parameters `endif // __UVME_CVA6_CFG_SV__ diff --git a/cva6/env/uvme/uvme_cva6_cntxt.sv b/cva6/env/uvme/uvme_cva6_cntxt.sv index 5a4433661..01ea415f0 100644 --- a/cva6/env/uvme/uvme_cva6_cntxt.sv +++ b/cva6/env/uvme/uvme_cva6_cntxt.sv @@ -31,6 +31,7 @@ class uvme_cva6_cntxt_c extends uvm_object; uvma_clknrst_cntxt_c clknrst_cntxt; uvma_cvxif_cntxt_c cvxif_cntxt; uvma_axi_cntxt_c axi_cntxt; + uvma_cva6_core_cntrl_cntxt_c core_cntrl_cntxt; // Memory modelling rand uvml_mem_c mem; @@ -43,6 +44,7 @@ class uvme_cva6_cntxt_c extends uvm_object; `uvm_object_utils_begin(uvme_cva6_cntxt_c) `uvm_field_object(clknrst_cntxt, UVM_DEFAULT) `uvm_field_object(axi_cntxt, UVM_DEFAULT) + `uvm_field_object(core_cntrl_cntxt, UVM_DEFAULT) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) `uvm_field_object(mem, UVM_DEFAULT) @@ -65,6 +67,7 @@ function uvme_cva6_cntxt_c::new(string name="uvme_cva6_cntxt"); super.new(name); clknrst_cntxt = uvma_clknrst_cntxt_c::type_id::create("clknrst_cntxt"); + core_cntrl_cntxt = uvma_cva6_core_cntrl_cntxt_c::type_id::create("core_cntrl_cntxt"); axi_cntxt = uvma_axi_cntxt_c::type_id::create("axi_cntxt"); mem = uvml_mem_c::type_id::create("mem"); diff --git a/cva6/env/uvme/uvme_cva6_constants.sv b/cva6/env/uvme/uvme_cva6_constants.sv index 083a2296d..c77ec8374 100644 --- a/cva6/env/uvme/uvme_cva6_constants.sv +++ b/cva6/env/uvme/uvme_cva6_constants.sv @@ -24,5 +24,7 @@ parameter uvme_cva6_sys_default_clk_period = 1_500; // 10ns parameter uvme_cva6_debug_default_clk_period = 10_000; // 10ns +parameter XLEN = 32; +parameter ILEN = 32; `endif // __UVME_CVA6_CONSTANTS_SV__ diff --git a/cva6/env/uvme/uvme_cva6_core_cntrl_if.sv b/cva6/env/uvme/uvme_cva6_core_cntrl_if.sv new file mode 100644 index 000000000..e8e32e340 --- /dev/null +++ b/cva6/env/uvme/uvme_cva6_core_cntrl_if.sv @@ -0,0 +1,31 @@ +/** + * Quasi-static core control signals. + */ +interface uvme_cva6_core_cntrl_if + import uvm_pkg::*; + import uvme_cva6_pkg::*; + (); + + logic clk; + logic fetch_en; + + logic scan_cg_en; + logic [XLEN-1:0] boot_addr; + logic [XLEN-1:0] mtvec_addr; + logic [XLEN-1:0] dm_halt_addr; + logic [XLEN-1:0] dm_exception_addr; + logic [XLEN-1:0] nmi_addr; + logic [XLEN-1:0] mhartid; + logic [XLEN-1:0] mimpid; + + logic [XLEN-1:0] num_mhpmcounters; + //~ pma_region_t pma_cfg[]; + + // Testcase asserts this to load memory (not really a core control signal) + logic load_instr_mem; + + clocking drv_cb @(posedge clk); + output fetch_en; + endclocking : drv_cb + +endinterface : uvme_cva6_core_cntrl_if diff --git a/cva6/env/uvme/uvme_cva6_env.sv b/cva6/env/uvme/uvme_cva6_env.sv index 008abaa12..b22e45ff6 100644 --- a/cva6/env/uvme/uvme_cva6_env.sv +++ b/cva6/env/uvme/uvme_cva6_env.sv @@ -42,7 +42,7 @@ class uvme_cva6_env_c extends uvm_env; uvma_clknrst_agent_c clknrst_agent; uvma_cvxif_agent_c cvxif_agent; uvma_axi_agent_c axi_agent; - + uvma_cva6_core_cntrl_agent_c core_cntrl_agent; `uvm_component_utils_begin(uvme_cva6_env_c) @@ -205,6 +205,8 @@ function void uvme_cva6_env_c::assign_cfg(); uvm_config_db#(uvma_axi_cfg_c)::set(this, "*axi_agent", "cfg", cfg.axi_cfg); + uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "core_cntrl_agent", "cfg", cfg); + endfunction: assign_cfg @@ -222,6 +224,7 @@ function void uvme_cva6_env_c::create_agents(); clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); cvxif_agent = uvma_cvxif_agent_c::type_id::create("cvxif_agent", this); axi_agent = uvma_axi_agent_c::type_id::create("axi_agent", this); + core_cntrl_agent = uvma_cva6_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this); endfunction: create_agents diff --git a/cva6/env/uvme/uvme_cva6_pkg.sv b/cva6/env/uvme/uvme_cva6_pkg.sv index 52876c643..8415dd058 100644 --- a/cva6/env/uvme/uvme_cva6_pkg.sv +++ b/cva6/env/uvme/uvme_cva6_pkg.sv @@ -45,12 +45,14 @@ package uvme_cva6_pkg; import uvma_cvxif_pkg::*; import uvma_axi_pkg::*; import uvml_mem_pkg ::*; + import uvma_core_cntrl_pkg::*; // Constants / Structs / Enums `include "uvme_cva6_constants.sv" `include "uvme_cva6_tdefs.sv" // Objects + `include "uvma_cva6_core_cntrl_cntxt.sv" `include "uvme_cva6_cfg.sv" `include "uvme_cva6_cntxt.sv" @@ -58,6 +60,8 @@ package uvme_cva6_pkg; `include "uvme_cva6_prd.sv" // Environment components + `include "uvma_cva6_core_cntrl_drv.sv" + `include "uvma_cva6_core_cntrl_agent.sv" `include "uvme_cva6_sb.sv" `include "uvme_cva6_vsqr.sv" `include "uvme_cvxif_covg.sv" @@ -70,9 +74,8 @@ package uvme_cva6_pkg; // `include "uvme_cva6_interrupt_noise_vseq.sv" `include "uvme_cva6_vseq_lib.sv" - - endpackage : uvme_cva6_pkg +`include "uvme_cva6_core_cntrl_if.sv" `endif // __UVME_CVA6_PKG_SV__ diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index ffaa29f1b..27e7af7e8 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -137,6 +137,7 @@ export CV_CORE_UC = CVA6 export DV_UVMT_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt export DV_UVME_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt +export DV_UVMA_CORE_CNTRL_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_core_cntrl export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst export DV_UVMA_CVXIF_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_cvxif diff --git a/cva6/tb/uvmt/cva6_tb_wrapper.sv b/cva6/tb/uvmt/cva6_tb_wrapper.sv index c94be22f1..e0ad93203 100644 --- a/cva6/tb/uvmt/cva6_tb_wrapper.sv +++ b/cva6/tb/uvmt/cva6_tb_wrapper.sv @@ -34,7 +34,9 @@ import "DPI-C" function read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function void read_section(input longint address, inout byte buffer[]); -module cva6_tb_wrapper #( +module cva6_tb_wrapper + import uvmt_cva6_pkg::*; +#( parameter int unsigned AXI_USER_WIDTH = 1, parameter int unsigned AXI_USER_EN = 0, parameter int unsigned AXI_ADDRESS_WIDTH = 64, @@ -43,6 +45,7 @@ module cva6_tb_wrapper #( ) ( input logic clk_i, input logic rst_ni, + input logic [XLEN-1:0] boot_addr_i, output wire tb_exit_o, output ariane_rvfi_pkg::rvfi_port_t rvfi_o, input cvxif_pkg::cvxif_resp_t cvxif_resp, @@ -64,7 +67,7 @@ module cva6_tb_wrapper #( ) i_cva6 ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .boot_addr_i ( 64'h0000_0000_8000_0000 ), //ariane_soc::ROMBase + .boot_addr_i ( boot_addr_i ),//Driving the boot_addr value from the core control agent .hart_id_i ( 64'h0000_0000_0000_0000 ), .irq_i ( 2'b00 /*irqs*/ ), .ipi_i ( 1'b0 /*ipi*/ ), diff --git a/cva6/tb/uvmt/uvmt_cva6.flist b/cva6/tb/uvmt/uvmt_cva6.flist index a805b6b3a..7579275ec 100644 --- a/cva6/tb/uvmt/uvmt_cva6.flist +++ b/cva6/tb/uvmt/uvmt_cva6.flist @@ -25,6 +25,7 @@ -f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist -f ${DV_UVMA_CVXIF_PATH}/src/uvma_cvxif_pkg.flist -f ${DV_UVMA_AXI_PATH}/src/uvma_axi_pkg.flist +-f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist // Environments -f ${CVA6_UVME_PATH}/uvme_cva6_pkg.flist diff --git a/cva6/tb/uvmt/uvmt_cva6_constants.sv b/cva6/tb/uvmt/uvmt_cva6_constants.sv index fd7d19012..94d0f8e1a 100644 --- a/cva6/tb/uvmt/uvmt_cva6_constants.sv +++ b/cva6/tb/uvmt/uvmt_cva6_constants.sv @@ -19,5 +19,6 @@ `ifndef __UVMT_CVA6_CONSTANTS_SV__ `define __UVMT_CVA6_CONSTANTS_SV__ +parameter XLEN = 32; `endif // __UVMT_CVA6_CONSTANTS_SV__ diff --git a/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv b/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv index 973c8e7db..0d41676d8 100644 --- a/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv +++ b/cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -25,6 +25,7 @@ module uvmt_cva6_dut_wrap # ( parameter int unsigned AXI_USER_WIDTH = 1, uvma_clknrst_if clknrst_if, uvma_cvxif_intf cvxif_if, uvma_axi_intf axi_if, + uvme_cva6_core_cntrl_if core_cntrl_if, output wire tb_exit_o, output ariane_rvfi_pkg::rvfi_port_t rvfi_o ); @@ -41,6 +42,7 @@ module uvmt_cva6_dut_wrap # ( parameter int unsigned AXI_USER_WIDTH = 1, cva6_tb_wrapper_i ( .clk_i ( clknrst_if.clk ), .rst_ni ( clknrst_if.reset_n ), + .boot_addr_i ( core_cntrl_if.boot_addr ), .cvxif_resp ( cvxif_if.cvxif_resp_o ), .cvxif_req ( cvxif_if.cvxif_req_i ), .axi_slave ( axi_if ), diff --git a/cva6/tb/uvmt/uvmt_cva6_tb.sv b/cva6/tb/uvmt/uvmt_cva6_tb.sv index 393c2bf9c..b2d2ca1fd 100644 --- a/cva6/tb/uvmt/uvmt_cva6_tb.sv +++ b/cva6/tb/uvmt/uvmt_cva6_tb.sv @@ -51,6 +51,7 @@ module uvmt_cva6_tb; .clk(clknrst_if.clk), .rst_n(clknrst_if.reset_n) ); + uvme_cva6_core_cntrl_if core_cntrl_if(); //bind assertion module for cvxif interface bind uvmt_cva6_dut_wrap @@ -83,6 +84,7 @@ module uvmt_cva6_tb; .clknrst_if(clknrst_if), .cvxif_if (cvxif_if), .axi_if (axi_if), + .core_cntrl_if(core_cntrl_if), .tb_exit_o(), .rvfi_o(rvfi_if.rvfi_o) ); @@ -101,6 +103,7 @@ module uvmt_cva6_tb; uvm_config_db#(virtual uvma_cvxif_intf )::set(.cntxt(null), .inst_name("*.env.cvxif_agent"), .field_name("vif"), .value(cvxif_if) ); uvm_config_db#(virtual uvma_axi_intf )::set(.cntxt(null), .inst_name("*"), .field_name("axi_vif"), .value(axi_if)); uvm_config_db#(virtual uvmt_rvfi_if )::set(.cntxt(null), .inst_name("*"), .field_name("rvfi_vif"), .value(rvfi_if)); + uvm_config_db#(virtual uvme_cva6_core_cntrl_if)::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if)); // DUT and ENV parameters uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_ADDR_WIDTH"), .value(ENV_PARAM_INSTR_ADDR_WIDTH) ); @@ -113,6 +116,8 @@ module uvmt_cva6_tb; uvm_top.run_test(); end : test_bench_entry_point + assign core_cntrl_if.clk = clknrst_if.clk; + /** * End-of-test summary printout. */ From 2768a433ac49ba93f3ecd9035508495effcbb5e4 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Fri, 24 Feb 2023 17:42:13 +0100 Subject: [PATCH 048/183] [VPTOOL] Improve Python dependency handling, update DV plan launch scripts. * cva6/docs/VerifPlans/AXI/runme.sh: Call the VPTOOL shell wrapper. * cva6/docs/VerifPlans/CVXIF/runme.sh: Ditto. Pass cmdline options to shell wrapper. * cva6/docs/VerifPlans/FRONTEND/runme.sh: Call the VPTOOL shell wrapper. * cva6/docs/VerifPlans/ISA_RV32/runme.sh: Ditto. * cva6/docs/VerifPlans/install-prerequisites.sh: Use 'requirements.txt' and PIP to install Python dependencies. * tools/vptool/README.md: Update wrt. new Yaml library. Update name of the README file. * tools/vptool/vptool.sh: New shell wrapper to transparently handle Python dependencies. * tools/vptool/vptool/requirements.txt: New. * tools/vptool/vptool/vp.py (toplevel): Remove unused PyYaml imports. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/AXI/runme.sh | 2 +- cva6/docs/VerifPlans/CVXIF/runme.sh | 2 +- cva6/docs/VerifPlans/FRONTEND/runme.sh | 2 +- cva6/docs/VerifPlans/ISA_RV32/runme.sh | 2 +- cva6/docs/VerifPlans/install-prerequisites.sh | 4 +-- tools/vptool/README.md | 5 ++-- tools/vptool/vptool.sh | 29 +++++++++++++++++++ tools/vptool/vptool/requirements.txt | 3 ++ tools/vptool/vptool/vp.py | 5 ---- 9 files changed, 40 insertions(+), 14 deletions(-) create mode 100644 tools/vptool/vptool.sh create mode 100644 tools/vptool/vptool/requirements.txt diff --git a/cva6/docs/VerifPlans/AXI/runme.sh b/cva6/docs/VerifPlans/AXI/runme.sh index b0cfce34d..e2cfd351f 100644 --- a/cva6/docs/VerifPlans/AXI/runme.sh +++ b/cva6/docs/VerifPlans/AXI/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/CVXIF/runme.sh b/cva6/docs/VerifPlans/CVXIF/runme.sh index f1be65625..1701a0ebe 100644 --- a/cva6/docs/VerifPlans/CVXIF/runme.sh +++ b/cva6/docs/VerifPlans/CVXIF/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/FRONTEND/runme.sh b/cva6/docs/VerifPlans/FRONTEND/runme.sh index fb0023f98..b808624f8 100644 --- a/cva6/docs/VerifPlans/FRONTEND/runme.sh +++ b/cva6/docs/VerifPlans/FRONTEND/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index 0af7efb8d..5c581f0d5 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/cva6/docs/VerifPlans/install-prerequisites.sh b/cva6/docs/VerifPlans/install-prerequisites.sh index 65a4d5642..f73a1fc76 100644 --- a/cva6/docs/VerifPlans/install-prerequisites.sh +++ b/cva6/docs/VerifPlans/install-prerequisites.sh @@ -10,9 +10,7 @@ # Make sure all necessary components are installed/available. # # Install Python dependencies. -for REQT in `cat requirements.txt` ; do - python3 -m pip install $REQT -done +python3 -m pip install -q -r $(dirname $(readlink -f $0))/requirements.txt # Check for a LaTeX installation. which latex > /dev/null || { \ diff --git a/tools/vptool/README.md b/tools/vptool/README.md index be78643b5..21adccb57 100644 --- a/tools/vptool/README.md +++ b/tools/vptool/README.md @@ -39,7 +39,8 @@ If you encounter a problem with VPTOOL, please open an issue on this repository use `sudo apt-get install python3-tk`. On RedHat-based systems (RedHat/CentOS/Fedora), use `sudo dnf install python3-tkinter` or `sudo yum install python3-tkinter`, as appropriate. -* PyYAML: a YAML I/O library for Python. Install using `pip3 install --upgrade pyyaml`. +* Ruamel YAML: a YAML I/O library for Python with round-trip parse/unparse capabilities. + Install using `pip3 install --upgrade ruamel.yaml`. * Pillow: A replacement for the original PIL (Python Image Library). Install using `pip3 install --upgrade pillow`. @@ -86,7 +87,7 @@ shell script named `vptool-example.sh` which can be invoked from any location. ### Directory structure -- VPTOOL-readme.txt this file +- README.md this file - vptool the code of `VPTOOL` - vptool-example an example of `VPTOOL` configuration with a verification database - runme.sh a shell script to run `VPTOOL` with the example database diff --git a/tools/vptool/vptool.sh b/tools/vptool/vptool.sh new file mode 100644 index 000000000..bf453ca16 --- /dev/null +++ b/tools/vptool/vptool.sh @@ -0,0 +1,29 @@ +############################################################################# +# Copyright (C) 2023 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Set the canonical path of the current script. +VPTOOL_DIR=$(dirname $(readlink -f $0)) + +# Install any missing dependencies. +# - check if tkinter module is available (its installation requires super-user privileges.) +# If not, provide installation hints. +echo "import tkinter" | python3 || \ +{ + echo "*** Missing system-wide dependency: Python3 module 'tkinter' not installed." + echo "*** Please ask your administrator to install the required package:" + echo "*** - Debian, Ubuntu: 'python3-tk'" + echo "*** - RedHat EL, CentOS, Fedora: 'python3-tkinter'" + exit 1; +} + +# - install Python3 required modules in user space. +python3 -m pip install -q -r $VPTOOL_DIR/vptool/requirements.txt + +# Run VPTOOL with the arguments as supplied by the caller. +python3 $VPTOOL_DIR/vptool/vp.py $* diff --git a/tools/vptool/vptool/requirements.txt b/tools/vptool/vptool/requirements.txt new file mode 100644 index 000000000..c024b2c62 --- /dev/null +++ b/tools/vptool/vptool/requirements.txt @@ -0,0 +1,3 @@ +ruamel.yaml>=0.16 +pillow +ttkthemes diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index 03047594b..b0efb3ae3 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -39,11 +39,6 @@ from PIL import Image, ImageTk import shutil import hashlib -try: - from yaml import CLoader as Loader, CDumper as Dumper -except ImportError: - from yaml import Loader, Dumper - global ip_list # Dict Containing IPs->Prop->item. Eventually, it contains the whole DB global MASTER_LABEL_COLOR, SECONDARY_LABEL_COLOR, TERTIARY_LABEL_COLOR, BG_COLOR, LOCK_COLOR global CUSTOM_NUM From b9c4f99ebad4a20cb824855967d095041fd201fc Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 27 Feb 2023 12:18:55 +0100 Subject: [PATCH 049/183] Improve handling of dependencies for publishing VPTOOL verification plans. * cva6/docs/VerifPlans/install-prerequisites.sh: Improve invocation from arbitrary directories>. Add better diagnostics. Add final success msg. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/install-prerequisites.sh | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/cva6/docs/VerifPlans/install-prerequisites.sh b/cva6/docs/VerifPlans/install-prerequisites.sh index f73a1fc76..b8f169bb7 100644 --- a/cva6/docs/VerifPlans/install-prerequisites.sh +++ b/cva6/docs/VerifPlans/install-prerequisites.sh @@ -9,17 +9,29 @@ ############################################################################# # Make sure all necessary components are installed/available. # -# Install Python dependencies. +# Install Python dependencies. We can extract the full path of the script only +# when invoked using '$SHELL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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Context Info:
- loaded run directory
  /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default

model files
  domain : hdl
    /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default/icc_59a3d6de_075288d4.ucm

ucds files
  domain : hdl
    /scratch/strichmo/corev/covg/201102/cv32_full_covg_no_pulp.strichmo.20_11_02_16_01_37_7059/default/icc_59a3d6de_075288d4.ucd

loaded refinements
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.auto.vRefine
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.manual.vRefine
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/cv32e40p_no_pulp.hierarchy.vRefine

ccf files
  /scratch/strichmo/corev/core-v-verif/cv32/sim/tools/xrun/covfile.tcl
    # ----------------------------------------------------------------------------------
    # General coverage configuration options
    # ----------------------------------------------------------------------------------
    
    # Setting Constant Object Marking and enabling log for it
    set_com -log
    
    # Disable scoring of implicit else and default case blocks
    set_implicit_block_scoring -off
    
    # Remove empty instances from coverage hierarchy
    deselect_coverage -remove_empty_instances
    
    # Enable resilience from code changes
    set_refinement_resilience
    
    # Improve expression coverage performance
    set_optimize -vlog_prune_on
    
    # Set glitch strobes
    set_glitch_strobe 1ps
    
    # ----------------------------------------------------------------------------------
    # Expression coverage configuration
    # ----------------------------------------------------------------------------------
    
    # Setting expression scoring for all operators (not only boolean (|| &&) and VHDL (AND OR NOR NAND)
    set_expr_scoring -all
    
    # ----------------------------------------------------------------------------------
    # Toggle coverage configuration
    # ----------------------------------------------------------------------------------
    
    # Toggle coverage smart refinement (refinement for toggle with traverse hierarchy)
    set_toggle_smart_refinement

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Version: IMC: 20.07-a001: (c) Copyright 1995-2020 Cadence Design Systems Inc

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Metrics tree View Name: CV32E40P

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Block View Name: Uncovered

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Expression View Name: Uncovered

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FSM View Name: FSM

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Cover group View Name: CoverGroups

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Assertion View Name: Assertions

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-} - -table.treetable tr.expanded.selected span.indenter a { - background-image: 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-} - -table.treetable tr.accept { - background-color: #a3bce4; - color: #fff -} - -table.treetable tr.collapsed.accept td span.indenter a { - background-image: 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-} - -table.treetable tr.expanded.accept td span.indenter a { - background-image: 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-} - -#main { - background: #fff; - border-left: 20px solid #eee; - border-right: 20px solid #eee; - margin: 0 auto; - max-width: 800px; - padding: 20px; -} diff --git a/docs/Reports/cv32e40p/2020-11-02/resources/jquery.js b/docs/Reports/cv32e40p/2020-11-02/resources/jquery.js deleted file mode 100644 index 4b57db620..000000000 --- a/docs/Reports/cv32e40p/2020-11-02/resources/jquery.js +++ /dev/null @@ -1,12696 +0,0 @@ - -/*! - * jQuery JavaScript Library v1.10.2 - * http://jquery.com/ - * - * Includes Sizzle.js - * http://sizzlejs.com/ - * - * Copyright 2005, 2013 jQuery Foundation, Inc. and other contributors - * Released under the MIT license - * http://jquery.org/license - * - * Date: 2013-07-03T13:48Z - */ -(function( window, undefined ) { - -// Can't do this because several apps including ASP.NET trace -// the stack via arguments.caller.callee and Firefox dies if -// you try to trace through "use strict" call chains. (#13335) -// Support: Firefox 18+ -//"use strict"; -var - // The deferred used on DOM ready - readyList, - - // A central reference to the root jQuery(document) - rootjQuery, - - // Support: IE<10 - // For `typeof xmlNode.method` instead of `xmlNode.method !== undefined` - core_strundefined = typeof undefined, - - // Use the correct document accordingly with window argument (sandbox) - location = window.location, - document = window.document, - docElem = document.documentElement, - - // Map over jQuery in case of overwrite - _jQuery = window.jQuery, - - // Map over the $ in case of overwrite - _$ = window.$, - - // [[Class]] -> type pairs - class2type = {}, - - // List of deleted data cache ids, so we can reuse them - core_deletedIds = [], - - core_version = "1.10.2", - - // Save a reference to some core methods - core_concat = core_deletedIds.concat, - core_push = core_deletedIds.push, - core_slice = core_deletedIds.slice, - core_indexOf = core_deletedIds.indexOf, - core_toString = class2type.toString, - core_hasOwn = class2type.hasOwnProperty, - core_trim = core_version.trim, - - // Define a local copy of jQuery - jQuery = function( selector, context ) { - // The jQuery object is actually just the init constructor 'enhanced' - return new jQuery.fn.init( selector, context, rootjQuery ); - }, - - // Used for matching numbers - core_pnum = /[+-]?(?:\d*\.|)\d+(?:[eE][+-]?\d+|)/.source, - - // Used for splitting on whitespace - core_rnotwhite = /\S+/g, - - // Make sure we trim BOM and NBSP (here's looking at you, Safari 5.0 and IE) - rtrim = /^[\s\uFEFF\xA0]+|[\s\uFEFF\xA0]+$/g, - - // A simple way to check for HTML strings - // Prioritize #id over to avoid XSS via location.hash (#9521) - // Strict HTML recognition (#11290: must start with <) - rquickExpr = /^(?:\s*(<[\w\W]+>)[^>]*|#([\w-]*))$/, - - // Match a standalone tag - rsingleTag = /^<(\w+)\s*\/?>(?:<\/\1>|)$/, - - // JSON RegExp - rvalidchars = /^[\],:{}\s]*$/, - rvalidbraces = /(?:^|:|,)(?:\s*\[)+/g, - rvalidescape = /\\(?:["\\\/bfnrt]|u[\da-fA-F]{4})/g, - rvalidtokens = /"[^"\\\r\n]*"|true|false|null|-?(?:\d+\.|)\d+(?:[eE][+-]?\d+|)/g, - - // Matches dashed string for camelizing - rmsPrefix = /^-ms-/, - rdashAlpha = /-([\da-z])/gi, - - // Used by jQuery.camelCase as callback to replace() - fcamelCase = function( all, letter ) { - return letter.toUpperCase(); - }, - - // The ready event handler - completed = function( event ) { - - // readyState === "complete" is good enough for us to call the dom ready in oldIE - if ( document.addEventListener || event.type === "load" || document.readyState === "complete" ) { - detach(); - jQuery.ready(); - } - }, - // Clean-up method for dom ready events - detach = function() { - if ( document.addEventListener ) { - document.removeEventListener( "DOMContentLoaded", completed, false ); - window.removeEventListener( "load", completed, false ); - - } else { - document.detachEvent( "onreadystatechange", completed ); - window.detachEvent( "onload", completed ); - } - }; - -jQuery.fn = jQuery.prototype = { - // The current version of jQuery being used - jquery: core_version, - - constructor: jQuery, - init: function( selector, context, rootjQuery ) { - var match, elem; - - // HANDLE: $(""), $(null), $(undefined), $(false) - if ( !selector ) { - return this; - } - - // Handle HTML strings - if ( typeof selector === "string" ) { - if ( selector.charAt(0) === "<" && selector.charAt( selector.length - 1 ) === ">" && selector.length >= 3 ) { - // Assume that strings that start and end with <> are HTML and skip the regex check - match = [ null, selector, null ]; - - } else { - match = rquickExpr.exec( selector ); - } - - // Match html or make sure no context is specified for #id - if ( match && (match[1] || !context) ) { - - // HANDLE: $(html) -> $(array) - if ( match[1] ) { - context = context instanceof jQuery ? context[0] : context; - - // scripts is true for back-compat - jQuery.merge( this, jQuery.parseHTML( - match[1], - context && context.nodeType ? context.ownerDocument || context : document, - true - ) ); - - // HANDLE: $(html, props) - if ( rsingleTag.test( match[1] ) && jQuery.isPlainObject( context ) ) { - for ( match in context ) { - // Properties of context are called as methods if possible - if ( jQuery.isFunction( this[ match ] ) ) { - this[ match ]( context[ match ] ); - - // ...and otherwise set as attributes - } else { - this.attr( match, context[ match ] ); - } - } - } - - return this; - - // HANDLE: $(#id) - } else { - elem = document.getElementById( match[2] ); - - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - if ( elem && elem.parentNode ) { - // Handle the case where IE and Opera return items - // by name instead of ID - if ( elem.id !== match[2] ) { - return rootjQuery.find( selector ); - } - - // Otherwise, we inject the element directly into the jQuery object - this.length = 1; - this[0] = elem; - } - - this.context = document; - this.selector = selector; - return this; - } - - // HANDLE: $(expr, $(...)) - } else if ( !context || context.jquery ) { - return ( context || rootjQuery ).find( selector ); - - // HANDLE: $(expr, context) - // (which is just equivalent to: $(context).find(expr) - } else { - return this.constructor( context ).find( selector ); - } - - // HANDLE: $(DOMElement) - } else if ( selector.nodeType ) { - this.context = this[0] = selector; - this.length = 1; - return this; - - // HANDLE: $(function) - // Shortcut for document ready - } else if ( jQuery.isFunction( selector ) ) { - return rootjQuery.ready( selector ); - } - - if ( selector.selector !== undefined ) { - this.selector = selector.selector; - this.context = selector.context; - } - - return jQuery.makeArray( selector, this ); - }, - - // Start with an empty selector - selector: "", - - // The default length of a jQuery object is 0 - length: 0, - - toArray: function() { - return core_slice.call( this ); - }, - - // Get the Nth element in the matched element set OR - // Get the whole matched element set as a clean array - get: function( num ) { - return num == null ? - - // Return a 'clean' array - this.toArray() : - - // Return just the object - ( num < 0 ? this[ this.length + num ] : this[ num ] ); - }, - - // Take an array of elements and push it onto the stack - // (returning the new matched element set) - pushStack: function( elems ) { - - // Build a new jQuery matched element set - var ret = jQuery.merge( this.constructor(), elems ); - - // Add the old object onto the stack (as a reference) - ret.prevObject = this; - ret.context = this.context; - - // Return the newly-formed element set - return ret; - }, - - // Execute a callback for every element in the matched set. - // (You can seed the arguments with an array of args, but this is - // only used internally.) - each: function( callback, args ) { - return jQuery.each( this, callback, args ); - }, - - ready: function( fn ) { - // Add the callback - jQuery.ready.promise().done( fn ); - - return this; - }, - - slice: function() { - return this.pushStack( core_slice.apply( this, arguments ) ); - }, - - first: function() { - return this.eq( 0 ); - }, - - last: function() { - return this.eq( -1 ); - }, - - eq: function( i ) { - var len = this.length, - j = +i + ( i < 0 ? len : 0 ); - return this.pushStack( j >= 0 && j < len ? [ this[j] ] : [] ); - }, - - map: function( callback ) { - return this.pushStack( jQuery.map(this, function( elem, i ) { - return callback.call( elem, i, elem ); - })); - }, - - end: function() { - return this.prevObject || this.constructor(null); - }, - - // For internal use only. - // Behaves like an Array's method, not like a jQuery method. - push: core_push, - sort: [].sort, - splice: [].splice -}; - -// Give the init function the jQuery prototype for later instantiation -jQuery.fn.init.prototype = jQuery.fn; - -jQuery.extend = jQuery.fn.extend = function() { - var src, copyIsArray, copy, name, options, clone, - target = arguments[0] || {}, - i = 1, - length = arguments.length, - deep = false; - - // Handle a deep copy situation - if ( typeof target === "boolean" ) { - deep = target; - target = arguments[1] || {}; - // skip the boolean and the target - i = 2; - } - - // Handle case when target is a string or something (possible in deep copy) - if ( typeof target !== "object" && !jQuery.isFunction(target) ) { - target = {}; - } - - // extend jQuery itself if only one argument is passed - if ( length === i ) { - target = this; - --i; - } - - for ( ; i < length; i++ ) { - // Only deal with non-null/undefined values - if ( (options = arguments[ i ]) != null ) { - // Extend the base object - for ( name in options ) { - src = target[ name ]; - copy = options[ name ]; - - // Prevent never-ending loop - if ( target === copy ) { - continue; - } - - // Recurse if we're merging plain objects or arrays - if ( deep && copy && ( jQuery.isPlainObject(copy) || (copyIsArray = jQuery.isArray(copy)) ) ) { - if ( copyIsArray ) { - copyIsArray = false; - clone = src && jQuery.isArray(src) ? src : []; - - } else { - clone = src && jQuery.isPlainObject(src) ? src : {}; - } - - // Never move original objects, clone them - target[ name ] = jQuery.extend( deep, clone, copy ); - - // Don't bring in undefined values - } else if ( copy !== undefined ) { - target[ name ] = copy; - } - } - } - } - - // Return the modified object - return target; -}; - -jQuery.extend({ - // Unique for each copy of jQuery on the page - // Non-digits removed to match rinlinejQuery - expando: "jQuery" + ( core_version + Math.random() ).replace( /\D/g, "" ), - - noConflict: function( deep ) { - if ( window.$ === jQuery ) { - window.$ = _$; - } - - if ( deep && window.jQuery === jQuery ) { - window.jQuery = _jQuery; - } - - return jQuery; - }, - - // Is the DOM ready to be used? Set to true once it occurs. - isReady: false, - - // A counter to track how many items to wait for before - // the ready event fires. See #6781 - readyWait: 1, - - // Hold (or release) the ready event - holdReady: function( hold ) { - if ( hold ) { - jQuery.readyWait++; - } else { - jQuery.ready( true ); - } - }, - - // Handle when the DOM is ready - ready: function( wait ) { - - // Abort if there are pending holds or we're already ready - if ( wait === true ? --jQuery.readyWait : jQuery.isReady ) { - return; - } - - // Make sure body exists, at least, in case IE gets a little overzealous (ticket #5443). - if ( !document.body ) { - return setTimeout( jQuery.ready ); - } - - // Remember that the DOM is ready - jQuery.isReady = true; - - // If a normal DOM Ready event fired, decrement, and wait if need be - if ( wait !== true && --jQuery.readyWait > 0 ) { - return; - } - - // If there are functions bound, to execute - readyList.resolveWith( document, [ jQuery ] ); - - // Trigger any bound ready events - if ( jQuery.fn.trigger ) { - jQuery( document ).trigger("ready").off("ready"); - } - }, - - // See test/unit/core.js for details concerning isFunction. - // Since version 1.3, DOM methods and functions like alert - // aren't supported. They return false on IE (#2968). - isFunction: function( obj ) { - return jQuery.type(obj) === "function"; - }, - - isArray: Array.isArray || function( obj ) { - return jQuery.type(obj) === "array"; - }, - - isWindow: function( obj ) { - /* jshint eqeqeq: false */ - return obj != null && obj == obj.window; - }, - - isNumeric: function( obj ) { - return !isNaN( parseFloat(obj) ) && isFinite( obj ); - }, - - type: function( obj ) { - if ( obj == null ) { - return String( obj ); - } - return typeof obj === "object" || typeof obj === "function" ? - class2type[ core_toString.call(obj) ] || "object" : - typeof obj; - }, - - isPlainObject: function( obj ) { - var key; - - // Must be an Object. - // Because of IE, we also have to check the presence of the constructor property. - // Make sure that DOM nodes and window objects don't pass through, as well - if ( !obj || jQuery.type(obj) !== "object" || obj.nodeType || jQuery.isWindow( obj ) ) { - return false; - } - - try { - // Not own constructor property must be Object - if ( obj.constructor && - !core_hasOwn.call(obj, "constructor") && - !core_hasOwn.call(obj.constructor.prototype, "isPrototypeOf") ) { - return false; - } - } catch ( e ) { - // IE8,9 Will throw exceptions on certain host objects #9897 - return false; - } - - // Support: IE<9 - // Handle iteration over inherited properties before own properties. - if ( jQuery.support.ownLast ) { - for ( key in obj ) { - return core_hasOwn.call( obj, key ); - } - } - - // Own properties are enumerated firstly, so to speed up, - // if last one is own, then all properties are own. - for ( key in obj ) {} - - return key === undefined || core_hasOwn.call( obj, key ); - }, - - isEmptyObject: function( obj ) { - var name; - for ( name in obj ) { - return false; - } - return true; - }, - - error: function( msg ) { - throw new Error( msg ); - }, - - // data: string of html - // context (optional): If specified, the fragment will be created in this context, defaults to document - // keepScripts (optional): If true, will include scripts passed in the html string - parseHTML: function( data, context, keepScripts ) { - if ( !data || typeof data !== "string" ) { - return null; - } - if ( typeof context === "boolean" ) { - keepScripts = context; - context = false; - } - context = context || document; - - var parsed = rsingleTag.exec( data ), - scripts = !keepScripts && []; - - // Single tag - if ( parsed ) { - return [ context.createElement( parsed[1] ) ]; - } - - parsed = jQuery.buildFragment( [ data ], context, scripts ); - if ( scripts ) { - jQuery( scripts ).remove(); - } - return jQuery.merge( [], parsed.childNodes ); - }, - - parseJSON: function( data ) { - // Attempt to parse using the native JSON parser first - if ( window.JSON && window.JSON.parse ) { - return window.JSON.parse( data ); - } - - if ( data === null ) { - return data; - } - - if ( typeof data === "string" ) { - - // Make sure leading/trailing whitespace is removed (IE can't handle it) - data = jQuery.trim( data ); - - if ( data ) { - // Make sure the incoming data is actual JSON - // Logic borrowed from http://json.org/json2.js - if ( rvalidchars.test( data.replace( rvalidescape, "@" ) - .replace( rvalidtokens, "]" ) - .replace( rvalidbraces, "")) ) { - - return ( new Function( "return " + data ) )(); - } - } - } - - jQuery.error( "Invalid JSON: " + data ); - }, - - // Cross-browser xml parsing - parseXML: function( data ) { - var xml, tmp; - if ( !data || typeof data !== "string" ) { - return null; - } - try { - if ( window.DOMParser ) { // Standard - tmp = new DOMParser(); - xml = tmp.parseFromString( data , "text/xml" ); - } else { // IE - xml = new ActiveXObject( "Microsoft.XMLDOM" ); - xml.async = "false"; - xml.loadXML( data ); - } - } catch( e ) { - xml = undefined; - } - if ( !xml || !xml.documentElement || xml.getElementsByTagName( "parsererror" ).length ) { - jQuery.error( "Invalid XML: " + data ); - } - return xml; - }, - - noop: function() {}, - - // Evaluates a script in a global context - // Workarounds based on findings by Jim Driscoll - // http://weblogs.java.net/blog/driscoll/archive/2009/09/08/eval-javascript-global-context - globalEval: function( data ) { - if ( data && jQuery.trim( data ) ) { - // We use execScript on Internet Explorer - // We use an anonymous function so that context is window - // rather than jQuery in Firefox - ( window.execScript || function( data ) { - window[ "eval" ].call( window, data ); - } )( data ); - } - }, - - // Convert dashed to camelCase; used by the css and data modules - // Microsoft forgot to hump their vendor prefix (#9572) - camelCase: function( string ) { - return string.replace( rmsPrefix, "ms-" ).replace( rdashAlpha, fcamelCase ); - }, - - nodeName: function( elem, name ) { - return elem.nodeName && elem.nodeName.toLowerCase() === name.toLowerCase(); - }, - - // args is for internal usage only - each: function( obj, callback, args ) { - var value, - i = 0, - length = obj.length, - isArray = isArraylike( obj ); - - if ( args ) { - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback.apply( obj[ i ], args ); - - if ( value === false ) { - break; - } - } - } else { - for ( i in obj ) { - value = callback.apply( obj[ i ], args ); - - if ( value === false ) { - break; - } - } - } - - // A special, fast, case for the most common use of each - } else { - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback.call( obj[ i ], i, obj[ i ] ); - - if ( value === false ) { - break; - } - } - } else { - for ( i in obj ) { - value = callback.call( obj[ i ], i, obj[ i ] ); - - if ( value === false ) { - break; - } - } - } - } - - return obj; - }, - - // Use native String.trim function wherever possible - trim: core_trim && !core_trim.call("\uFEFF\xA0") ? - function( text ) { - return text == null ? - "" : - core_trim.call( text ); - } : - - // Otherwise use our own trimming functionality - function( text ) { - return text == null ? - "" : - ( text + "" ).replace( rtrim, "" ); - }, - - // results is for internal usage only - makeArray: function( arr, results ) { - var ret = results || []; - - if ( arr != null ) { - if ( isArraylike( Object(arr) ) ) { - jQuery.merge( ret, - typeof arr === "string" ? - [ arr ] : arr - ); - } else { - core_push.call( ret, arr ); - } - } - - return ret; - }, - - inArray: function( elem, arr, i ) { - var len; - - if ( arr ) { - if ( core_indexOf ) { - return core_indexOf.call( arr, elem, i ); - } - - len = arr.length; - i = i ? i < 0 ? Math.max( 0, len + i ) : i : 0; - - for ( ; i < len; i++ ) { - // Skip accessing in sparse arrays - if ( i in arr && arr[ i ] === elem ) { - return i; - } - } - } - - return -1; - }, - - merge: function( first, second ) { - var l = second.length, - i = first.length, - j = 0; - - if ( typeof l === "number" ) { - for ( ; j < l; j++ ) { - first[ i++ ] = second[ j ]; - } - } else { - while ( second[j] !== undefined ) { - first[ i++ ] = second[ j++ ]; - } - } - - first.length = i; - - return first; - }, - - grep: function( elems, callback, inv ) { - var retVal, - ret = [], - i = 0, - length = elems.length; - inv = !!inv; - - // Go through the array, only saving the items - // that pass the validator function - for ( ; i < length; i++ ) { - retVal = !!callback( elems[ i ], i ); - if ( inv !== retVal ) { - ret.push( elems[ i ] ); - } - } - - return ret; - }, - - // arg is for internal usage only - map: function( elems, callback, arg ) { - var value, - i = 0, - length = elems.length, - isArray = isArraylike( elems ), - ret = []; - - // Go through the array, translating each of the items to their - if ( isArray ) { - for ( ; i < length; i++ ) { - value = callback( elems[ i ], i, arg ); - - if ( value != null ) { - ret[ ret.length ] = value; - } - } - - // Go through every key on the object, - } else { - for ( i in elems ) { - value = callback( elems[ i ], i, arg ); - - if ( value != null ) { - ret[ ret.length ] = value; - } - } - } - - // Flatten any nested arrays - return core_concat.apply( [], ret ); - }, - - // A global GUID counter for objects - guid: 1, - - // Bind a function to a context, optionally partially applying any - // arguments. - proxy: function( fn, context ) { - var args, proxy, tmp; - - if ( typeof context === "string" ) { - tmp = fn[ context ]; - context = fn; - fn = tmp; - } - - // Quick check to determine if target is callable, in the spec - // this throws a TypeError, but we will just return undefined. - if ( !jQuery.isFunction( fn ) ) { - return undefined; - } - - // Simulated bind - args = core_slice.call( arguments, 2 ); - proxy = function() { - return fn.apply( context || this, args.concat( core_slice.call( arguments ) ) ); - }; - - // Set the guid of unique handler to the same of original handler, so it can be removed - proxy.guid = fn.guid = fn.guid || jQuery.guid++; - - return proxy; - }, - - // Multifunctional method to get and set values of a collection - // The value/s can optionally be executed if it's a function - access: function( elems, fn, key, value, chainable, emptyGet, raw ) { - var i = 0, - length = elems.length, - bulk = key == null; - - // Sets many values - if ( jQuery.type( key ) === "object" ) { - chainable = true; - for ( i in key ) { - jQuery.access( elems, fn, i, key[i], true, emptyGet, raw ); - } - - // Sets one value - } else if ( value !== undefined ) { - chainable = true; - - if ( !jQuery.isFunction( value ) ) { - raw = true; - } - - if ( bulk ) { - // Bulk operations run against the entire set - if ( raw ) { - fn.call( elems, value ); - fn = null; - - // ...except when executing function values - } else { - bulk = fn; - fn = function( elem, key, value ) { - return bulk.call( jQuery( elem ), value ); - }; - } - } - - if ( fn ) { - for ( ; i < length; i++ ) { - fn( elems[i], key, raw ? value : value.call( elems[i], i, fn( elems[i], key ) ) ); - } - } - } - - return chainable ? - elems : - - // Gets - bulk ? - fn.call( elems ) : - length ? fn( elems[0], key ) : emptyGet; - }, - - now: function() { - return ( new Date() ).getTime(); - }, - - // A method for quickly swapping in/out CSS properties to get correct calculations. - // Note: this method belongs to the css module but it's needed here for the support module. - // If support gets modularized, this method should be moved back to the css module. - swap: function( elem, options, callback, args ) { - var ret, name, - old = {}; - - // Remember the old values, and insert the new ones - for ( name in options ) { - old[ name ] = elem.style[ name ]; - elem.style[ name ] = options[ name ]; - } - - ret = callback.apply( elem, args || [] ); - - // Revert the old values - for ( name in options ) { - elem.style[ name ] = old[ name ]; - } - - return ret; - } -}); - -jQuery.ready.promise = function( obj ) { - if ( !readyList ) { - - readyList = jQuery.Deferred(); - - // Catch cases where $(document).ready() is called after the browser event has already occurred. - // we once tried to use readyState "interactive" here, but it caused issues like the one - // discovered by ChrisS here: http://bugs.jquery.com/ticket/12282#comment:15 - if ( document.readyState === "complete" ) { - // Handle it asynchronously to allow scripts the opportunity to delay ready - setTimeout( jQuery.ready ); - - // Standards-based browsers support DOMContentLoaded - } else if ( document.addEventListener ) { - // Use the handy event callback - document.addEventListener( "DOMContentLoaded", completed, false ); - - // A fallback to window.onload, that will always work - window.addEventListener( "load", completed, false ); - - // If IE event model is used - } else { - // Ensure firing before onload, maybe late but safe also for iframes - document.attachEvent( "onreadystatechange", completed ); - - // A fallback to window.onload, that will always work - window.attachEvent( "onload", completed ); - - // If IE and not a frame - // continually check to see if the document is ready - var top = false; - - try { - top = window.frameElement == null && document.documentElement; - } catch(e) {} - - if ( top && top.doScroll ) { - (function doScrollCheck() { - if ( !jQuery.isReady ) { - - try { - // Use the trick by Diego Perini - // http://javascript.nwbox.com/IEContentLoaded/ - top.doScroll("left"); - } catch(e) { - return setTimeout( doScrollCheck, 50 ); - } - - // detach all dom ready events - detach(); - - // and execute any waiting functions - jQuery.ready(); - } - })(); - } - } - } - return readyList.promise( obj ); -}; - -// Populate the class2type map -jQuery.each("Boolean Number String Function Array Date RegExp Object Error".split(" "), function(i, name) { - class2type[ "[object " + name + "]" ] = name.toLowerCase(); -}); - -function isArraylike( obj ) { - var length = obj.length, - type = jQuery.type( obj ); - - if ( jQuery.isWindow( obj ) ) { - return false; - } - - if ( obj.nodeType === 1 && length ) { - return true; - } - - return type === "array" || type !== "function" && - ( length === 0 || - typeof length === "number" && length > 0 && ( length - 1 ) in obj ); -} - -// All jQuery objects should point back to these -rootjQuery = jQuery(document); -/*! - * Sizzle CSS Selector Engine v1.10.2 - * http://sizzlejs.com/ - * - * Copyright 2013 jQuery Foundation, Inc. and other contributors - * Released under the MIT license - * http://jquery.org/license - * - * Date: 2013-07-03 - */ -(function( window, undefined ) { - -var i, - support, - cachedruns, - Expr, - getText, - isXML, - compile, - outermostContext, - sortInput, - - // Local document vars - setDocument, - document, - docElem, - documentIsHTML, - rbuggyQSA, - rbuggyMatches, - matches, - contains, - - // Instance-specific data - expando = "sizzle" + -(new Date()), - preferredDoc = window.document, - dirruns = 0, - done = 0, - classCache = createCache(), - tokenCache = createCache(), - compilerCache = createCache(), - hasDuplicate = false, - sortOrder = function( a, b ) { - if ( a === b ) { - hasDuplicate = true; - return 0; - } - return 0; - }, - - // General-purpose constants - strundefined = typeof undefined, - MAX_NEGATIVE = 1 << 31, - - // Instance methods - hasOwn = ({}).hasOwnProperty, - arr = [], - pop = arr.pop, - push_native = arr.push, - push = arr.push, - slice = arr.slice, - // Use a stripped-down indexOf if we can't use a native one - indexOf = arr.indexOf || function( elem ) { - var i = 0, - len = this.length; - for ( ; i < len; i++ ) { - if ( this[i] === elem ) { - return i; - } - } - return -1; - }, - - booleans = "checked|selected|async|autofocus|autoplay|controls|defer|disabled|hidden|ismap|loop|multiple|open|readonly|required|scoped", - - // Regular expressions - - // Whitespace characters http://www.w3.org/TR/css3-selectors/#whitespace - whitespace = "[\\x20\\t\\r\\n\\f]", - // http://www.w3.org/TR/css3-syntax/#characters - characterEncoding = "(?:\\\\.|[\\w-]|[^\\x00-\\xa0])+", - - // Loosely modeled on CSS identifier characters - // An unquoted value should be a CSS identifier http://www.w3.org/TR/css3-selectors/#attribute-selectors - // Proper syntax: http://www.w3.org/TR/CSS21/syndata.html#value-def-identifier - identifier = characterEncoding.replace( "w", "w#" ), - - // Acceptable operators http://www.w3.org/TR/selectors/#attribute-selectors - attributes = "\\[" + whitespace + "*(" + characterEncoding + ")" + whitespace + - "*(?:([*^$|!~]?=)" + whitespace + "*(?:(['\"])((?:\\\\.|[^\\\\])*?)\\3|(" + identifier + ")|)|)" + whitespace + "*\\]", - - // Prefer arguments quoted, - // then not containing pseudos/brackets, - // then attribute selectors/non-parenthetical expressions, - // then anything else - // These preferences are here to reduce the number of selectors - // needing tokenize in the PSEUDO preFilter - pseudos = ":(" + characterEncoding + ")(?:\\(((['\"])((?:\\\\.|[^\\\\])*?)\\3|((?:\\\\.|[^\\\\()[\\]]|" + attributes.replace( 3, 8 ) + ")*)|.*)\\)|)", - - // Leading and non-escaped trailing whitespace, capturing some non-whitespace characters preceding the latter - rtrim = new RegExp( "^" + whitespace + "+|((?:^|[^\\\\])(?:\\\\.)*)" + whitespace + "+$", "g" ), - - rcomma = new RegExp( "^" + whitespace + "*," + whitespace + "*" ), - rcombinators = new RegExp( "^" + whitespace + "*([>+~]|" + whitespace + ")" + whitespace + "*" ), - - rsibling = new RegExp( whitespace + "*[+~]" ), - rattributeQuotes = new RegExp( "=" + whitespace + "*([^\\]'\"]*)" + whitespace + "*\\]", "g" ), - - rpseudo = new RegExp( pseudos ), - ridentifier = new RegExp( "^" + identifier + "$" ), - - matchExpr = { - "ID": new RegExp( "^#(" + characterEncoding + ")" ), - "CLASS": new RegExp( "^\\.(" + characterEncoding + ")" ), - "TAG": new RegExp( "^(" + characterEncoding.replace( "w", "w*" ) + ")" ), - "ATTR": new RegExp( "^" + attributes ), - "PSEUDO": new RegExp( "^" + pseudos ), - "CHILD": new RegExp( "^:(only|first|last|nth|nth-last)-(child|of-type)(?:\\(" + whitespace + - "*(even|odd|(([+-]|)(\\d*)n|)" + whitespace + "*(?:([+-]|)" + whitespace + - "*(\\d+)|))" + whitespace + "*\\)|)", "i" ), - "bool": new RegExp( "^(?:" + booleans + ")$", "i" ), - // For use in libraries implementing .is() - // We use this for POS matching in `select` - "needsContext": new RegExp( "^" + whitespace + "*[>+~]|:(even|odd|eq|gt|lt|nth|first|last)(?:\\(" + - whitespace + "*((?:-\\d)?\\d*)" + whitespace + "*\\)|)(?=[^-]|$)", "i" ) - }, - - rnative = /^[^{]+\{\s*\[native \w/, - - // Easily-parseable/retrievable ID or TAG or CLASS selectors - rquickExpr = /^(?:#([\w-]+)|(\w+)|\.([\w-]+))$/, - - rinputs = /^(?:input|select|textarea|button)$/i, - rheader = /^h\d$/i, - - rescape = /'|\\/g, - - // CSS escapes http://www.w3.org/TR/CSS21/syndata.html#escaped-characters - runescape = new RegExp( "\\\\([\\da-f]{1,6}" + whitespace + "?|(" + whitespace + ")|.)", "ig" ), - funescape = function( _, escaped, escapedWhitespace ) { - var high = "0x" + escaped - 0x10000; - // NaN means non-codepoint - // Support: Firefox - // Workaround erroneous numeric interpretation of +"0x" - return high !== high || escapedWhitespace ? - escaped : - // BMP codepoint - high < 0 ? - String.fromCharCode( high + 0x10000 ) : - // Supplemental Plane codepoint (surrogate pair) - String.fromCharCode( high >> 10 | 0xD800, high & 0x3FF | 0xDC00 ); - }; - -// Optimize for push.apply( _, NodeList ) -try { - push.apply( - (arr = slice.call( preferredDoc.childNodes )), - preferredDoc.childNodes - ); - // Support: Android<4.0 - // Detect silently failing push.apply - arr[ preferredDoc.childNodes.length ].nodeType; -} catch ( e ) { - push = { apply: arr.length ? - - // Leverage slice if possible - function( target, els ) { - push_native.apply( target, slice.call(els) ); - } : - - // Support: IE<9 - // Otherwise append directly - function( target, els ) { - var j = target.length, - i = 0; - // Can't trust NodeList.length - while ( (target[j++] = els[i++]) ) {} - target.length = j - 1; - } - }; -} - -function Sizzle( selector, context, results, seed ) { - var match, elem, m, nodeType, - // QSA vars - i, groups, old, nid, newContext, newSelector; - - if ( ( context ? context.ownerDocument || context : preferredDoc ) !== document ) { - setDocument( context ); - } - - context = context || document; - results = results || []; - - if ( !selector || typeof selector !== "string" ) { - return results; - } - - if ( (nodeType = context.nodeType) !== 1 && nodeType !== 9 ) { - return []; - } - - if ( documentIsHTML && !seed ) { - - // Shortcuts - if ( (match = rquickExpr.exec( selector )) ) { - // Speed-up: Sizzle("#ID") - if ( (m = match[1]) ) { - if ( nodeType === 9 ) { - elem = context.getElementById( m ); - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - if ( elem && elem.parentNode ) { - // Handle the case where IE, Opera, and Webkit return items - // by name instead of ID - if ( elem.id === m ) { - results.push( elem ); - return results; - } - } else { - return results; - } - } else { - // Context is not a document - if ( context.ownerDocument && (elem = context.ownerDocument.getElementById( m )) && - contains( context, elem ) && elem.id === m ) { - results.push( elem ); - return results; - } - } - - // Speed-up: Sizzle("TAG") - } else if ( match[2] ) { - push.apply( results, context.getElementsByTagName( selector ) ); - return results; - - // Speed-up: Sizzle(".CLASS") - } else if ( (m = match[3]) && support.getElementsByClassName && context.getElementsByClassName ) { - push.apply( results, context.getElementsByClassName( m ) ); - return results; - } - } - - // QSA path - if ( support.qsa && (!rbuggyQSA || !rbuggyQSA.test( selector )) ) { - nid = old = expando; - newContext = context; - newSelector = nodeType === 9 && selector; - - // qSA works strangely on Element-rooted queries - // We can work around this by specifying an extra ID on the root - // and working up from there (Thanks to Andrew Dupont for the technique) - // IE 8 doesn't work on object elements - if ( nodeType === 1 && context.nodeName.toLowerCase() !== "object" ) { - groups = tokenize( selector ); - - if ( (old = context.getAttribute("id")) ) { - nid = old.replace( rescape, "\\$&" ); - } else { - context.setAttribute( "id", nid ); - } - nid = "[id='" + nid + "'] "; - - i = groups.length; - while ( i-- ) { - groups[i] = nid + toSelector( groups[i] ); - } - newContext = rsibling.test( selector ) && context.parentNode || context; - newSelector = groups.join(","); - } - - if ( newSelector ) { - try { - push.apply( results, - newContext.querySelectorAll( newSelector ) - ); - return results; - } catch(qsaError) { - } finally { - if ( !old ) { - context.removeAttribute("id"); - } - } - } - } - } - - // All others - return select( selector.replace( rtrim, "$1" ), context, results, seed ); -} - -/** - * Create key-value caches of limited size - * @returns {Function(string, Object)} Returns the Object data after storing it on itself with - * property name the (space-suffixed) string and (if the cache is larger than Expr.cacheLength) - * deleting the oldest entry - */ -function createCache() { - var keys = []; - - function cache( key, value ) { - // Use (key + " ") to avoid collision with native prototype properties (see Issue #157) - if ( keys.push( key += " " ) > Expr.cacheLength ) { - // Only keep the most recent entries - delete cache[ keys.shift() ]; - } - return (cache[ key ] = value); - } - return cache; -} - -/** - * Mark a function for special use by Sizzle - * @param {Function} fn The function to mark - */ -function markFunction( fn ) { - fn[ expando ] = true; - return fn; -} - -/** - * Support testing using an element - * @param {Function} fn Passed the created div and expects a boolean result - */ -function assert( fn ) { - var div = document.createElement("div"); - - try { - return !!fn( div ); - } catch (e) { - return false; - } finally { - // Remove from its parent by default - if ( div.parentNode ) { - div.parentNode.removeChild( div ); - } - // release memory in IE - div = null; - } -} - -/** - * Adds the same handler for all of the specified attrs - * @param {String} attrs Pipe-separated list of attributes - * @param {Function} handler The method that will be applied - */ -function addHandle( attrs, handler ) { - var arr = attrs.split("|"), - i = attrs.length; - - while ( i-- ) { - Expr.attrHandle[ arr[i] ] = handler; - } -} - -/** - * Checks document order of two siblings - * @param {Element} a - * @param {Element} b - * @returns {Number} Returns less than 0 if a precedes b, greater than 0 if a follows b - */ -function siblingCheck( a, b ) { - var cur = b && a, - diff = cur && a.nodeType === 1 && b.nodeType === 1 && - ( ~b.sourceIndex || MAX_NEGATIVE ) - - ( ~a.sourceIndex || MAX_NEGATIVE ); - - // Use IE sourceIndex if available on both nodes - if ( diff ) { - return diff; - } - - // Check if b follows a - if ( cur ) { - while ( (cur = cur.nextSibling) ) { - if ( cur === b ) { - return -1; - } - } - } - - return a ? 1 : -1; -} - -/** - * Returns a function to use in pseudos for input types - * @param {String} type - */ -function createInputPseudo( type ) { - return function( elem ) { - var name = elem.nodeName.toLowerCase(); - return name === "input" && elem.type === type; - }; -} - -/** - * Returns a function to use in pseudos for buttons - * @param {String} type - */ -function createButtonPseudo( type ) { - return function( elem ) { - var name = elem.nodeName.toLowerCase(); - return (name === "input" || name === "button") && elem.type === type; - }; -} - -/** - * Returns a function to use in pseudos for positionals - * @param {Function} fn - */ -function createPositionalPseudo( fn ) { - return markFunction(function( argument ) { - argument = +argument; - return markFunction(function( seed, matches ) { - var j, - matchIndexes = fn( [], seed.length, argument ), - i = matchIndexes.length; - - // Match elements found at the specified indexes - while ( i-- ) { - if ( seed[ (j = matchIndexes[i]) ] ) { - seed[j] = !(matches[j] = seed[j]); - } - } - }); - }); -} - -/** - * Detect xml - * @param {Element|Object} elem An element or a document - */ -isXML = Sizzle.isXML = function( elem ) { - // documentElement is verified for cases where it doesn't yet exist - // (such as loading iframes in IE - #4833) - var documentElement = elem && (elem.ownerDocument || elem).documentElement; - return documentElement ? documentElement.nodeName !== "HTML" : false; -}; - -// Expose support vars for convenience -support = Sizzle.support = {}; - -/** - * Sets document-related variables once based on the current document - * @param {Element|Object} [doc] An element or document object to use to set the document - * @returns {Object} Returns the current document - */ -setDocument = Sizzle.setDocument = function( node ) { - var doc = node ? node.ownerDocument || node : preferredDoc, - parent = doc.defaultView; - - // If no document and documentElement is available, return - if ( doc === document || doc.nodeType !== 9 || !doc.documentElement ) { - return document; - } - - // Set our document - document = doc; - docElem = doc.documentElement; - - // Support tests - documentIsHTML = !isXML( doc ); - - // Support: IE>8 - // If iframe document is assigned to "document" variable and if iframe has been reloaded, - // IE will throw "permission denied" error when accessing "document" variable, see jQuery #13936 - // IE6-8 do not support the defaultView property so parent will be undefined - if ( parent && parent.attachEvent && parent !== parent.top ) { - parent.attachEvent( "onbeforeunload", function() { - setDocument(); - }); - } - - /* Attributes - ---------------------------------------------------------------------- */ - - // Support: IE<8 - // Verify that getAttribute really returns attributes and not properties (excepting IE8 booleans) - support.attributes = assert(function( div ) { - div.className = "i"; - return !div.getAttribute("className"); - }); - - /* getElement(s)By* - ---------------------------------------------------------------------- */ - - // Check if getElementsByTagName("*") returns only elements - support.getElementsByTagName = assert(function( div ) { - div.appendChild( doc.createComment("") ); - return !div.getElementsByTagName("*").length; - }); - - // Check if getElementsByClassName can be trusted - support.getElementsByClassName = assert(function( div ) { - div.innerHTML = "
"; - - // Support: Safari<4 - // Catch class over-caching - div.firstChild.className = "i"; - // Support: Opera<10 - // Catch gEBCN failure to find non-leading classes - return div.getElementsByClassName("i").length === 2; - }); - - // Support: IE<10 - // Check if getElementById returns elements by name - // The broken getElementById methods don't pick up programatically-set names, - // so use a roundabout getElementsByName test - support.getById = assert(function( div ) { - docElem.appendChild( div ).id = expando; - return !doc.getElementsByName || !doc.getElementsByName( expando ).length; - }); - - // ID find and filter - if ( support.getById ) { - Expr.find["ID"] = function( id, context ) { - if ( typeof context.getElementById !== strundefined && documentIsHTML ) { - var m = context.getElementById( id ); - // Check parentNode to catch when Blackberry 4.6 returns - // nodes that are no longer in the document #6963 - return m && m.parentNode ? [m] : []; - } - }; - Expr.filter["ID"] = function( id ) { - var attrId = id.replace( runescape, funescape ); - return function( elem ) { - return elem.getAttribute("id") === attrId; - }; - }; - } else { - // Support: IE6/7 - // getElementById is not reliable as a find shortcut - delete Expr.find["ID"]; - - Expr.filter["ID"] = function( id ) { - var attrId = id.replace( runescape, funescape ); - return function( elem ) { - var node = typeof elem.getAttributeNode !== strundefined && elem.getAttributeNode("id"); - return node && node.value === attrId; - }; - }; - } - - // Tag - Expr.find["TAG"] = support.getElementsByTagName ? - function( tag, context ) { - if ( typeof context.getElementsByTagName !== strundefined ) { - return context.getElementsByTagName( tag ); - } - } : - function( tag, context ) { - var elem, - tmp = [], - i = 0, - results = context.getElementsByTagName( tag ); - - // Filter out possible comments - if ( tag === "*" ) { - while ( (elem = results[i++]) ) { - if ( elem.nodeType === 1 ) { - tmp.push( elem ); - } - } - - return tmp; - } - return results; - }; - - // Class - Expr.find["CLASS"] = support.getElementsByClassName && function( className, context ) { - if ( typeof context.getElementsByClassName !== strundefined && documentIsHTML ) { - return context.getElementsByClassName( className ); - } - }; - - /* QSA/matchesSelector - ---------------------------------------------------------------------- */ - - // QSA and matchesSelector support - - // matchesSelector(:active) reports false when true (IE9/Opera 11.5) - rbuggyMatches = []; - - // qSa(:focus) reports false when true (Chrome 21) - // We allow this because of a bug in IE8/9 that throws an error - // whenever `document.activeElement` is accessed on an iframe - // So, we allow :focus to pass through QSA all the time to avoid the IE error - // See http://bugs.jquery.com/ticket/13378 - rbuggyQSA = []; - - if ( (support.qsa = rnative.test( doc.querySelectorAll )) ) { - // Build QSA regex - // Regex strategy adopted from Diego Perini - assert(function( div ) { - // Select is set to empty string on purpose - // This is to test IE's treatment of not explicitly - // setting a boolean content attribute, - // since its presence should be enough - // http://bugs.jquery.com/ticket/12359 - div.innerHTML = ""; - - // Support: IE8 - // Boolean attributes and "value" are not treated correctly - if ( !div.querySelectorAll("[selected]").length ) { - rbuggyQSA.push( "\\[" + whitespace + "*(?:value|" + booleans + ")" ); - } - - // Webkit/Opera - :checked should return selected option elements - // http://www.w3.org/TR/2011/REC-css3-selectors-20110929/#checked - // IE8 throws error here and will not see later tests - if ( !div.querySelectorAll(":checked").length ) { - rbuggyQSA.push(":checked"); - } - }); - - assert(function( div ) { - - // Support: Opera 10-12/IE8 - // ^= $= *= and empty values - // Should not select anything - // Support: Windows 8 Native Apps - // The type attribute is restricted during .innerHTML assignment - var input = doc.createElement("input"); - input.setAttribute( "type", "hidden" ); - div.appendChild( input ).setAttribute( "t", "" ); - - if ( div.querySelectorAll("[t^='']").length ) { - rbuggyQSA.push( "[*^$]=" + whitespace + "*(?:''|\"\")" ); - } - - // FF 3.5 - :enabled/:disabled and hidden elements (hidden elements are still enabled) - // IE8 throws error here and will not see later tests - if ( !div.querySelectorAll(":enabled").length ) { - rbuggyQSA.push( ":enabled", ":disabled" ); - } - - // Opera 10-11 does not throw on post-comma invalid pseudos - div.querySelectorAll("*,:x"); - rbuggyQSA.push(",.*:"); - }); - } - - if ( (support.matchesSelector = rnative.test( (matches = docElem.webkitMatchesSelector || - docElem.mozMatchesSelector || - docElem.oMatchesSelector || - docElem.msMatchesSelector) )) ) { - - assert(function( div ) { - // Check to see if it's possible to do matchesSelector - // on a disconnected node (IE 9) - support.disconnectedMatch = matches.call( div, "div" ); - - // This should fail with an exception - // Gecko does not error, returns false instead - matches.call( div, "[s!='']:x" ); - rbuggyMatches.push( "!=", pseudos ); - }); - } - - rbuggyQSA = rbuggyQSA.length && new RegExp( rbuggyQSA.join("|") ); - rbuggyMatches = rbuggyMatches.length && new RegExp( rbuggyMatches.join("|") ); - - /* Contains - ---------------------------------------------------------------------- */ - - // Element contains another - // Purposefully does not implement inclusive descendent - // As in, an element does not contain itself - contains = rnative.test( docElem.contains ) || docElem.compareDocumentPosition ? - function( a, b ) { - var adown = a.nodeType === 9 ? a.documentElement : a, - bup = b && b.parentNode; - return a === bup || !!( bup && bup.nodeType === 1 && ( - adown.contains ? - adown.contains( bup ) : - a.compareDocumentPosition && a.compareDocumentPosition( bup ) & 16 - )); - } : - function( a, b ) { - if ( b ) { - while ( (b = b.parentNode) ) { - if ( b === a ) { - return true; - } - } - } - return false; - }; - - /* Sorting - ---------------------------------------------------------------------- */ - - // Document order sorting - sortOrder = docElem.compareDocumentPosition ? - function( a, b ) { - - // Flag for duplicate removal - if ( a === b ) { - hasDuplicate = true; - return 0; - } - - var compare = b.compareDocumentPosition && a.compareDocumentPosition && a.compareDocumentPosition( b ); - - if ( compare ) { - // Disconnected nodes - if ( compare & 1 || - (!support.sortDetached && b.compareDocumentPosition( a ) === compare) ) { - - // Choose the first element that is related to our preferred document - if ( a === doc || contains(preferredDoc, a) ) { - return -1; - } - if ( b === doc || contains(preferredDoc, b) ) { - return 1; - } - - // Maintain original order - return sortInput ? - ( indexOf.call( sortInput, a ) - indexOf.call( sortInput, b ) ) : - 0; - } - - return compare & 4 ? -1 : 1; - } - - // Not directly comparable, sort on existence of method - return a.compareDocumentPosition ? -1 : 1; - } : - function( a, b ) { - var cur, - i = 0, - aup = a.parentNode, - bup = b.parentNode, - ap = [ a ], - bp = [ b ]; - - // Exit early if the nodes are identical - if ( a === b ) { - hasDuplicate = true; - return 0; - - // Parentless nodes are either documents or disconnected - } else if ( !aup || !bup ) { - return a === doc ? -1 : - b === doc ? 1 : - aup ? -1 : - bup ? 1 : - sortInput ? - ( indexOf.call( sortInput, a ) - indexOf.call( sortInput, b ) ) : - 0; - - // If the nodes are siblings, we can do a quick check - } else if ( aup === bup ) { - return siblingCheck( a, b ); - } - - // Otherwise we need full lists of their ancestors for comparison - cur = a; - while ( (cur = cur.parentNode) ) { - ap.unshift( cur ); - } - cur = b; - while ( (cur = cur.parentNode) ) { - bp.unshift( cur ); - } - - // Walk down the tree looking for a discrepancy - while ( ap[i] === bp[i] ) { - i++; - } - - return i ? - // Do a sibling check if the nodes have a common ancestor - siblingCheck( ap[i], bp[i] ) : - - // Otherwise nodes in our document sort first - ap[i] === preferredDoc ? -1 : - bp[i] === preferredDoc ? 1 : - 0; - }; - - return doc; -}; - -Sizzle.matches = function( expr, elements ) { - return Sizzle( expr, null, null, elements ); -}; - -Sizzle.matchesSelector = function( elem, expr ) { - // Set document vars if needed - if ( ( elem.ownerDocument || elem ) !== document ) { - setDocument( elem ); - } - - // Make sure that attribute selectors are quoted - expr = expr.replace( rattributeQuotes, "='$1']" ); - - if ( support.matchesSelector && documentIsHTML && - ( !rbuggyMatches || !rbuggyMatches.test( expr ) ) && - ( !rbuggyQSA || !rbuggyQSA.test( expr ) ) ) { - - try { - var ret = matches.call( elem, expr ); - - // IE 9's matchesSelector returns false on disconnected nodes - if ( ret || support.disconnectedMatch || - // As well, disconnected nodes are said to be in a document - // fragment in IE 9 - elem.document && elem.document.nodeType !== 11 ) { - return ret; - } - } catch(e) {} - } - - return Sizzle( expr, document, null, [elem] ).length > 0; -}; - -Sizzle.contains = function( context, elem ) { - // Set document vars if needed - if ( ( context.ownerDocument || context ) !== document ) { - setDocument( context ); - } - return contains( context, elem ); -}; - -Sizzle.attr = function( elem, name ) { - // Set document vars if needed - if ( ( elem.ownerDocument || elem ) !== document ) { - setDocument( elem ); - } - - var fn = Expr.attrHandle[ name.toLowerCase() ], - // Don't get fooled by Object.prototype properties (jQuery #13807) - val = fn && hasOwn.call( Expr.attrHandle, name.toLowerCase() ) ? - fn( elem, name, !documentIsHTML ) : - undefined; - - return val === undefined ? - support.attributes || !documentIsHTML ? - elem.getAttribute( name ) : - (val = elem.getAttributeNode(name)) && val.specified ? - val.value : - null : - val; -}; - -Sizzle.error = function( msg ) { - throw new Error( "Syntax error, unrecognized expression: " + msg ); -}; - -/** - * Document sorting and removing duplicates - * @param {ArrayLike} results - */ -Sizzle.uniqueSort = function( results ) { - var elem, - duplicates = [], - j = 0, - i = 0; - - // Unless we *know* we can detect duplicates, assume their presence - hasDuplicate = !support.detectDuplicates; - sortInput = !support.sortStable && results.slice( 0 ); - results.sort( sortOrder ); - - if ( hasDuplicate ) { - while ( (elem = results[i++]) ) { - if ( elem === results[ i ] ) { - j = duplicates.push( i ); - } - } - while ( j-- ) { - results.splice( duplicates[ j ], 1 ); - } - } - - return results; -}; - -/** - * Utility function for retrieving the text value of an array of DOM nodes - * @param {Array|Element} elem - */ -getText = Sizzle.getText = function( elem ) { - var node, - ret = "", - i = 0, - nodeType = elem.nodeType; - - if ( !nodeType ) { - // If no nodeType, this is expected to be an array - for ( ; (node = elem[i]); i++ ) { - // Do not traverse comment nodes - ret += getText( node ); - } - } else if ( nodeType === 1 || nodeType === 9 || nodeType === 11 ) { - // Use textContent for elements - // innerText usage removed for consistency of new lines (see #11153) - if ( typeof elem.textContent === "string" ) { - return elem.textContent; - } else { - // Traverse its children - for ( elem = elem.firstChild; elem; elem = elem.nextSibling ) { - ret += getText( elem ); - } - } - } else if ( nodeType === 3 || nodeType === 4 ) { - return elem.nodeValue; - } - // Do not include comment or processing instruction nodes - - return ret; -}; - -Expr = Sizzle.selectors = { - - // Can be adjusted by the user - cacheLength: 50, - - createPseudo: markFunction, - - match: matchExpr, - - attrHandle: {}, - - find: {}, - - relative: { - ">": { dir: "parentNode", first: true }, - " ": { dir: "parentNode" }, - "+": { dir: "previousSibling", first: true }, - "~": { dir: "previousSibling" } - }, - - preFilter: { - "ATTR": function( match ) { - match[1] = match[1].replace( runescape, funescape ); - - // Move the given value to match[3] whether quoted or unquoted - match[3] = ( match[4] || match[5] || "" ).replace( runescape, funescape ); - - if ( match[2] === "~=" ) { - match[3] = " " + match[3] + " "; - } - - return match.slice( 0, 4 ); - }, - - "CHILD": function( match ) { - /* matches from matchExpr["CHILD"] - 1 type (only|nth|...) - 2 what (child|of-type) - 3 argument (even|odd|\d*|\d*n([+-]\d+)?|...) - 4 xn-component of xn+y argument ([+-]?\d*n|) - 5 sign of xn-component - 6 x of xn-component - 7 sign of y-component - 8 y of y-component - */ - match[1] = match[1].toLowerCase(); - - if ( match[1].slice( 0, 3 ) === "nth" ) { - // nth-* requires argument - if ( !match[3] ) { - Sizzle.error( match[0] ); - } - - // numeric x and y parameters for Expr.filter.CHILD - // remember that false/true cast respectively to 0/1 - match[4] = +( match[4] ? match[5] + (match[6] || 1) : 2 * ( match[3] === "even" || match[3] === "odd" ) ); - match[5] = +( ( match[7] + match[8] ) || match[3] === "odd" ); - - // other types prohibit arguments - } else if ( match[3] ) { - Sizzle.error( match[0] ); - } - - return match; - }, - - "PSEUDO": function( match ) { - var excess, - unquoted = !match[5] && match[2]; - - if ( matchExpr["CHILD"].test( match[0] ) ) { - return null; - } - - // Accept quoted arguments as-is - if ( match[3] && match[4] !== undefined ) { - match[2] = match[4]; - - // Strip excess characters from unquoted arguments - } else if ( unquoted && rpseudo.test( unquoted ) && - // Get excess from tokenize (recursively) - (excess = tokenize( unquoted, true )) && - // advance to the next closing parenthesis - (excess = unquoted.indexOf( ")", unquoted.length - excess ) - unquoted.length) ) { - - // excess is a negative index - match[0] = match[0].slice( 0, excess ); - match[2] = unquoted.slice( 0, excess ); - } - - // Return only captures needed by the pseudo filter method (type and argument) - return match.slice( 0, 3 ); - } - }, - - filter: { - - "TAG": function( nodeNameSelector ) { - var nodeName = nodeNameSelector.replace( runescape, funescape ).toLowerCase(); - return nodeNameSelector === "*" ? - function() { return true; } : - function( elem ) { - return elem.nodeName && elem.nodeName.toLowerCase() === nodeName; - }; - }, - - "CLASS": function( className ) { - var pattern = classCache[ className + " " ]; - - return pattern || - (pattern = new RegExp( "(^|" + whitespace + ")" + className + "(" + whitespace + "|$)" )) && - classCache( className, function( elem ) { - return pattern.test( typeof elem.className === "string" && elem.className || typeof elem.getAttribute !== strundefined && elem.getAttribute("class") || "" ); - }); - }, - - "ATTR": function( name, operator, check ) { - return function( elem ) { - var result = Sizzle.attr( elem, name ); - - if ( result == null ) { - return operator === "!="; - } - if ( !operator ) { - return true; - } - - result += ""; - - return operator === "=" ? result === check : - operator === "!=" ? result !== check : - operator === "^=" ? check && result.indexOf( check ) === 0 : - operator === "*=" ? check && result.indexOf( check ) > -1 : - operator === "$=" ? check && result.slice( -check.length ) === check : - operator === "~=" ? ( " " + result + " " ).indexOf( check ) > -1 : - operator === "|=" ? result === check || result.slice( 0, check.length + 1 ) === check + "-" : - false; - }; - }, - - "CHILD": function( type, what, argument, first, last ) { - var simple = type.slice( 0, 3 ) !== "nth", - forward = type.slice( -4 ) !== "last", - ofType = what === "of-type"; - - return first === 1 && last === 0 ? - - // Shortcut for :nth-*(n) - function( elem ) { - return !!elem.parentNode; - } : - - function( elem, context, xml ) { - var cache, outerCache, node, diff, nodeIndex, start, - dir = simple !== forward ? "nextSibling" : "previousSibling", - parent = elem.parentNode, - name = ofType && elem.nodeName.toLowerCase(), - useCache = !xml && !ofType; - - if ( parent ) { - - // :(first|last|only)-(child|of-type) - if ( simple ) { - while ( dir ) { - node = elem; - while ( (node = node[ dir ]) ) { - if ( ofType ? node.nodeName.toLowerCase() === name : node.nodeType === 1 ) { - return false; - } - } - // Reverse direction for :only-* (if we haven't yet done so) - start = dir = type === "only" && !start && "nextSibling"; - } - return true; - } - - start = [ forward ? parent.firstChild : parent.lastChild ]; - - // non-xml :nth-child(...) stores cache data on `parent` - if ( forward && useCache ) { - // Seek `elem` from a previously-cached index - outerCache = parent[ expando ] || (parent[ expando ] = {}); - cache = outerCache[ type ] || []; - nodeIndex = cache[0] === dirruns && cache[1]; - diff = cache[0] === dirruns && cache[2]; - node = nodeIndex && parent.childNodes[ nodeIndex ]; - - while ( (node = ++nodeIndex && node && node[ dir ] || - - // Fallback to seeking `elem` from the start - (diff = nodeIndex = 0) || start.pop()) ) { - - // When found, cache indexes on `parent` and break - if ( node.nodeType === 1 && ++diff && node === elem ) { - outerCache[ type ] = [ dirruns, nodeIndex, diff ]; - break; - } - } - - // Use previously-cached element index if available - } else if ( useCache && (cache = (elem[ expando ] || (elem[ expando ] = {}))[ type ]) && cache[0] === dirruns ) { - diff = cache[1]; - - // xml :nth-child(...) or :nth-last-child(...) or :nth(-last)?-of-type(...) - } else { - // Use the same loop as above to seek `elem` from the start - while ( (node = ++nodeIndex && node && node[ dir ] || - (diff = nodeIndex = 0) || start.pop()) ) { - - if ( ( ofType ? node.nodeName.toLowerCase() === name : node.nodeType === 1 ) && ++diff ) { - // Cache the index of each encountered element - if ( useCache ) { - (node[ expando ] || (node[ expando ] = {}))[ type ] = [ dirruns, diff ]; - } - - if ( node === elem ) { - break; - } - } - } - } - - // Incorporate the offset, then check against cycle size - diff -= last; - return diff === first || ( diff % first === 0 && diff / first >= 0 ); - } - }; - }, - - "PSEUDO": function( pseudo, argument ) { - // pseudo-class names are case-insensitive - // http://www.w3.org/TR/selectors/#pseudo-classes - // Prioritize by case sensitivity in case custom pseudos are added with uppercase letters - // Remember that setFilters inherits from pseudos - var args, - fn = Expr.pseudos[ pseudo ] || Expr.setFilters[ pseudo.toLowerCase() ] || - Sizzle.error( "unsupported pseudo: " + pseudo ); - - // The user may use createPseudo to indicate that - // arguments are needed to create the filter function - // just as Sizzle does - if ( fn[ expando ] ) { - return fn( argument ); - } - - // But maintain support for old signatures - if ( fn.length > 1 ) { - args = [ pseudo, pseudo, "", argument ]; - return Expr.setFilters.hasOwnProperty( pseudo.toLowerCase() ) ? - markFunction(function( seed, matches ) { - var idx, - matched = fn( seed, argument ), - i = matched.length; - while ( i-- ) { - idx = indexOf.call( seed, matched[i] ); - seed[ idx ] = !( matches[ idx ] = matched[i] ); - } - }) : - function( elem ) { - return fn( elem, 0, args ); - }; - } - - return fn; - } - }, - - pseudos: { - // Potentially complex pseudos - "not": markFunction(function( selector ) { - // Trim the selector passed to compile - // to avoid treating leading and trailing - // spaces as combinators - var input = [], - results = [], - matcher = compile( selector.replace( rtrim, "$1" ) ); - - return matcher[ expando ] ? - markFunction(function( seed, matches, context, xml ) { - var elem, - unmatched = matcher( seed, null, xml, [] ), - i = seed.length; - - // Match elements unmatched by `matcher` - while ( i-- ) { - if ( (elem = unmatched[i]) ) { - seed[i] = !(matches[i] = elem); - } - } - }) : - function( elem, context, xml ) { - input[0] = elem; - matcher( input, null, xml, results ); - return !results.pop(); - }; - }), - - "has": markFunction(function( selector ) { - return function( elem ) { - return Sizzle( selector, elem ).length > 0; - }; - }), - - "contains": markFunction(function( text ) { - return function( elem ) { - return ( elem.textContent || elem.innerText || getText( elem ) ).indexOf( text ) > -1; - }; - }), - - // "Whether an element is represented by a :lang() selector - // is based solely on the element's language value - // being equal to the identifier C, - // or beginning with the identifier C immediately followed by "-". - // The matching of C against the element's language value is performed case-insensitively. - // The identifier C does not have to be a valid language name." - // http://www.w3.org/TR/selectors/#lang-pseudo - "lang": markFunction( function( lang ) { - // lang value must be a valid identifier - if ( !ridentifier.test(lang || "") ) { - Sizzle.error( "unsupported lang: " + lang ); - } - lang = lang.replace( runescape, funescape ).toLowerCase(); - return function( elem ) { - var elemLang; - do { - if ( (elemLang = documentIsHTML ? - elem.lang : - elem.getAttribute("xml:lang") || elem.getAttribute("lang")) ) { - - elemLang = elemLang.toLowerCase(); - return elemLang === lang || elemLang.indexOf( lang + "-" ) === 0; - } - } while ( (elem = elem.parentNode) && elem.nodeType === 1 ); - return false; - }; - }), - - // Miscellaneous - "target": function( elem ) { - var hash = window.location && window.location.hash; - return hash && hash.slice( 1 ) === elem.id; - }, - - "root": function( elem ) { - return elem === docElem; - }, - - "focus": function( elem ) { - return elem === document.activeElement && (!document.hasFocus || document.hasFocus()) && !!(elem.type || elem.href || ~elem.tabIndex); - }, - - // Boolean properties - "enabled": function( elem ) { - return elem.disabled === false; - }, - - "disabled": function( elem ) { - return elem.disabled === true; - }, - - "checked": function( elem ) { - // In CSS3, :checked should return both checked and selected elements - // http://www.w3.org/TR/2011/REC-css3-selectors-20110929/#checked - var nodeName = elem.nodeName.toLowerCase(); - return (nodeName === "input" && !!elem.checked) || (nodeName === "option" && !!elem.selected); - }, - - "selected": function( elem ) { - // Accessing this property makes selected-by-default - // options in Safari work properly - if ( elem.parentNode ) { - elem.parentNode.selectedIndex; - } - - return elem.selected === true; - }, - - // Contents - "empty": function( elem ) { - // http://www.w3.org/TR/selectors/#empty-pseudo - // :empty is only affected by element nodes and content nodes(including text(3), cdata(4)), - // not comment, processing instructions, or others - // Thanks to Diego Perini for the nodeName shortcut - // Greater than "@" means alpha characters (specifically not starting with "#" or "?") - for ( elem = elem.firstChild; elem; elem = elem.nextSibling ) { - if ( elem.nodeName > "@" || elem.nodeType === 3 || elem.nodeType === 4 ) { - return false; - } - } - return true; - }, - - "parent": function( elem ) { - return !Expr.pseudos["empty"]( elem ); - }, - - // Element/input types - "header": function( elem ) { - return rheader.test( elem.nodeName ); - }, - - "input": function( elem ) { - return rinputs.test( elem.nodeName ); - }, - - "button": function( elem ) { - var name = elem.nodeName.toLowerCase(); - return name === "input" && elem.type === "button" || name === "button"; - }, - - "text": function( elem ) { - var attr; - // IE6 and 7 will map elem.type to 'text' for new HTML5 types (search, etc) - // use getAttribute instead to test this case - return elem.nodeName.toLowerCase() === "input" && - elem.type === "text" && - ( (attr = elem.getAttribute("type")) == null || attr.toLowerCase() === elem.type ); - }, - - // Position-in-collection - "first": createPositionalPseudo(function() { - return [ 0 ]; - }), - - "last": createPositionalPseudo(function( matchIndexes, length ) { - return [ length - 1 ]; - }), - - "eq": createPositionalPseudo(function( matchIndexes, length, argument ) { - return [ argument < 0 ? argument + length : argument ]; - }), - - "even": createPositionalPseudo(function( matchIndexes, length ) { - var i = 0; - for ( ; i < length; i += 2 ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "odd": createPositionalPseudo(function( matchIndexes, length ) { - var i = 1; - for ( ; i < length; i += 2 ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "lt": createPositionalPseudo(function( matchIndexes, length, argument ) { - var i = argument < 0 ? argument + length : argument; - for ( ; --i >= 0; ) { - matchIndexes.push( i ); - } - return matchIndexes; - }), - - "gt": createPositionalPseudo(function( matchIndexes, length, argument ) { - var i = argument < 0 ? argument + length : argument; - for ( ; ++i < length; ) { - matchIndexes.push( i ); - } - return matchIndexes; - }) - } -}; - -Expr.pseudos["nth"] = Expr.pseudos["eq"]; - -// Add button/input type pseudos -for ( i in { radio: true, checkbox: true, file: true, password: true, image: true } ) { - Expr.pseudos[ i ] = createInputPseudo( i ); -} -for ( i in { submit: true, reset: true } ) { - Expr.pseudos[ i ] = createButtonPseudo( i ); -} - -// Easy API for creating new setFilters -function setFilters() {} -setFilters.prototype = Expr.filters = Expr.pseudos; -Expr.setFilters = new setFilters(); - -function tokenize( selector, parseOnly ) { - var matched, match, tokens, type, - soFar, groups, preFilters, - cached = tokenCache[ selector + " " ]; - - if ( cached ) { - return parseOnly ? 0 : cached.slice( 0 ); - } - - soFar = selector; - groups = []; - preFilters = Expr.preFilter; - - while ( soFar ) { - - // Comma and first run - if ( !matched || (match = rcomma.exec( soFar )) ) { - if ( match ) { - // Don't consume trailing commas as valid - soFar = soFar.slice( match[0].length ) || soFar; - } - groups.push( tokens = [] ); - } - - matched = false; - - // Combinators - if ( (match = rcombinators.exec( soFar )) ) { - matched = match.shift(); - tokens.push({ - value: matched, - // Cast descendant combinators to space - type: match[0].replace( rtrim, " " ) - }); - soFar = soFar.slice( matched.length ); - } - - // Filters - for ( type in Expr.filter ) { - if ( (match = matchExpr[ type ].exec( soFar )) && (!preFilters[ type ] || - (match = preFilters[ type ]( match ))) ) { - matched = match.shift(); - tokens.push({ - value: matched, - type: type, - matches: match - }); - soFar = soFar.slice( matched.length ); - } - } - - if ( !matched ) { - break; - } - } - - // Return the length of the invalid excess - // if we're just parsing - // Otherwise, throw an error or return tokens - return parseOnly ? - soFar.length : - soFar ? - Sizzle.error( selector ) : - // Cache the tokens - tokenCache( selector, groups ).slice( 0 ); -} - -function toSelector( tokens ) { - var i = 0, - len = tokens.length, - selector = ""; - for ( ; i < len; i++ ) { - selector += tokens[i].value; - } - return selector; -} - -function addCombinator( matcher, combinator, base ) { - var dir = combinator.dir, - checkNonElements = base && dir === "parentNode", - doneName = done++; - - return combinator.first ? - // Check against closest ancestor/preceding element - function( elem, context, xml ) { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - return matcher( elem, context, xml ); - } - } - } : - - // Check against all ancestor/preceding elements - function( elem, context, xml ) { - var data, cache, outerCache, - dirkey = dirruns + " " + doneName; - - // We can't set arbitrary data on XML nodes, so they don't benefit from dir caching - if ( xml ) { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - if ( matcher( elem, context, xml ) ) { - return true; - } - } - } - } else { - while ( (elem = elem[ dir ]) ) { - if ( elem.nodeType === 1 || checkNonElements ) { - outerCache = elem[ expando ] || (elem[ expando ] = {}); - if ( (cache = outerCache[ dir ]) && cache[0] === dirkey ) { - if ( (data = cache[1]) === true || data === cachedruns ) { - return data === true; - } - } else { - cache = outerCache[ dir ] = [ dirkey ]; - cache[1] = matcher( elem, context, xml ) || cachedruns; - if ( cache[1] === true ) { - return true; - } - } - } - } - } - }; -} - -function elementMatcher( matchers ) { - return matchers.length > 1 ? - function( elem, context, xml ) { - var i = matchers.length; - while ( i-- ) { - if ( !matchers[i]( elem, context, xml ) ) { - return false; - } - } - return true; - } : - matchers[0]; -} - -function condense( unmatched, map, filter, context, xml ) { - var elem, - newUnmatched = [], - i = 0, - len = unmatched.length, - mapped = map != null; - - for ( ; i < len; i++ ) { - if ( (elem = unmatched[i]) ) { - if ( !filter || filter( elem, context, xml ) ) { - newUnmatched.push( elem ); - if ( mapped ) { - map.push( i ); - } - } - } - } - - return newUnmatched; -} - -function setMatcher( preFilter, selector, matcher, postFilter, postFinder, postSelector ) { - if ( postFilter && !postFilter[ expando ] ) { - postFilter = setMatcher( postFilter ); - } - if ( postFinder && !postFinder[ expando ] ) { - postFinder = setMatcher( postFinder, postSelector ); - } - return markFunction(function( seed, results, context, xml ) { - var temp, i, elem, - preMap = [], - postMap = [], - preexisting = results.length, - - // Get initial elements from seed or context - elems = seed || multipleContexts( selector || "*", context.nodeType ? [ context ] : context, [] ), - - // Prefilter to get matcher input, preserving a map for seed-results synchronization - matcherIn = preFilter && ( seed || !selector ) ? - condense( elems, preMap, preFilter, context, xml ) : - elems, - - matcherOut = matcher ? - // If we have a postFinder, or filtered seed, or non-seed postFilter or preexisting results, - postFinder || ( seed ? preFilter : preexisting || postFilter ) ? - - // ...intermediate processing is necessary - [] : - - // ...otherwise use results directly - results : - matcherIn; - - // Find primary matches - if ( matcher ) { - matcher( matcherIn, matcherOut, context, xml ); - } - - // Apply postFilter - if ( postFilter ) { - temp = condense( matcherOut, postMap ); - postFilter( temp, [], context, xml ); - - // Un-match failing elements by moving them back to matcherIn - i = temp.length; - while ( i-- ) { - if ( (elem = temp[i]) ) { - matcherOut[ postMap[i] ] = !(matcherIn[ postMap[i] ] = elem); - } - } - } - - if ( seed ) { - if ( postFinder || preFilter ) { - if ( postFinder ) { - // Get the final matcherOut by condensing this intermediate into postFinder contexts - temp = []; - i = matcherOut.length; - while ( i-- ) { - if ( (elem = matcherOut[i]) ) { - // Restore matcherIn since elem is not yet a final match - temp.push( (matcherIn[i] = elem) ); - } - } - postFinder( null, (matcherOut = []), temp, xml ); - } - - // Move matched elements from seed to results to keep them synchronized - i = matcherOut.length; - while ( i-- ) { - if ( (elem = matcherOut[i]) && - (temp = postFinder ? indexOf.call( seed, elem ) : preMap[i]) > -1 ) { - - seed[temp] = !(results[temp] = elem); - } - } - } - - // Add elements to results, through postFinder if defined - } else { - matcherOut = condense( - matcherOut === results ? - matcherOut.splice( preexisting, matcherOut.length ) : - matcherOut - ); - if ( postFinder ) { - postFinder( null, results, matcherOut, xml ); - } else { - push.apply( results, matcherOut ); - } - } - }); -} - -function matcherFromTokens( tokens ) { - var checkContext, matcher, j, - len = tokens.length, - leadingRelative = Expr.relative[ tokens[0].type ], - implicitRelative = leadingRelative || Expr.relative[" "], - i = leadingRelative ? 1 : 0, - - // The foundational matcher ensures that elements are reachable from top-level context(s) - matchContext = addCombinator( function( elem ) { - return elem === checkContext; - }, implicitRelative, true ), - matchAnyContext = addCombinator( function( elem ) { - return indexOf.call( checkContext, elem ) > -1; - }, implicitRelative, true ), - matchers = [ function( elem, context, xml ) { - return ( !leadingRelative && ( xml || context !== outermostContext ) ) || ( - (checkContext = context).nodeType ? - matchContext( elem, context, xml ) : - matchAnyContext( elem, context, xml ) ); - } ]; - - for ( ; i < len; i++ ) { - if ( (matcher = Expr.relative[ tokens[i].type ]) ) { - matchers = [ addCombinator(elementMatcher( matchers ), matcher) ]; - } else { - matcher = Expr.filter[ tokens[i].type ].apply( null, tokens[i].matches ); - - // Return special upon seeing a positional matcher - if ( matcher[ expando ] ) { - // Find the next relative operator (if any) for proper handling - j = ++i; - for ( ; j < len; j++ ) { - if ( Expr.relative[ tokens[j].type ] ) { - break; - } - } - return setMatcher( - i > 1 && elementMatcher( matchers ), - i > 1 && toSelector( - // If the preceding token was a descendant combinator, insert an implicit any-element `*` - tokens.slice( 0, i - 1 ).concat({ value: tokens[ i - 2 ].type === " " ? "*" : "" }) - ).replace( rtrim, "$1" ), - matcher, - i < j && matcherFromTokens( tokens.slice( i, j ) ), - j < len && matcherFromTokens( (tokens = tokens.slice( j )) ), - j < len && toSelector( tokens ) - ); - } - matchers.push( matcher ); - } - } - - return elementMatcher( matchers ); -} - -function matcherFromGroupMatchers( elementMatchers, setMatchers ) { - // A counter to specify which element is currently being matched - var matcherCachedRuns = 0, - bySet = setMatchers.length > 0, - byElement = elementMatchers.length > 0, - superMatcher = function( seed, context, xml, results, expandContext ) { - var elem, j, matcher, - setMatched = [], - matchedCount = 0, - i = "0", - unmatched = seed && [], - outermost = expandContext != null, - contextBackup = outermostContext, - // We must always have either seed elements or context - elems = seed || byElement && Expr.find["TAG"]( "*", expandContext && context.parentNode || context ), - // Use integer dirruns iff this is the outermost matcher - dirrunsUnique = (dirruns += contextBackup == null ? 1 : Math.random() || 0.1); - - if ( outermost ) { - outermostContext = context !== document && context; - cachedruns = matcherCachedRuns; - } - - // Add elements passing elementMatchers directly to results - // Keep `i` a string if there are no elements so `matchedCount` will be "00" below - for ( ; (elem = elems[i]) != null; i++ ) { - if ( byElement && elem ) { - j = 0; - while ( (matcher = elementMatchers[j++]) ) { - if ( matcher( elem, context, xml ) ) { - results.push( elem ); - break; - } - } - if ( outermost ) { - dirruns = dirrunsUnique; - cachedruns = ++matcherCachedRuns; - } - } - - // Track unmatched elements for set filters - if ( bySet ) { - // They will have gone through all possible matchers - if ( (elem = !matcher && elem) ) { - matchedCount--; - } - - // Lengthen the array for every element, matched or not - if ( seed ) { - unmatched.push( elem ); - } - } - } - - // Apply set filters to unmatched elements - matchedCount += i; - if ( bySet && i !== matchedCount ) { - j = 0; - while ( (matcher = setMatchers[j++]) ) { - matcher( unmatched, setMatched, context, xml ); - } - - if ( seed ) { - // Reintegrate element matches to eliminate the need for sorting - if ( matchedCount > 0 ) { - while ( i-- ) { - if ( !(unmatched[i] || setMatched[i]) ) { - setMatched[i] = pop.call( results ); - } - } - } - - // Discard index placeholder values to get only actual matches - setMatched = condense( setMatched ); - } - - // Add matches to results - push.apply( results, setMatched ); - - // Seedless set matches succeeding multiple successful matchers stipulate sorting - if ( outermost && !seed && setMatched.length > 0 && - ( matchedCount + setMatchers.length ) > 1 ) { - - Sizzle.uniqueSort( results ); - } - } - - // Override manipulation of globals by nested matchers - if ( outermost ) { - dirruns = dirrunsUnique; - outermostContext = contextBackup; - } - - return unmatched; - }; - - return bySet ? - markFunction( superMatcher ) : - superMatcher; -} - -compile = Sizzle.compile = function( selector, group /* Internal Use Only */ ) { - var i, - setMatchers = [], - elementMatchers = [], - cached = compilerCache[ selector + " " ]; - - if ( !cached ) { - // Generate a function of recursive functions that can be used to check each element - if ( !group ) { - group = tokenize( selector ); - } - i = group.length; - while ( i-- ) { - cached = matcherFromTokens( group[i] ); - if ( cached[ expando ] ) { - setMatchers.push( cached ); - } else { - elementMatchers.push( cached ); - } - } - - // Cache the compiled function - cached = compilerCache( selector, matcherFromGroupMatchers( elementMatchers, setMatchers ) ); - } - return cached; -}; - -function multipleContexts( selector, contexts, results ) { - var i = 0, - len = contexts.length; - for ( ; i < len; i++ ) { - Sizzle( selector, contexts[i], results ); - } - return results; -} - -function select( selector, context, results, seed ) { - var i, tokens, token, type, find, - match = tokenize( selector ); - - if ( !seed ) { - // Try to minimize operations if there is only one group - if ( match.length === 1 ) { - - // Take a shortcut and set the context if the root selector is an ID - tokens = match[0] = match[0].slice( 0 ); - if ( tokens.length > 2 && (token = tokens[0]).type === "ID" && - support.getById && context.nodeType === 9 && documentIsHTML && - Expr.relative[ tokens[1].type ] ) { - - context = ( Expr.find["ID"]( token.matches[0].replace(runescape, funescape), context ) || [] )[0]; - if ( !context ) { - return results; - } - selector = selector.slice( tokens.shift().value.length ); - } - - // Fetch a seed set for right-to-left matching - i = matchExpr["needsContext"].test( selector ) ? 0 : tokens.length; - while ( i-- ) { - token = tokens[i]; - - // Abort if we hit a combinator - if ( Expr.relative[ (type = token.type) ] ) { - break; - } - if ( (find = Expr.find[ type ]) ) { - // Search, expanding context for leading sibling combinators - if ( (seed = find( - token.matches[0].replace( runescape, funescape ), - rsibling.test( tokens[0].type ) && context.parentNode || context - )) ) { - - // If seed is empty or no tokens remain, we can return early - tokens.splice( i, 1 ); - selector = seed.length && toSelector( tokens ); - if ( !selector ) { - push.apply( results, seed ); - return results; - } - - break; - } - } - } - } - } - - // Compile and execute a filtering function - // Provide `match` to avoid retokenization if we modified the selector above - compile( selector, match )( - seed, - context, - !documentIsHTML, - results, - rsibling.test( selector ) - ); - return results; -} - -// One-time assignments - -// Sort stability -support.sortStable = expando.split("").sort( sortOrder ).join("") === expando; - -// Support: Chrome<14 -// Always assume duplicates if they aren't passed to the comparison function -support.detectDuplicates = hasDuplicate; - -// Initialize against the default document -setDocument(); - -// Support: Webkit<537.32 - Safari 6.0.3/Chrome 25 (fixed in Chrome 27) -// Detached nodes confoundingly follow *each other* -support.sortDetached = assert(function( div1 ) { - // Should return 1, but returns 4 (following) - return div1.compareDocumentPosition( document.createElement("div") ) & 1; -}); - -// Support: IE<8 -// Prevent attribute/property "interpolation" -// http://msdn.microsoft.com/en-us/library/ms536429%28VS.85%29.aspx -if ( !assert(function( div ) { - div.innerHTML = ""; - return div.firstChild.getAttribute("href") === "#" ; -}) ) { - addHandle( "type|href|height|width", function( elem, name, isXML ) { - if ( !isXML ) { - return elem.getAttribute( name, name.toLowerCase() === "type" ? 1 : 2 ); - } - }); -} - -// Support: IE<9 -// Use defaultValue in place of getAttribute("value") -if ( !support.attributes || !assert(function( div ) { - div.innerHTML = ""; - div.firstChild.setAttribute( "value", "" ); - return div.firstChild.getAttribute( "value" ) === ""; -}) ) { - addHandle( "value", function( elem, name, isXML ) { - if ( !isXML && elem.nodeName.toLowerCase() === "input" ) { - return elem.defaultValue; - } - }); -} - -// Support: IE<9 -// Use getAttributeNode to fetch booleans when getAttribute lies -if ( !assert(function( div ) { - return div.getAttribute("disabled") == null; -}) ) { - addHandle( booleans, function( elem, name, isXML ) { - var val; - if ( !isXML ) { - return (val = elem.getAttributeNode( name )) && val.specified ? - val.value : - elem[ name ] === true ? name.toLowerCase() : null; - } - }); -} - -jQuery.find = Sizzle; -jQuery.expr = Sizzle.selectors; -jQuery.expr[":"] = jQuery.expr.pseudos; -jQuery.unique = Sizzle.uniqueSort; -jQuery.text = Sizzle.getText; -jQuery.isXMLDoc = Sizzle.isXML; -jQuery.contains = Sizzle.contains; - - -})( window ); -// String to Object options format cache -var optionsCache = {}; - -// Convert String-formatted options into Object-formatted ones and store in cache -function createOptions( options ) { - var object = optionsCache[ options ] = {}; - jQuery.each( options.match( core_rnotwhite ) || [], function( _, flag ) { - object[ flag ] = true; - }); - return object; -} - -/* - * Create a callback list using the following parameters: - * - * options: an optional list of space-separated options that will change how - * the callback list behaves or a more traditional option object - * - * By default a callback list will act like an event callback list and can be - * "fired" multiple times. - * - * Possible options: - * - * once: will ensure the callback list can only be fired once (like a Deferred) - * - * memory: will keep track of previous values and will call any callback added - * after the list has been fired right away with the latest "memorized" - * values (like a Deferred) - * - * unique: will ensure a callback can only be added once (no duplicate in the list) - * - * stopOnFalse: interrupt callings when a callback returns false - * - */ -jQuery.Callbacks = function( options ) { - - // Convert options from String-formatted to Object-formatted if needed - // (we check in cache first) - options = typeof options === "string" ? - ( optionsCache[ options ] || createOptions( options ) ) : - jQuery.extend( {}, options ); - - var // Flag to know if list is currently firing - firing, - // Last fire value (for non-forgettable lists) - memory, - // Flag to know if list was already fired - fired, - // End of the loop when firing - firingLength, - // Index of currently firing callback (modified by remove if needed) - firingIndex, - // First callback to fire (used internally by add and fireWith) - firingStart, - // Actual callback list - list = [], - // Stack of fire calls for repeatable lists - stack = !options.once && [], - // Fire callbacks - fire = function( data ) { - memory = options.memory && data; - fired = true; - firingIndex = firingStart || 0; - firingStart = 0; - firingLength = list.length; - firing = true; - for ( ; list && firingIndex < firingLength; firingIndex++ ) { - if ( list[ firingIndex ].apply( data[ 0 ], data[ 1 ] ) === false && options.stopOnFalse ) { - memory = false; // To prevent further calls using add - break; - } - } - firing = false; - if ( list ) { - if ( stack ) { - if ( stack.length ) { - fire( stack.shift() ); - } - } else if ( memory ) { - list = []; - } else { - self.disable(); - } - } - }, - // Actual Callbacks object - self = { - // Add a callback or a collection of callbacks to the list - add: function() { - if ( list ) { - // First, we save the current length - var start = list.length; - (function add( args ) { - jQuery.each( args, function( _, arg ) { - var type = jQuery.type( arg ); - if ( type === "function" ) { - if ( !options.unique || !self.has( arg ) ) { - list.push( arg ); - } - } else if ( arg && arg.length && type !== "string" ) { - // Inspect recursively - add( arg ); - } - }); - })( arguments ); - // Do we need to add the callbacks to the - // current firing batch? - if ( firing ) { - firingLength = list.length; - // With memory, if we're not firing then - // we should call right away - } else if ( memory ) { - firingStart = start; - fire( memory ); - } - } - return this; - }, - // Remove a callback from the list - remove: function() { - if ( list ) { - jQuery.each( arguments, function( _, arg ) { - var index; - while( ( index = jQuery.inArray( arg, list, index ) ) > -1 ) { - list.splice( index, 1 ); - // Handle firing indexes - if ( firing ) { - if ( index <= firingLength ) { - firingLength--; - } - if ( index <= firingIndex ) { - firingIndex--; - } - } - } - }); - } - return this; - }, - // Check if a given callback is in the list. - // If no argument is given, return whether or not list has callbacks attached. - has: function( fn ) { - return fn ? jQuery.inArray( fn, list ) > -1 : !!( list && list.length ); - }, - // Remove all callbacks from the list - empty: function() { - list = []; - firingLength = 0; - return this; - }, - // Have the list do nothing anymore - disable: function() { - list = stack = memory = undefined; - return this; - }, - // Is it disabled? - disabled: function() { - return !list; - }, - // Lock the list in its current state - lock: function() { - stack = undefined; - if ( !memory ) { - self.disable(); - } - return this; - }, - // Is it locked? - locked: function() { - return !stack; - }, - // Call all callbacks with the given context and arguments - fireWith: function( context, args ) { - if ( list && ( !fired || stack ) ) { - args = args || []; - args = [ context, args.slice ? args.slice() : args ]; - if ( firing ) { - stack.push( args ); - } else { - fire( args ); - } - } - return this; - }, - // Call all the callbacks with the given arguments - fire: function() { - self.fireWith( this, arguments ); - return this; - }, - // To know if the callbacks have already been called at least once - fired: function() { - return !!fired; - } - }; - - return self; -}; -jQuery.extend({ - - Deferred: function( func ) { - var tuples = [ - // action, add listener, listener list, final state - [ "resolve", "done", jQuery.Callbacks("once memory"), "resolved" ], - [ "reject", "fail", jQuery.Callbacks("once memory"), "rejected" ], - [ "notify", "progress", jQuery.Callbacks("memory") ] - ], - state = "pending", - promise = { - state: function() { - return state; - }, - always: function() { - deferred.done( arguments ).fail( arguments ); - return this; - }, - then: function( /* fnDone, fnFail, fnProgress */ ) { - var fns = arguments; - return jQuery.Deferred(function( newDefer ) { - jQuery.each( tuples, function( i, tuple ) { - var action = tuple[ 0 ], - fn = jQuery.isFunction( fns[ i ] ) && fns[ i ]; - // deferred[ done | fail | progress ] for forwarding actions to newDefer - deferred[ tuple[1] ](function() { - var returned = fn && fn.apply( this, arguments ); - if ( returned && jQuery.isFunction( returned.promise ) ) { - returned.promise() - .done( newDefer.resolve ) - .fail( newDefer.reject ) - .progress( newDefer.notify ); - } else { - newDefer[ action + "With" ]( this === promise ? newDefer.promise() : this, fn ? [ returned ] : arguments ); - } - }); - }); - fns = null; - }).promise(); - }, - // Get a promise for this deferred - // If obj is provided, the promise aspect is added to the object - promise: function( obj ) { - return obj != null ? jQuery.extend( obj, promise ) : promise; - } - }, - deferred = {}; - - // Keep pipe for back-compat - promise.pipe = promise.then; - - // Add list-specific methods - jQuery.each( tuples, function( i, tuple ) { - var list = tuple[ 2 ], - stateString = tuple[ 3 ]; - - // promise[ done | fail | progress ] = list.add - promise[ tuple[1] ] = list.add; - - // Handle state - if ( stateString ) { - list.add(function() { - // state = [ resolved | rejected ] - state = stateString; - - // [ reject_list | resolve_list ].disable; progress_list.lock - }, tuples[ i ^ 1 ][ 2 ].disable, tuples[ 2 ][ 2 ].lock ); - } - - // deferred[ resolve | reject | notify ] - deferred[ tuple[0] ] = function() { - deferred[ tuple[0] + "With" ]( this === deferred ? promise : this, arguments ); - return this; - }; - deferred[ tuple[0] + "With" ] = list.fireWith; - }); - - // Make the deferred a promise - promise.promise( deferred ); - - // Call given func if any - if ( func ) { - func.call( deferred, deferred ); - } - - // All done! - return deferred; - }, - - // Deferred helper - when: function( subordinate /* , ..., subordinateN */ ) { - var i = 0, - resolveValues = core_slice.call( arguments ), - length = resolveValues.length, - - // the count of uncompleted subordinates - remaining = length !== 1 || ( subordinate && jQuery.isFunction( subordinate.promise ) ) ? length : 0, - - // the master Deferred. If resolveValues consist of only a single Deferred, just use that. - deferred = remaining === 1 ? subordinate : jQuery.Deferred(), - - // Update function for both resolve and progress values - updateFunc = function( i, contexts, values ) { - return function( value ) { - contexts[ i ] = this; - values[ i ] = arguments.length > 1 ? core_slice.call( arguments ) : value; - if( values === progressValues ) { - deferred.notifyWith( contexts, values ); - } else if ( !( --remaining ) ) { - deferred.resolveWith( contexts, values ); - } - }; - }, - - progressValues, progressContexts, resolveContexts; - - // add listeners to Deferred subordinates; treat others as resolved - if ( length > 1 ) { - progressValues = new Array( length ); - progressContexts = new Array( length ); - resolveContexts = new Array( length ); - for ( ; i < length; i++ ) { - if ( resolveValues[ i ] && jQuery.isFunction( resolveValues[ i ].promise ) ) { - resolveValues[ i ].promise() - .done( updateFunc( i, resolveContexts, resolveValues ) ) - .fail( deferred.reject ) - .progress( updateFunc( i, progressContexts, progressValues ) ); - } else { - --remaining; - } - } - } - - // if we're not waiting on anything, resolve the master - if ( !remaining ) { - deferred.resolveWith( resolveContexts, resolveValues ); - } - - return deferred.promise(); - } -}); -jQuery.support = (function( support ) { - - var all, a, input, select, fragment, opt, eventName, isSupported, i, - div = document.createElement("div"); - - // Setup - div.setAttribute( "className", "t" ); - div.innerHTML = "
a"; - - // Finish early in limited (non-browser) environments - all = div.getElementsByTagName("*") || []; - a = div.getElementsByTagName("a")[ 0 ]; - if ( !a || !a.style || !all.length ) { - return support; - } - - // First batch of tests - select = document.createElement("select"); - opt = select.appendChild( document.createElement("option") ); - input = div.getElementsByTagName("input")[ 0 ]; - - a.style.cssText = "top:1px;float:left;opacity:.5"; - - // Test setAttribute on camelCase class. If it works, we need attrFixes when doing get/setAttribute (ie6/7) - support.getSetAttribute = div.className !== "t"; - - // IE strips leading whitespace when .innerHTML is used - support.leadingWhitespace = div.firstChild.nodeType === 3; - - // Make sure that tbody elements aren't automatically inserted - // IE will insert them into empty tables - support.tbody = !div.getElementsByTagName("tbody").length; - - // Make sure that link elements get serialized correctly by innerHTML - // This requires a wrapper element in IE - support.htmlSerialize = !!div.getElementsByTagName("link").length; - - // Get the style information from getAttribute - // (IE uses .cssText instead) - support.style = /top/.test( a.getAttribute("style") ); - - // Make sure that URLs aren't manipulated - // (IE normalizes it by default) - support.hrefNormalized = a.getAttribute("href") === "/a"; - - // Make sure that element opacity exists - // (IE uses filter instead) - // Use a regex to work around a WebKit issue. See #5145 - support.opacity = /^0.5/.test( a.style.opacity ); - - // Verify style float existence - // (IE uses styleFloat instead of cssFloat) - support.cssFloat = !!a.style.cssFloat; - - // Check the default checkbox/radio value ("" on WebKit; "on" elsewhere) - support.checkOn = !!input.value; - - // Make sure that a selected-by-default option has a working selected property. - // (WebKit defaults to false instead of true, IE too, if it's in an optgroup) - support.optSelected = opt.selected; - - // Tests for enctype support on a form (#6743) - support.enctype = !!document.createElement("form").enctype; - - // Makes sure cloning an html5 element does not cause problems - // Where outerHTML is undefined, this still works - support.html5Clone = document.createElement("nav").cloneNode( true ).outerHTML !== "<:nav>"; - - // Will be defined later - support.inlineBlockNeedsLayout = false; - support.shrinkWrapBlocks = false; - support.pixelPosition = false; - support.deleteExpando = true; - support.noCloneEvent = true; - support.reliableMarginRight = true; - support.boxSizingReliable = true; - - // Make sure checked status is properly cloned - input.checked = true; - support.noCloneChecked = input.cloneNode( true ).checked; - - // Make sure that the options inside disabled selects aren't marked as disabled - // (WebKit marks them as disabled) - select.disabled = true; - support.optDisabled = !opt.disabled; - - // Support: IE<9 - try { - delete div.test; - } catch( e ) { - support.deleteExpando = false; - } - - // Check if we can trust getAttribute("value") - input = document.createElement("input"); - input.setAttribute( "value", "" ); - support.input = input.getAttribute( "value" ) === ""; - - // Check if an input maintains its value after becoming a radio - input.value = "t"; - input.setAttribute( "type", "radio" ); - support.radioValue = input.value === "t"; - - // #11217 - WebKit loses check when the name is after the checked attribute - input.setAttribute( "checked", "t" ); - input.setAttribute( "name", "t" ); - - fragment = document.createDocumentFragment(); - fragment.appendChild( input ); - - // Check if a disconnected checkbox will retain its checked - // value of true after appended to the DOM (IE6/7) - support.appendChecked = input.checked; - - // WebKit doesn't clone checked state correctly in fragments - support.checkClone = fragment.cloneNode( true ).cloneNode( true ).lastChild.checked; - - // Support: IE<9 - // Opera does not clone events (and typeof div.attachEvent === undefined). - // IE9-10 clones events bound via attachEvent, but they don't trigger with .click() - if ( div.attachEvent ) { - div.attachEvent( "onclick", function() { - support.noCloneEvent = false; - }); - - div.cloneNode( true ).click(); - } - - // Support: IE<9 (lack submit/change bubble), Firefox 17+ (lack focusin event) - // Beware of CSP restrictions (https://developer.mozilla.org/en/Security/CSP) - for ( i in { submit: true, change: true, focusin: true }) { - div.setAttribute( eventName = "on" + i, "t" ); - - support[ i + "Bubbles" ] = eventName in window || div.attributes[ eventName ].expando === false; - } - - div.style.backgroundClip = "content-box"; - div.cloneNode( true ).style.backgroundClip = ""; - support.clearCloneStyle = div.style.backgroundClip === "content-box"; - - // Support: IE<9 - // Iteration over object's inherited properties before its own. - for ( i in jQuery( support ) ) { - break; - } - support.ownLast = i !== "0"; - - // Run tests that need a body at doc ready - jQuery(function() { - var container, marginDiv, tds, - divReset = "padding:0;margin:0;border:0;display:block;box-sizing:content-box;-moz-box-sizing:content-box;-webkit-box-sizing:content-box;", - body = document.getElementsByTagName("body")[0]; - - if ( !body ) { - // Return for frameset docs that don't have a body - return; - } - - container = document.createElement("div"); - container.style.cssText = "border:0;width:0;height:0;position:absolute;top:0;left:-9999px;margin-top:1px"; - - body.appendChild( container ).appendChild( div ); - - // Support: IE8 - // Check if table cells still have offsetWidth/Height when they are set - // to display:none and there are still other visible table cells in a - // table row; if so, offsetWidth/Height are not reliable for use when - // determining if an element has been hidden directly using - // display:none (it is still safe to use offsets if a parent element is - // hidden; don safety goggles and see bug #4512 for more information). - div.innerHTML = "
t
"; - tds = div.getElementsByTagName("td"); - tds[ 0 ].style.cssText = "padding:0;margin:0;border:0;display:none"; - isSupported = ( tds[ 0 ].offsetHeight === 0 ); - - tds[ 0 ].style.display = ""; - tds[ 1 ].style.display = "none"; - - // Support: IE8 - // Check if empty table cells still have offsetWidth/Height - support.reliableHiddenOffsets = isSupported && ( tds[ 0 ].offsetHeight === 0 ); - - // Check box-sizing and margin behavior. - div.innerHTML = ""; - div.style.cssText = "box-sizing:border-box;-moz-box-sizing:border-box;-webkit-box-sizing:border-box;padding:1px;border:1px;display:block;width:4px;margin-top:1%;position:absolute;top:1%;"; - - // Workaround failing boxSizing test due to offsetWidth returning wrong value - // with some non-1 values of body zoom, ticket #13543 - jQuery.swap( body, body.style.zoom != null ? { zoom: 1 } : {}, function() { - support.boxSizing = div.offsetWidth === 4; - }); - - // Use window.getComputedStyle because jsdom on node.js will break without it. - if ( window.getComputedStyle ) { - support.pixelPosition = ( window.getComputedStyle( div, null ) || {} ).top !== "1%"; - support.boxSizingReliable = ( window.getComputedStyle( div, null ) || { width: "4px" } ).width === "4px"; - - // Check if div with explicit width and no margin-right incorrectly - // gets computed margin-right based on width of container. (#3333) - // Fails in WebKit before Feb 2011 nightlies - // WebKit Bug 13343 - getComputedStyle returns wrong value for margin-right - marginDiv = div.appendChild( document.createElement("div") ); - marginDiv.style.cssText = div.style.cssText = divReset; - marginDiv.style.marginRight = marginDiv.style.width = "0"; - div.style.width = "1px"; - - support.reliableMarginRight = - !parseFloat( ( window.getComputedStyle( marginDiv, null ) || {} ).marginRight ); - } - - if ( typeof div.style.zoom !== core_strundefined ) { - // Support: IE<8 - // Check if natively block-level elements act like inline-block - // elements when setting their display to 'inline' and giving - // them layout - div.innerHTML = ""; - div.style.cssText = divReset + "width:1px;padding:1px;display:inline;zoom:1"; - support.inlineBlockNeedsLayout = ( div.offsetWidth === 3 ); - - // Support: IE6 - // Check if elements with layout shrink-wrap their children - div.style.display = "block"; - div.innerHTML = "
"; - div.firstChild.style.width = "5px"; - support.shrinkWrapBlocks = ( div.offsetWidth !== 3 ); - - if ( support.inlineBlockNeedsLayout ) { - // Prevent IE 6 from affecting layout for positioned elements #11048 - // Prevent IE from shrinking the body in IE 7 mode #12869 - // Support: IE<8 - body.style.zoom = 1; - } - } - - body.removeChild( container ); - - // Null elements to avoid leaks in IE - container = div = tds = marginDiv = null; - }); - - // Null elements to avoid leaks in IE - all = select = fragment = opt = a = input = null; - - return support; -})({}); - -var rbrace = /(?:\{[\s\S]*\}|\[[\s\S]*\])$/, - rmultiDash = /([A-Z])/g; - -function internalData( elem, name, data, pvt /* Internal Use Only */ ){ - if ( !jQuery.acceptData( elem ) ) { - return; - } - - var ret, thisCache, - internalKey = jQuery.expando, - - // We have to handle DOM nodes and JS objects differently because IE6-7 - // can't GC object references properly across the DOM-JS boundary - isNode = elem.nodeType, - - // Only DOM nodes need the global jQuery cache; JS object data is - // attached directly to the object so GC can occur automatically - cache = isNode ? jQuery.cache : elem, - - // Only defining an ID for JS objects if its cache already exists allows - // the code to shortcut on the same path as a DOM node with no cache - id = isNode ? elem[ internalKey ] : elem[ internalKey ] && internalKey; - - // Avoid doing any more work than we need to when trying to get data on an - // object that has no data at all - if ( (!id || !cache[id] || (!pvt && !cache[id].data)) && data === undefined && typeof name === "string" ) { - return; - } - - if ( !id ) { - // Only DOM nodes need a new unique ID for each element since their data - // ends up in the global cache - if ( isNode ) { - id = elem[ internalKey ] = core_deletedIds.pop() || jQuery.guid++; - } else { - id = internalKey; - } - } - - if ( !cache[ id ] ) { - // Avoid exposing jQuery metadata on plain JS objects when the object - // is serialized using JSON.stringify - cache[ id ] = isNode ? {} : { toJSON: jQuery.noop }; - } - - // An object can be passed to jQuery.data instead of a key/value pair; this gets - // shallow copied over onto the existing cache - if ( typeof name === "object" || typeof name === "function" ) { - if ( pvt ) { - cache[ id ] = jQuery.extend( cache[ id ], name ); - } else { - cache[ id ].data = jQuery.extend( cache[ id ].data, name ); - } - } - - thisCache = cache[ id ]; - - // jQuery data() is stored in a separate object inside the object's internal data - // cache in order to avoid key collisions between internal data and user-defined - // data. - if ( !pvt ) { - if ( !thisCache.data ) { - thisCache.data = {}; - } - - thisCache = thisCache.data; - } - - if ( data !== undefined ) { - thisCache[ jQuery.camelCase( name ) ] = data; - } - - // Check for both converted-to-camel and non-converted data property names - // If a data property was specified - if ( typeof name === "string" ) { - - // First Try to find as-is property data - ret = thisCache[ name ]; - - // Test for null|undefined property data - if ( ret == null ) { - - // Try to find the camelCased property - ret = thisCache[ jQuery.camelCase( name ) ]; - } - } else { - ret = thisCache; - } - - return ret; -} - -function internalRemoveData( elem, name, pvt ) { - if ( !jQuery.acceptData( elem ) ) { - return; - } - - var thisCache, i, - isNode = elem.nodeType, - - // See jQuery.data for more information - cache = isNode ? jQuery.cache : elem, - id = isNode ? elem[ jQuery.expando ] : jQuery.expando; - - // If there is already no cache entry for this object, there is no - // purpose in continuing - if ( !cache[ id ] ) { - return; - } - - if ( name ) { - - thisCache = pvt ? cache[ id ] : cache[ id ].data; - - if ( thisCache ) { - - // Support array or space separated string names for data keys - if ( !jQuery.isArray( name ) ) { - - // try the string as a key before any manipulation - if ( name in thisCache ) { - name = [ name ]; - } else { - - // split the camel cased version by spaces unless a key with the spaces exists - name = jQuery.camelCase( name ); - if ( name in thisCache ) { - name = [ name ]; - } else { - name = name.split(" "); - } - } - } else { - // If "name" is an array of keys... - // When data is initially created, via ("key", "val") signature, - // keys will be converted to camelCase. - // Since there is no way to tell _how_ a key was added, remove - // both plain key and camelCase key. #12786 - // This will only penalize the array argument path. - name = name.concat( jQuery.map( name, jQuery.camelCase ) ); - } - - i = name.length; - while ( i-- ) { - delete thisCache[ name[i] ]; - } - - // If there is no data left in the cache, we want to continue - // and let the cache object itself get destroyed - if ( pvt ? !isEmptyDataObject(thisCache) : !jQuery.isEmptyObject(thisCache) ) { - return; - } - } - } - - // See jQuery.data for more information - if ( !pvt ) { - delete cache[ id ].data; - - // Don't destroy the parent cache unless the internal data object - // had been the only thing left in it - if ( !isEmptyDataObject( cache[ id ] ) ) { - return; - } - } - - // Destroy the cache - if ( isNode ) { - jQuery.cleanData( [ elem ], true ); - - // Use delete when supported for expandos or `cache` is not a window per isWindow (#10080) - /* jshint eqeqeq: false */ - } else if ( jQuery.support.deleteExpando || cache != cache.window ) { - /* jshint eqeqeq: true */ - delete cache[ id ]; - - // When all else fails, null - } else { - cache[ id ] = null; - } -} - -jQuery.extend({ - cache: {}, - - // The following elements throw uncatchable exceptions if you - // attempt to add expando properties to them. - noData: { - "applet": true, - "embed": true, - // Ban all objects except for Flash (which handle expandos) - "object": "clsid:D27CDB6E-AE6D-11cf-96B8-444553540000" - }, - - hasData: function( elem ) { - elem = elem.nodeType ? jQuery.cache[ elem[jQuery.expando] ] : elem[ jQuery.expando ]; - return !!elem && !isEmptyDataObject( elem ); - }, - - data: function( elem, name, data ) { - return internalData( elem, name, data ); - }, - - removeData: function( elem, name ) { - return internalRemoveData( elem, name ); - }, - - // For internal use only. - _data: function( elem, name, data ) { - return internalData( elem, name, data, true ); - }, - - _removeData: function( elem, name ) { - return internalRemoveData( elem, name, true ); - }, - - // A method for determining if a DOM node can handle the data expando - acceptData: function( elem ) { - // Do not set data on non-element because it will not be cleared (#8335). - if ( elem.nodeType && elem.nodeType !== 1 && elem.nodeType !== 9 ) { - return false; - } - - var noData = elem.nodeName && jQuery.noData[ elem.nodeName.toLowerCase() ]; - - // nodes accept data unless otherwise specified; rejection can be conditional - return !noData || noData !== true && elem.getAttribute("classid") === noData; - } -}); - -jQuery.fn.extend({ - data: function( key, value ) { - var attrs, name, - data = null, - i = 0, - elem = this[0]; - - // Special expections of .data basically thwart jQuery.access, - // so implement the relevant behavior ourselves - - // Gets all values - if ( key === undefined ) { - if ( this.length ) { - data = jQuery.data( elem ); - - if ( elem.nodeType === 1 && !jQuery._data( elem, "parsedAttrs" ) ) { - attrs = elem.attributes; - for ( ; i < attrs.length; i++ ) { - name = attrs[i].name; - - if ( name.indexOf("data-") === 0 ) { - name = jQuery.camelCase( name.slice(5) ); - - dataAttr( elem, name, data[ name ] ); - } - } - jQuery._data( elem, "parsedAttrs", true ); - } - } - - return data; - } - - // Sets multiple values - if ( typeof key === "object" ) { - return this.each(function() { - jQuery.data( this, key ); - }); - } - - return arguments.length > 1 ? - - // Sets one value - this.each(function() { - jQuery.data( this, key, value ); - }) : - - // Gets one value - // Try to fetch any internally stored data first - elem ? dataAttr( elem, key, jQuery.data( elem, key ) ) : null; - }, - - removeData: function( key ) { - return this.each(function() { - jQuery.removeData( this, key ); - }); - } -}); - -function dataAttr( elem, key, data ) { - // If nothing was found internally, try to fetch any - // data from the HTML5 data-* attribute - if ( data === undefined && elem.nodeType === 1 ) { - - var name = "data-" + key.replace( rmultiDash, "-$1" ).toLowerCase(); - - data = elem.getAttribute( name ); - - if ( typeof data === "string" ) { - try { - data = data === "true" ? true : - data === "false" ? false : - data === "null" ? null : - // Only convert to a number if it doesn't change the string - +data + "" === data ? +data : - rbrace.test( data ) ? jQuery.parseJSON( data ) : - data; - } catch( e ) {} - - // Make sure we set the data so it isn't changed later - jQuery.data( elem, key, data ); - - } else { - data = undefined; - } - } - - return data; -} - -// checks a cache object for emptiness -function isEmptyDataObject( obj ) { - var name; - for ( name in obj ) { - - // if the public data object is empty, the private is still empty - if ( name === "data" && jQuery.isEmptyObject( obj[name] ) ) { - continue; - } - if ( name !== "toJSON" ) { - return false; - } - } - - return true; -} -jQuery.extend({ - queue: function( elem, type, data ) { - var queue; - - if ( elem ) { - type = ( type || "fx" ) + "queue"; - queue = jQuery._data( elem, type ); - - // Speed up dequeue by getting out quickly if this is just a lookup - if ( data ) { - if ( !queue || jQuery.isArray(data) ) { - queue = jQuery._data( elem, type, jQuery.makeArray(data) ); - } else { - queue.push( data ); - } - } - return queue || []; - } - }, - - dequeue: function( elem, type ) { - type = type || "fx"; - - var queue = jQuery.queue( elem, type ), - startLength = queue.length, - fn = queue.shift(), - hooks = jQuery._queueHooks( elem, type ), - next = function() { - jQuery.dequeue( elem, type ); - }; - - // If the fx queue is dequeued, always remove the progress sentinel - if ( fn === "inprogress" ) { - fn = queue.shift(); - startLength--; - } - - if ( fn ) { - - // Add a progress sentinel to prevent the fx queue from being - // automatically dequeued - if ( type === "fx" ) { - queue.unshift( "inprogress" ); - } - - // clear up the last queue stop function - delete hooks.stop; - fn.call( elem, next, hooks ); - } - - if ( !startLength && hooks ) { - hooks.empty.fire(); - } - }, - - // not intended for public consumption - generates a queueHooks object, or returns the current one - _queueHooks: function( elem, type ) { - var key = type + "queueHooks"; - return jQuery._data( elem, key ) || jQuery._data( elem, key, { - empty: jQuery.Callbacks("once memory").add(function() { - jQuery._removeData( elem, type + "queue" ); - jQuery._removeData( elem, key ); - }) - }); - } -}); - -jQuery.fn.extend({ - queue: function( type, data ) { - var setter = 2; - - if ( typeof type !== "string" ) { - data = type; - type = "fx"; - setter--; - } - - if ( arguments.length < setter ) { - return jQuery.queue( this[0], type ); - } - - return data === undefined ? - this : - this.each(function() { - var queue = jQuery.queue( this, type, data ); - - // ensure a hooks for this queue - jQuery._queueHooks( this, type ); - - if ( type === "fx" && queue[0] !== "inprogress" ) { - jQuery.dequeue( this, type ); - } - }); - }, - dequeue: function( type ) { - return this.each(function() { - jQuery.dequeue( this, type ); - }); - }, - // Based off of the plugin by Clint Helfers, with permission. - // http://blindsignals.com/index.php/2009/07/jquery-delay/ - delay: function( time, type ) { - time = jQuery.fx ? jQuery.fx.speeds[ time ] || time : time; - type = type || "fx"; - - return this.queue( type, function( next, hooks ) { - var timeout = setTimeout( next, time ); - hooks.stop = function() { - clearTimeout( timeout ); - }; - }); - }, - clearQueue: function( type ) { - return this.queue( type || "fx", [] ); - }, - // Get a promise resolved when queues of a certain type - // are emptied (fx is the type by default) - promise: function( type, obj ) { - var tmp, - count = 1, - defer = jQuery.Deferred(), - elements = this, - i = this.length, - resolve = function() { - if ( !( --count ) ) { - defer.resolveWith( elements, [ elements ] ); - } - }; - - if ( typeof type !== "string" ) { - obj = type; - type = undefined; - } - type = type || "fx"; - - while( i-- ) { - tmp = jQuery._data( elements[ i ], type + "queueHooks" ); - if ( tmp && tmp.empty ) { - count++; - tmp.empty.add( resolve ); - } - } - resolve(); - return defer.promise( obj ); - } -}); -var nodeHook, boolHook, - rclass = /[\t\r\n\f]/g, - rreturn = /\r/g, - rfocusable = /^(?:input|select|textarea|button|object)$/i, - rclickable = /^(?:a|area)$/i, - ruseDefault = /^(?:checked|selected)$/i, - getSetAttribute = jQuery.support.getSetAttribute, - getSetInput = jQuery.support.input; - -jQuery.fn.extend({ - attr: function( name, value ) { - return jQuery.access( this, jQuery.attr, name, value, arguments.length > 1 ); - }, - - removeAttr: function( name ) { - return this.each(function() { - jQuery.removeAttr( this, name ); - }); - }, - - prop: function( name, value ) { - return jQuery.access( this, jQuery.prop, name, value, arguments.length > 1 ); - }, - - removeProp: function( name ) { - name = jQuery.propFix[ name ] || name; - return this.each(function() { - // try/catch handles cases where IE balks (such as removing a property on window) - try { - this[ name ] = undefined; - delete this[ name ]; - } catch( e ) {} - }); - }, - - addClass: function( value ) { - var classes, elem, cur, clazz, j, - i = 0, - len = this.length, - proceed = typeof value === "string" && value; - - if ( jQuery.isFunction( value ) ) { - return this.each(function( j ) { - jQuery( this ).addClass( value.call( this, j, this.className ) ); - }); - } - - if ( proceed ) { - // The disjunction here is for better compressibility (see removeClass) - classes = ( value || "" ).match( core_rnotwhite ) || []; - - for ( ; i < len; i++ ) { - elem = this[ i ]; - cur = elem.nodeType === 1 && ( elem.className ? - ( " " + elem.className + " " ).replace( rclass, " " ) : - " " - ); - - if ( cur ) { - j = 0; - while ( (clazz = classes[j++]) ) { - if ( cur.indexOf( " " + clazz + " " ) < 0 ) { - cur += clazz + " "; - } - } - elem.className = jQuery.trim( cur ); - - } - } - } - - return this; - }, - - removeClass: function( value ) { - var classes, elem, cur, clazz, j, - i = 0, - len = this.length, - proceed = arguments.length === 0 || typeof value === "string" && value; - - if ( jQuery.isFunction( value ) ) { - return this.each(function( j ) { - jQuery( this ).removeClass( value.call( this, j, this.className ) ); - }); - } - if ( proceed ) { - classes = ( value || "" ).match( core_rnotwhite ) || []; - - for ( ; i < len; i++ ) { - elem = this[ i ]; - // This expression is here for better compressibility (see addClass) - cur = elem.nodeType === 1 && ( elem.className ? - ( " " + elem.className + " " ).replace( rclass, " " ) : - "" - ); - - if ( cur ) { - j = 0; - while ( (clazz = classes[j++]) ) { - // Remove *all* instances - while ( cur.indexOf( " " + clazz + " " ) >= 0 ) { - cur = cur.replace( " " + clazz + " ", " " ); - } - } - elem.className = value ? jQuery.trim( cur ) : ""; - } - } - } - - return this; - }, - - toggleClass: function( value, stateVal ) { - var type = typeof value; - - if ( typeof stateVal === "boolean" && type === "string" ) { - return stateVal ? this.addClass( value ) : this.removeClass( value ); - } - - if ( jQuery.isFunction( value ) ) { - return this.each(function( i ) { - jQuery( this ).toggleClass( value.call(this, i, this.className, stateVal), stateVal ); - }); - } - - return this.each(function() { - if ( type === "string" ) { - // toggle individual class names - var className, - i = 0, - self = jQuery( this ), - classNames = value.match( core_rnotwhite ) || []; - - while ( (className = classNames[ i++ ]) ) { - // check each className given, space separated list - if ( self.hasClass( className ) ) { - self.removeClass( className ); - } else { - self.addClass( className ); - } - } - - // Toggle whole class name - } else if ( type === core_strundefined || type === "boolean" ) { - if ( this.className ) { - // store className if set - jQuery._data( this, "__className__", this.className ); - } - - // If the element has a class name or if we're passed "false", - // then remove the whole classname (if there was one, the above saved it). - // Otherwise bring back whatever was previously saved (if anything), - // falling back to the empty string if nothing was stored. - this.className = this.className || value === false ? "" : jQuery._data( this, "__className__" ) || ""; - } - }); - }, - - hasClass: function( selector ) { - var className = " " + selector + " ", - i = 0, - l = this.length; - for ( ; i < l; i++ ) { - if ( this[i].nodeType === 1 && (" " + this[i].className + " ").replace(rclass, " ").indexOf( className ) >= 0 ) { - return true; - } - } - - return false; - }, - - val: function( value ) { - var ret, hooks, isFunction, - elem = this[0]; - - if ( !arguments.length ) { - if ( elem ) { - hooks = jQuery.valHooks[ elem.type ] || jQuery.valHooks[ elem.nodeName.toLowerCase() ]; - - if ( hooks && "get" in hooks && (ret = hooks.get( elem, "value" )) !== undefined ) { - return ret; - } - - ret = elem.value; - - return typeof ret === "string" ? - // handle most common string cases - ret.replace(rreturn, "") : - // handle cases where value is null/undef or number - ret == null ? "" : ret; - } - - return; - } - - isFunction = jQuery.isFunction( value ); - - return this.each(function( i ) { - var val; - - if ( this.nodeType !== 1 ) { - return; - } - - if ( isFunction ) { - val = value.call( this, i, jQuery( this ).val() ); - } else { - val = value; - } - - // Treat null/undefined as ""; convert numbers to string - if ( val == null ) { - val = ""; - } else if ( typeof val === "number" ) { - val += ""; - } else if ( jQuery.isArray( val ) ) { - val = jQuery.map(val, function ( value ) { - return value == null ? "" : value + ""; - }); - } - - hooks = jQuery.valHooks[ this.type ] || jQuery.valHooks[ this.nodeName.toLowerCase() ]; - - // If set returns undefined, fall back to normal setting - if ( !hooks || !("set" in hooks) || hooks.set( this, val, "value" ) === undefined ) { - this.value = val; - } - }); - } -}); - -jQuery.extend({ - valHooks: { - option: { - get: function( elem ) { - // Use proper attribute retrieval(#6932, #12072) - var val = jQuery.find.attr( elem, "value" ); - return val != null ? - val : - elem.text; - } - }, - select: { - get: function( elem ) { - var value, option, - options = elem.options, - index = elem.selectedIndex, - one = elem.type === "select-one" || index < 0, - values = one ? null : [], - max = one ? index + 1 : options.length, - i = index < 0 ? - max : - one ? index : 0; - - // Loop through all the selected options - for ( ; i < max; i++ ) { - option = options[ i ]; - - // oldIE doesn't update selected after form reset (#2551) - if ( ( option.selected || i === index ) && - // Don't return options that are disabled or in a disabled optgroup - ( jQuery.support.optDisabled ? !option.disabled : option.getAttribute("disabled") === null ) && - ( !option.parentNode.disabled || !jQuery.nodeName( option.parentNode, "optgroup" ) ) ) { - - // Get the specific value for the option - value = jQuery( option ).val(); - - // We don't need an array for one selects - if ( one ) { - return value; - } - - // Multi-Selects return an array - values.push( value ); - } - } - - return values; - }, - - set: function( elem, value ) { - var optionSet, option, - options = elem.options, - values = jQuery.makeArray( value ), - i = options.length; - - while ( i-- ) { - option = options[ i ]; - if ( (option.selected = jQuery.inArray( jQuery(option).val(), values ) >= 0) ) { - optionSet = true; - } - } - - // force browsers to behave consistently when non-matching value is set - if ( !optionSet ) { - elem.selectedIndex = -1; - } - return values; - } - } - }, - - attr: function( elem, name, value ) { - var hooks, ret, - nType = elem.nodeType; - - // don't get/set attributes on text, comment and attribute nodes - if ( !elem || nType === 3 || nType === 8 || nType === 2 ) { - return; - } - - // Fallback to prop when attributes are not supported - if ( typeof elem.getAttribute === core_strundefined ) { - return jQuery.prop( elem, name, value ); - } - - // All attributes are lowercase - // Grab necessary hook if one is defined - if ( nType !== 1 || !jQuery.isXMLDoc( elem ) ) { - name = name.toLowerCase(); - hooks = jQuery.attrHooks[ name ] || - ( jQuery.expr.match.bool.test( name ) ? boolHook : nodeHook ); - } - - if ( value !== undefined ) { - - if ( value === null ) { - jQuery.removeAttr( elem, name ); - - } else if ( hooks && "set" in hooks && (ret = hooks.set( elem, value, name )) !== undefined ) { - return ret; - - } else { - elem.setAttribute( name, value + "" ); - return value; - } - - } else if ( hooks && "get" in hooks && (ret = hooks.get( elem, name )) !== null ) { - return ret; - - } else { - ret = jQuery.find.attr( elem, name ); - - // Non-existent attributes return null, we normalize to undefined - return ret == null ? - undefined : - ret; - } - }, - - removeAttr: function( elem, value ) { - var name, propName, - i = 0, - attrNames = value && value.match( core_rnotwhite ); - - if ( attrNames && elem.nodeType === 1 ) { - while ( (name = attrNames[i++]) ) { - propName = jQuery.propFix[ name ] || name; - - // Boolean attributes get special treatment (#10870) - if ( jQuery.expr.match.bool.test( name ) ) { - // Set corresponding property to false - if ( getSetInput && getSetAttribute || !ruseDefault.test( name ) ) { - elem[ propName ] = false; - // Support: IE<9 - // Also clear defaultChecked/defaultSelected (if appropriate) - } else { - elem[ jQuery.camelCase( "default-" + name ) ] = - elem[ propName ] = false; - } - - // See #9699 for explanation of this approach (setting first, then removal) - } else { - jQuery.attr( elem, name, "" ); - } - - elem.removeAttribute( getSetAttribute ? name : propName ); - } - } - }, - - attrHooks: { - type: { - set: function( elem, value ) { - if ( !jQuery.support.radioValue && value === "radio" && jQuery.nodeName(elem, "input") ) { - // Setting the type on a radio button after the value resets the value in IE6-9 - // Reset value to default in case type is set after value during creation - var val = elem.value; - elem.setAttribute( "type", value ); - if ( val ) { - elem.value = val; - } - return value; - } - } - } - }, - - propFix: { - "for": "htmlFor", - "class": "className" - }, - - prop: function( elem, name, value ) { - var ret, hooks, notxml, - nType = elem.nodeType; - - // don't get/set properties on text, comment and attribute nodes - if ( !elem || nType === 3 || nType === 8 || nType === 2 ) { - return; - } - - notxml = nType !== 1 || !jQuery.isXMLDoc( elem ); - - if ( notxml ) { - // Fix name and attach hooks - name = jQuery.propFix[ name ] || name; - hooks = jQuery.propHooks[ name ]; - } - - if ( value !== undefined ) { - return hooks && "set" in hooks && (ret = hooks.set( elem, value, name )) !== undefined ? - ret : - ( elem[ name ] = value ); - - } else { - return hooks && "get" in hooks && (ret = hooks.get( elem, name )) !== null ? - ret : - elem[ name ]; - } - }, - - propHooks: { - tabIndex: { - get: function( elem ) { - // elem.tabIndex doesn't always return the correct value when it hasn't been explicitly set - // http://fluidproject.org/blog/2008/01/09/getting-setting-and-removing-tabindex-values-with-javascript/ - // Use proper attribute retrieval(#12072) - var tabindex = jQuery.find.attr( elem, "tabindex" ); - - return tabindex ? - parseInt( tabindex, 10 ) : - rfocusable.test( elem.nodeName ) || rclickable.test( elem.nodeName ) && elem.href ? - 0 : - -1; - } - } - } -}); - -// Hooks for boolean attributes -boolHook = { - set: function( elem, value, name ) { - if ( value === false ) { - // Remove boolean attributes when set to false - jQuery.removeAttr( elem, name ); - } else if ( getSetInput && getSetAttribute || !ruseDefault.test( name ) ) { - // IE<8 needs the *property* name - elem.setAttribute( !getSetAttribute && jQuery.propFix[ name ] || name, name ); - - // Use defaultChecked and defaultSelected for oldIE - } else { - elem[ jQuery.camelCase( "default-" + name ) ] = elem[ name ] = true; - } - - return name; - } -}; -jQuery.each( jQuery.expr.match.bool.source.match( /\w+/g ), function( i, name ) { - var getter = jQuery.expr.attrHandle[ name ] || jQuery.find.attr; - - jQuery.expr.attrHandle[ name ] = getSetInput && getSetAttribute || !ruseDefault.test( name ) ? - function( elem, name, isXML ) { - var fn = jQuery.expr.attrHandle[ name ], - ret = isXML ? - undefined : - /* jshint eqeqeq: false */ - (jQuery.expr.attrHandle[ name ] = undefined) != - getter( elem, name, isXML ) ? - - name.toLowerCase() : - null; - jQuery.expr.attrHandle[ name ] = fn; - return ret; - } : - function( elem, name, isXML ) { - return isXML ? - undefined : - elem[ jQuery.camelCase( "default-" + name ) ] ? - name.toLowerCase() : - null; - }; -}); - -// fix oldIE attroperties -if ( !getSetInput || !getSetAttribute ) { - jQuery.attrHooks.value = { - set: function( elem, value, name ) { - if ( jQuery.nodeName( elem, "input" ) ) { - // Does not return so that setAttribute is also used - elem.defaultValue = value; - } else { - // Use nodeHook if defined (#1954); otherwise setAttribute is fine - return nodeHook && nodeHook.set( elem, value, name ); - } - } - }; -} - -// IE6/7 do not support getting/setting some attributes with get/setAttribute -if ( !getSetAttribute ) { - - // Use this for any attribute in IE6/7 - // This fixes almost every IE6/7 issue - nodeHook = { - set: function( elem, value, name ) { - // Set the existing or create a new attribute node - var ret = elem.getAttributeNode( name ); - if ( !ret ) { - elem.setAttributeNode( - (ret = elem.ownerDocument.createAttribute( name )) - ); - } - - ret.value = value += ""; - - // Break association with cloned elements by also using setAttribute (#9646) - return name === "value" || value === elem.getAttribute( name ) ? - value : - undefined; - } - }; - jQuery.expr.attrHandle.id = jQuery.expr.attrHandle.name = jQuery.expr.attrHandle.coords = - // Some attributes are constructed with empty-string values when not defined - function( elem, name, isXML ) { - var ret; - return isXML ? - undefined : - (ret = elem.getAttributeNode( name )) && ret.value !== "" ? - ret.value : - null; - }; - jQuery.valHooks.button = { - get: function( elem, name ) { - var ret = elem.getAttributeNode( name ); - return ret && ret.specified ? - ret.value : - undefined; - }, - set: nodeHook.set - }; - - // Set contenteditable to false on removals(#10429) - // Setting to empty string throws an error as an invalid value - jQuery.attrHooks.contenteditable = { - set: function( elem, value, name ) { - nodeHook.set( elem, value === "" ? false : value, name ); - } - }; - - // Set width and height to auto instead of 0 on empty string( Bug #8150 ) - // This is for removals - jQuery.each([ "width", "height" ], function( i, name ) { - jQuery.attrHooks[ name ] = { - set: function( elem, value ) { - if ( value === "" ) { - elem.setAttribute( name, "auto" ); - return value; - } - } - }; - }); -} - - -// Some attributes require a special call on IE -// http://msdn.microsoft.com/en-us/library/ms536429%28VS.85%29.aspx -if ( !jQuery.support.hrefNormalized ) { - // href/src property should get the full normalized URL (#10299/#12915) - jQuery.each([ "href", "src" ], function( i, name ) { - jQuery.propHooks[ name ] = { - get: function( elem ) { - return elem.getAttribute( name, 4 ); - } - }; - }); -} - -if ( !jQuery.support.style ) { - jQuery.attrHooks.style = { - get: function( elem ) { - // Return undefined in the case of empty string - // Note: IE uppercases css property names, but if we were to .toLowerCase() - // .cssText, that would destroy case senstitivity in URL's, like in "background" - return elem.style.cssText || undefined; - }, - set: function( elem, value ) { - return ( elem.style.cssText = value + "" ); - } - }; -} - -// Safari mis-reports the default selected property of an option -// Accessing the parent's selectedIndex property fixes it -if ( !jQuery.support.optSelected ) { - jQuery.propHooks.selected = { - get: function( elem ) { - var parent = elem.parentNode; - - if ( parent ) { - parent.selectedIndex; - - // Make sure that it also works with optgroups, see #5701 - if ( parent.parentNode ) { - parent.parentNode.selectedIndex; - } - } - return null; - } - }; -} - -jQuery.each([ - "tabIndex", - "readOnly", - "maxLength", - "cellSpacing", - "cellPadding", - "rowSpan", - "colSpan", - "useMap", - "frameBorder", - "contentEditable" -], function() { - jQuery.propFix[ this.toLowerCase() ] = this; -}); - -// IE6/7 call enctype encoding -if ( !jQuery.support.enctype ) { - jQuery.propFix.enctype = "encoding"; -} - -// Radios and checkboxes getter/setter -jQuery.each([ "radio", "checkbox" ], function() { - jQuery.valHooks[ this ] = { - set: function( elem, value ) { - if ( jQuery.isArray( value ) ) { - return ( elem.checked = jQuery.inArray( jQuery(elem).val(), value ) >= 0 ); - } - } - }; - if ( !jQuery.support.checkOn ) { - jQuery.valHooks[ this ].get = function( elem ) { - // Support: Webkit - // "" is returned instead of "on" if a value isn't specified - return elem.getAttribute("value") === null ? "on" : elem.value; - }; - } -}); -var rformElems = /^(?:input|select|textarea)$/i, - rkeyEvent = /^key/, - rmouseEvent = /^(?:mouse|contextmenu)|click/, - rfocusMorph = /^(?:focusinfocus|focusoutblur)$/, - rtypenamespace = /^([^.]*)(?:\.(.+)|)$/; - -function returnTrue() { - return true; -} - -function returnFalse() { - return false; -} - -function safeActiveElement() { - try { - return document.activeElement; - } catch ( err ) { } -} - -/* - * Helper functions for managing events -- not part of the public interface. - * Props to Dean Edwards' addEvent library for many of the ideas. - */ -jQuery.event = { - - global: {}, - - add: function( elem, types, handler, data, selector ) { - var tmp, events, t, handleObjIn, - special, eventHandle, handleObj, - handlers, type, namespaces, origType, - elemData = jQuery._data( elem ); - - // Don't attach events to noData or text/comment nodes (but allow plain objects) - if ( !elemData ) { - return; - } - - // Caller can pass in an object of custom data in lieu of the handler - if ( handler.handler ) { - handleObjIn = handler; - handler = handleObjIn.handler; - selector = handleObjIn.selector; - } - - // Make sure that the handler has a unique ID, used to find/remove it later - if ( !handler.guid ) { - handler.guid = jQuery.guid++; - } - - // Init the element's event structure and main handler, if this is the first - if ( !(events = elemData.events) ) { - events = elemData.events = {}; - } - if ( !(eventHandle = elemData.handle) ) { - eventHandle = elemData.handle = function( e ) { - // Discard the second event of a jQuery.event.trigger() and - // when an event is called after a page has unloaded - return typeof jQuery !== core_strundefined && (!e || jQuery.event.triggered !== e.type) ? - jQuery.event.dispatch.apply( eventHandle.elem, arguments ) : - undefined; - }; - // Add elem as a property of the handle fn to prevent a memory leak with IE non-native events - eventHandle.elem = elem; - } - - // Handle multiple events separated by a space - types = ( types || "" ).match( core_rnotwhite ) || [""]; - t = types.length; - while ( t-- ) { - tmp = rtypenamespace.exec( types[t] ) || []; - type = origType = tmp[1]; - namespaces = ( tmp[2] || "" ).split( "." ).sort(); - - // There *must* be a type, no attaching namespace-only handlers - if ( !type ) { - continue; - } - - // If event changes its type, use the special event handlers for the changed type - special = jQuery.event.special[ type ] || {}; - - // If selector defined, determine special event api type, otherwise given type - type = ( selector ? special.delegateType : special.bindType ) || type; - - // Update special based on newly reset type - special = jQuery.event.special[ type ] || {}; - - // handleObj is passed to all event handlers - handleObj = jQuery.extend({ - type: type, - origType: origType, - data: data, - handler: handler, - guid: handler.guid, - selector: selector, - needsContext: selector && jQuery.expr.match.needsContext.test( selector ), - namespace: namespaces.join(".") - }, handleObjIn ); - - // Init the event handler queue if we're the first - if ( !(handlers = events[ type ]) ) { - handlers = events[ type ] = []; - handlers.delegateCount = 0; - - // Only use addEventListener/attachEvent if the special events handler returns false - if ( !special.setup || special.setup.call( elem, data, namespaces, eventHandle ) === false ) { - // Bind the global event handler to the element - if ( elem.addEventListener ) { - elem.addEventListener( type, eventHandle, false ); - - } else if ( elem.attachEvent ) { - elem.attachEvent( "on" + type, eventHandle ); - } - } - } - - if ( special.add ) { - special.add.call( elem, handleObj ); - - if ( !handleObj.handler.guid ) { - handleObj.handler.guid = handler.guid; - } - } - - // Add to the element's handler list, delegates in front - if ( selector ) { - handlers.splice( handlers.delegateCount++, 0, handleObj ); - } else { - handlers.push( handleObj ); - } - - // Keep track of which events have ever been used, for event optimization - jQuery.event.global[ type ] = true; - } - - // Nullify elem to prevent memory leaks in IE - elem = null; - }, - - // Detach an event or set of events from an element - remove: function( elem, types, handler, selector, mappedTypes ) { - var j, handleObj, tmp, - origCount, t, events, - special, handlers, type, - namespaces, origType, - elemData = jQuery.hasData( elem ) && jQuery._data( elem ); - - if ( !elemData || !(events = elemData.events) ) { - return; - } - - // Once for each type.namespace in types; type may be omitted - types = ( types || "" ).match( core_rnotwhite ) || [""]; - t = types.length; - while ( t-- ) { - tmp = rtypenamespace.exec( types[t] ) || []; - type = origType = tmp[1]; - namespaces = ( tmp[2] || "" ).split( "." ).sort(); - - // Unbind all events (on this namespace, if provided) for the element - if ( !type ) { - for ( type in events ) { - jQuery.event.remove( elem, type + types[ t ], handler, selector, true ); - } - continue; - } - - special = jQuery.event.special[ type ] || {}; - type = ( selector ? special.delegateType : special.bindType ) || type; - handlers = events[ type ] || []; - tmp = tmp[2] && new RegExp( "(^|\\.)" + namespaces.join("\\.(?:.*\\.|)") + "(\\.|$)" ); - - // Remove matching events - origCount = j = handlers.length; - while ( j-- ) { - handleObj = handlers[ j ]; - - if ( ( mappedTypes || origType === handleObj.origType ) && - ( !handler || handler.guid === handleObj.guid ) && - ( !tmp || tmp.test( handleObj.namespace ) ) && - ( !selector || selector === handleObj.selector || selector === "**" && handleObj.selector ) ) { - handlers.splice( j, 1 ); - - if ( handleObj.selector ) { - handlers.delegateCount--; - } - if ( special.remove ) { - special.remove.call( elem, handleObj ); - } - } - } - - // Remove generic event handler if we removed something and no more handlers exist - // (avoids potential for endless recursion during removal of special event handlers) - if ( origCount && !handlers.length ) { - if ( !special.teardown || special.teardown.call( elem, namespaces, elemData.handle ) === false ) { - jQuery.removeEvent( elem, type, elemData.handle ); - } - - delete events[ type ]; - } - } - - // Remove the expando if it's no longer used - if ( jQuery.isEmptyObject( events ) ) { - delete elemData.handle; - - // removeData also checks for emptiness and clears the expando if empty - // so use it instead of delete - jQuery._removeData( elem, "events" ); - } - }, - - trigger: function( event, data, elem, onlyHandlers ) { - var handle, ontype, cur, - bubbleType, special, tmp, i, - eventPath = [ elem || document ], - type = core_hasOwn.call( event, "type" ) ? event.type : event, - namespaces = core_hasOwn.call( event, "namespace" ) ? event.namespace.split(".") : []; - - cur = tmp = elem = elem || document; - - // Don't do events on text and comment nodes - if ( elem.nodeType === 3 || elem.nodeType === 8 ) { - return; - } - - // focus/blur morphs to focusin/out; ensure we're not firing them right now - if ( rfocusMorph.test( type + jQuery.event.triggered ) ) { - return; - } - - if ( type.indexOf(".") >= 0 ) { - // Namespaced trigger; create a regexp to match event type in handle() - namespaces = type.split("."); - type = namespaces.shift(); - namespaces.sort(); - } - ontype = type.indexOf(":") < 0 && "on" + type; - - // Caller can pass in a jQuery.Event object, Object, or just an event type string - event = event[ jQuery.expando ] ? - event : - new jQuery.Event( type, typeof event === "object" && event ); - - // Trigger bitmask: & 1 for native handlers; & 2 for jQuery (always true) - event.isTrigger = onlyHandlers ? 2 : 3; - event.namespace = namespaces.join("."); - event.namespace_re = event.namespace ? - new RegExp( "(^|\\.)" + namespaces.join("\\.(?:.*\\.|)") + "(\\.|$)" ) : - null; - - // Clean up the event in case it is being reused - event.result = undefined; - if ( !event.target ) { - event.target = elem; - } - - // Clone any incoming data and prepend the event, creating the handler arg list - data = data == null ? - [ event ] : - jQuery.makeArray( data, [ event ] ); - - // Allow special events to draw outside the lines - special = jQuery.event.special[ type ] || {}; - if ( !onlyHandlers && special.trigger && special.trigger.apply( elem, data ) === false ) { - return; - } - - // Determine event propagation path in advance, per W3C events spec (#9951) - // Bubble up to document, then to window; watch for a global ownerDocument var (#9724) - if ( !onlyHandlers && !special.noBubble && !jQuery.isWindow( elem ) ) { - - bubbleType = special.delegateType || type; - if ( !rfocusMorph.test( bubbleType + type ) ) { - cur = cur.parentNode; - } - for ( ; cur; cur = cur.parentNode ) { - eventPath.push( cur ); - tmp = cur; - } - - // Only add window if we got to document (e.g., not plain obj or detached DOM) - if ( tmp === (elem.ownerDocument || document) ) { - eventPath.push( tmp.defaultView || tmp.parentWindow || window ); - } - } - - // Fire handlers on the event path - i = 0; - while ( (cur = eventPath[i++]) && !event.isPropagationStopped() ) { - - event.type = i > 1 ? - bubbleType : - special.bindType || type; - - // jQuery handler - handle = ( jQuery._data( cur, "events" ) || {} )[ event.type ] && jQuery._data( cur, "handle" ); - if ( handle ) { - handle.apply( cur, data ); - } - - // Native handler - handle = ontype && cur[ ontype ]; - if ( handle && jQuery.acceptData( cur ) && handle.apply && handle.apply( cur, data ) === false ) { - event.preventDefault(); - } - } - event.type = type; - - // If nobody prevented the default action, do it now - if ( !onlyHandlers && !event.isDefaultPrevented() ) { - - if ( (!special._default || special._default.apply( eventPath.pop(), data ) === false) && - jQuery.acceptData( elem ) ) { - - // Call a native DOM method on the target with the same name name as the event. - // Can't use an .isFunction() check here because IE6/7 fails that test. - // Don't do default actions on window, that's where global variables be (#6170) - if ( ontype && elem[ type ] && !jQuery.isWindow( elem ) ) { - - // Don't re-trigger an onFOO event when we call its FOO() method - tmp = elem[ ontype ]; - - if ( tmp ) { - elem[ ontype ] = null; - } - - // Prevent re-triggering of the same event, since we already bubbled it above - jQuery.event.triggered = type; - try { - elem[ type ](); - } catch ( e ) { - // IE<9 dies on focus/blur to hidden element (#1486,#12518) - // only reproducible on winXP IE8 native, not IE9 in IE8 mode - } - jQuery.event.triggered = undefined; - - if ( tmp ) { - elem[ ontype ] = tmp; - } - } - } - } - - return event.result; - }, - - dispatch: function( event ) { - - // Make a writable jQuery.Event from the native event object - event = jQuery.event.fix( event ); - - var i, ret, handleObj, matched, j, - handlerQueue = [], - args = core_slice.call( arguments ), - handlers = ( jQuery._data( this, "events" ) || {} )[ event.type ] || [], - special = jQuery.event.special[ event.type ] || {}; - - // Use the fix-ed jQuery.Event rather than the (read-only) native event - args[0] = event; - event.delegateTarget = this; - - // Call the preDispatch hook for the mapped type, and let it bail if desired - if ( special.preDispatch && special.preDispatch.call( this, event ) === false ) { - return; - } - - // Determine handlers - handlerQueue = jQuery.event.handlers.call( this, event, handlers ); - - // Run delegates first; they may want to stop propagation beneath us - i = 0; - while ( (matched = handlerQueue[ i++ ]) && !event.isPropagationStopped() ) { - event.currentTarget = matched.elem; - - j = 0; - while ( (handleObj = matched.handlers[ j++ ]) && !event.isImmediatePropagationStopped() ) { - - // Triggered event must either 1) have no namespace, or - // 2) have namespace(s) a subset or equal to those in the bound event (both can have no namespace). - if ( !event.namespace_re || event.namespace_re.test( handleObj.namespace ) ) { - - event.handleObj = handleObj; - event.data = handleObj.data; - - ret = ( (jQuery.event.special[ handleObj.origType ] || {}).handle || handleObj.handler ) - .apply( matched.elem, args ); - - if ( ret !== undefined ) { - if ( (event.result = ret) === false ) { - event.preventDefault(); - event.stopPropagation(); - } - } - } - } - } - - // Call the postDispatch hook for the mapped type - if ( special.postDispatch ) { - special.postDispatch.call( this, event ); - } - - return event.result; - }, - - handlers: function( event, handlers ) { - var sel, handleObj, matches, i, - handlerQueue = [], - delegateCount = handlers.delegateCount, - cur = event.target; - - // Find delegate handlers - // Black-hole SVG instance trees (#13180) - // Avoid non-left-click bubbling in Firefox (#3861) - if ( delegateCount && cur.nodeType && (!event.button || event.type !== "click") ) { - - /* jshint eqeqeq: false */ - for ( ; cur != this; cur = cur.parentNode || this ) { - /* jshint eqeqeq: true */ - - // Don't check non-elements (#13208) - // Don't process clicks on disabled elements (#6911, #8165, #11382, #11764) - if ( cur.nodeType === 1 && (cur.disabled !== true || event.type !== "click") ) { - matches = []; - for ( i = 0; i < delegateCount; i++ ) { - handleObj = handlers[ i ]; - - // Don't conflict with Object.prototype properties (#13203) - sel = handleObj.selector + " "; - - if ( matches[ sel ] === undefined ) { - matches[ sel ] = handleObj.needsContext ? - jQuery( sel, this ).index( cur ) >= 0 : - jQuery.find( sel, this, null, [ cur ] ).length; - } - if ( matches[ sel ] ) { - matches.push( handleObj ); - } - } - if ( matches.length ) { - handlerQueue.push({ elem: cur, handlers: matches }); - } - } - } - } - - // Add the remaining (directly-bound) handlers - if ( delegateCount < handlers.length ) { - handlerQueue.push({ elem: this, handlers: handlers.slice( delegateCount ) }); - } - - return handlerQueue; - }, - - fix: function( event ) { - if ( event[ jQuery.expando ] ) { - return event; - } - - // Create a writable copy of the event object and normalize some properties - var i, prop, copy, - type = event.type, - originalEvent = event, - fixHook = this.fixHooks[ type ]; - - if ( !fixHook ) { - this.fixHooks[ type ] = fixHook = - rmouseEvent.test( type ) ? this.mouseHooks : - rkeyEvent.test( type ) ? this.keyHooks : - {}; - } - copy = fixHook.props ? this.props.concat( fixHook.props ) : this.props; - - event = new jQuery.Event( originalEvent ); - - i = copy.length; - while ( i-- ) { - prop = copy[ i ]; - event[ prop ] = originalEvent[ prop ]; - } - - // Support: IE<9 - // Fix target property (#1925) - if ( !event.target ) { - event.target = originalEvent.srcElement || document; - } - - // Support: Chrome 23+, Safari? - // Target should not be a text node (#504, #13143) - if ( event.target.nodeType === 3 ) { - event.target = event.target.parentNode; - } - - // Support: IE<9 - // For mouse/key events, metaKey==false if it's undefined (#3368, #11328) - event.metaKey = !!event.metaKey; - - return fixHook.filter ? fixHook.filter( event, originalEvent ) : event; - }, - - // Includes some event props shared by KeyEvent and MouseEvent - props: "altKey bubbles cancelable ctrlKey currentTarget eventPhase metaKey relatedTarget shiftKey target timeStamp view which".split(" "), - - fixHooks: {}, - - keyHooks: { - props: "char charCode key keyCode".split(" "), - filter: function( event, original ) { - - // Add which for key events - if ( event.which == null ) { - event.which = original.charCode != null ? original.charCode : original.keyCode; - } - - return event; - } - }, - - mouseHooks: { - props: "button buttons clientX clientY fromElement offsetX offsetY pageX pageY screenX screenY toElement".split(" "), - filter: function( event, original ) { - var body, eventDoc, doc, - button = original.button, - fromElement = original.fromElement; - - // Calculate pageX/Y if missing and clientX/Y available - if ( event.pageX == null && original.clientX != null ) { - eventDoc = event.target.ownerDocument || document; - doc = eventDoc.documentElement; - body = eventDoc.body; - - event.pageX = original.clientX + ( doc && doc.scrollLeft || body && body.scrollLeft || 0 ) - ( doc && doc.clientLeft || body && body.clientLeft || 0 ); - event.pageY = original.clientY + ( doc && doc.scrollTop || body && body.scrollTop || 0 ) - ( doc && doc.clientTop || body && body.clientTop || 0 ); - } - - // Add relatedTarget, if necessary - if ( !event.relatedTarget && fromElement ) { - event.relatedTarget = fromElement === event.target ? original.toElement : fromElement; - } - - // Add which for click: 1 === left; 2 === middle; 3 === right - // Note: button is not normalized, so don't use it - if ( !event.which && button !== undefined ) { - event.which = ( button & 1 ? 1 : ( button & 2 ? 3 : ( button & 4 ? 2 : 0 ) ) ); - } - - return event; - } - }, - - special: { - load: { - // Prevent triggered image.load events from bubbling to window.load - noBubble: true - }, - focus: { - // Fire native event if possible so blur/focus sequence is correct - trigger: function() { - if ( this !== safeActiveElement() && this.focus ) { - try { - this.focus(); - return false; - } catch ( e ) { - // Support: IE<9 - // If we error on focus to hidden element (#1486, #12518), - // let .trigger() run the handlers - } - } - }, - delegateType: "focusin" - }, - blur: { - trigger: function() { - if ( this === safeActiveElement() && this.blur ) { - this.blur(); - return false; - } - }, - delegateType: "focusout" - }, - click: { - // For checkbox, fire native event so checked state will be right - trigger: function() { - if ( jQuery.nodeName( this, "input" ) && this.type === "checkbox" && this.click ) { - this.click(); - return false; - } - }, - - // For cross-browser consistency, don't fire native .click() on links - _default: function( event ) { - return jQuery.nodeName( event.target, "a" ); - } - }, - - beforeunload: { - postDispatch: function( event ) { - - // Even when returnValue equals to undefined Firefox will still show alert - if ( event.result !== undefined ) { - event.originalEvent.returnValue = event.result; - } - } - } - }, - - simulate: function( type, elem, event, bubble ) { - // Piggyback on a donor event to simulate a different one. - // Fake originalEvent to avoid donor's stopPropagation, but if the - // simulated event prevents default then we do the same on the donor. - var e = jQuery.extend( - new jQuery.Event(), - event, - { - type: type, - isSimulated: true, - originalEvent: {} - } - ); - if ( bubble ) { - jQuery.event.trigger( e, null, elem ); - } else { - jQuery.event.dispatch.call( elem, e ); - } - if ( e.isDefaultPrevented() ) { - event.preventDefault(); - } - } -}; - -jQuery.removeEvent = document.removeEventListener ? - function( elem, type, handle ) { - if ( elem.removeEventListener ) { - elem.removeEventListener( type, handle, false ); - } - } : - function( elem, type, handle ) { - var name = "on" + type; - - if ( elem.detachEvent ) { - - // #8545, #7054, preventing memory leaks for custom events in IE6-8 - // detachEvent needed property on element, by name of that event, to properly expose it to GC - if ( typeof elem[ name ] === core_strundefined ) { - elem[ name ] = null; - } - - elem.detachEvent( name, handle ); - } - }; - -jQuery.Event = function( src, props ) { - // Allow instantiation without the 'new' keyword - if ( !(this instanceof jQuery.Event) ) { - return new jQuery.Event( src, props ); - } - - // Event object - if ( src && src.type ) { - this.originalEvent = src; - this.type = src.type; - - // Events bubbling up the document may have been marked as prevented - // by a handler lower down the tree; reflect the correct value. - this.isDefaultPrevented = ( src.defaultPrevented || src.returnValue === false || - src.getPreventDefault && src.getPreventDefault() ) ? returnTrue : returnFalse; - - // Event type - } else { - this.type = src; - } - - // Put explicitly provided properties onto the event object - if ( props ) { - jQuery.extend( this, props ); - } - - // Create a timestamp if incoming event doesn't have one - this.timeStamp = src && src.timeStamp || jQuery.now(); - - // Mark it as fixed - this[ jQuery.expando ] = true; -}; - -// jQuery.Event is based on DOM3 Events as specified by the ECMAScript Language Binding -// http://www.w3.org/TR/2003/WD-DOM-Level-3-Events-20030331/ecma-script-binding.html -jQuery.Event.prototype = { - isDefaultPrevented: returnFalse, - isPropagationStopped: returnFalse, - isImmediatePropagationStopped: returnFalse, - - preventDefault: function() { - var e = this.originalEvent; - - this.isDefaultPrevented = returnTrue; - if ( !e ) { - return; - } - - // If preventDefault exists, run it on the original event - if ( e.preventDefault ) { - e.preventDefault(); - - // Support: IE - // Otherwise set the returnValue property of the original event to false - } else { - e.returnValue = false; - } - }, - stopPropagation: function() { - var e = this.originalEvent; - - this.isPropagationStopped = returnTrue; - if ( !e ) { - return; - } - // If stopPropagation exists, run it on the original event - if ( e.stopPropagation ) { - e.stopPropagation(); - } - - // Support: IE - // Set the cancelBubble property of the original event to true - e.cancelBubble = true; - }, - stopImmediatePropagation: function() { - this.isImmediatePropagationStopped = returnTrue; - this.stopPropagation(); - } -}; - -// Create mouseenter/leave events using mouseover/out and event-time checks -jQuery.each({ - mouseenter: "mouseover", - mouseleave: "mouseout" -}, function( orig, fix ) { - jQuery.event.special[ orig ] = { - delegateType: fix, - bindType: fix, - - handle: function( event ) { - var ret, - target = this, - related = event.relatedTarget, - handleObj = event.handleObj; - - // For mousenter/leave call the handler if related is outside the target. - // NB: No relatedTarget if the mouse left/entered the browser window - if ( !related || (related !== target && !jQuery.contains( target, related )) ) { - event.type = handleObj.origType; - ret = handleObj.handler.apply( this, arguments ); - event.type = fix; - } - return ret; - } - }; -}); - -// IE submit delegation -if ( !jQuery.support.submitBubbles ) { - - jQuery.event.special.submit = { - setup: function() { - // Only need this for delegated form submit events - if ( jQuery.nodeName( this, "form" ) ) { - return false; - } - - // Lazy-add a submit handler when a descendant form may potentially be submitted - jQuery.event.add( this, "click._submit keypress._submit", function( e ) { - // Node name check avoids a VML-related crash in IE (#9807) - var elem = e.target, - form = jQuery.nodeName( elem, "input" ) || jQuery.nodeName( elem, "button" ) ? elem.form : undefined; - if ( form && !jQuery._data( form, "submitBubbles" ) ) { - jQuery.event.add( form, "submit._submit", function( event ) { - event._submit_bubble = true; - }); - jQuery._data( form, "submitBubbles", true ); - } - }); - // return undefined since we don't need an event listener - }, - - postDispatch: function( event ) { - // If form was submitted by the user, bubble the event up the tree - if ( event._submit_bubble ) { - delete event._submit_bubble; - if ( this.parentNode && !event.isTrigger ) { - jQuery.event.simulate( "submit", this.parentNode, event, true ); - } - } - }, - - teardown: function() { - // Only need this for delegated form submit events - if ( jQuery.nodeName( this, "form" ) ) { - return false; - } - - // Remove delegated handlers; cleanData eventually reaps submit handlers attached above - jQuery.event.remove( this, "._submit" ); - } - }; -} - -// IE change delegation and checkbox/radio fix -if ( !jQuery.support.changeBubbles ) { - - jQuery.event.special.change = { - - setup: function() { - - if ( rformElems.test( this.nodeName ) ) { - // IE doesn't fire change on a check/radio until blur; trigger it on click - // after a propertychange. Eat the blur-change in special.change.handle. - // This still fires onchange a second time for check/radio after blur. - if ( this.type === "checkbox" || this.type === "radio" ) { - jQuery.event.add( this, "propertychange._change", function( event ) { - if ( event.originalEvent.propertyName === "checked" ) { - this._just_changed = true; - } - }); - jQuery.event.add( this, "click._change", function( event ) { - if ( this._just_changed && !event.isTrigger ) { - this._just_changed = false; - } - // Allow triggered, simulated change events (#11500) - jQuery.event.simulate( "change", this, event, true ); - }); - } - return false; - } - // Delegated event; lazy-add a change handler on descendant inputs - jQuery.event.add( this, "beforeactivate._change", function( e ) { - var elem = e.target; - - if ( rformElems.test( elem.nodeName ) && !jQuery._data( elem, "changeBubbles" ) ) { - jQuery.event.add( elem, "change._change", function( event ) { - if ( this.parentNode && !event.isSimulated && !event.isTrigger ) { - jQuery.event.simulate( "change", this.parentNode, event, true ); - } - }); - jQuery._data( elem, "changeBubbles", true ); - } - }); - }, - - handle: function( event ) { - var elem = event.target; - - // Swallow native change events from checkbox/radio, we already triggered them above - if ( this !== elem || event.isSimulated || event.isTrigger || (elem.type !== "radio" && elem.type !== "checkbox") ) { - return event.handleObj.handler.apply( this, arguments ); - } - }, - - teardown: function() { - jQuery.event.remove( this, "._change" ); - - return !rformElems.test( this.nodeName ); - } - }; -} - -// Create "bubbling" focus and blur events -if ( !jQuery.support.focusinBubbles ) { - jQuery.each({ focus: "focusin", blur: "focusout" }, function( orig, fix ) { - - // Attach a single capturing handler while someone wants focusin/focusout - var attaches = 0, - handler = function( event ) { - jQuery.event.simulate( fix, event.target, jQuery.event.fix( event ), true ); - }; - - jQuery.event.special[ fix ] = { - setup: function() { - if ( attaches++ === 0 ) { - document.addEventListener( orig, handler, true ); - } - }, - teardown: function() { - if ( --attaches === 0 ) { - document.removeEventListener( orig, handler, true ); - } - } - }; - }); -} - -jQuery.fn.extend({ - - on: function( types, selector, data, fn, /*INTERNAL*/ one ) { - var type, origFn; - - // Types can be a map of types/handlers - if ( typeof types === "object" ) { - // ( types-Object, selector, data ) - if ( typeof selector !== "string" ) { - // ( types-Object, data ) - data = data || selector; - selector = undefined; - } - for ( type in types ) { - this.on( type, selector, data, types[ type ], one ); - } - return this; - } - - if ( data == null && fn == null ) { - // ( types, fn ) - fn = selector; - data = selector = undefined; - } else if ( fn == null ) { - if ( typeof selector === "string" ) { - // ( types, selector, fn ) - fn = data; - data = undefined; - } else { - // ( types, data, fn ) - fn = data; - data = selector; - selector = undefined; - } - } - if ( fn === false ) { - fn = returnFalse; - } else if ( !fn ) { - return this; - } - - if ( one === 1 ) { - origFn = fn; - fn = function( event ) { - // Can use an empty set, since event contains the info - jQuery().off( event ); - return origFn.apply( this, arguments ); - }; - // Use same guid so caller can remove using origFn - fn.guid = origFn.guid || ( origFn.guid = jQuery.guid++ ); - } - return this.each( function() { - jQuery.event.add( this, types, fn, data, selector ); - }); - }, - one: function( types, selector, data, fn ) { - return this.on( types, selector, data, fn, 1 ); - }, - off: function( types, selector, fn ) { - var handleObj, type; - if ( types && types.preventDefault && types.handleObj ) { - // ( event ) dispatched jQuery.Event - handleObj = types.handleObj; - jQuery( types.delegateTarget ).off( - handleObj.namespace ? handleObj.origType + "." + handleObj.namespace : handleObj.origType, - handleObj.selector, - handleObj.handler - ); - return this; - } - if ( typeof types === "object" ) { - // ( types-object [, selector] ) - for ( type in types ) { - this.off( type, selector, types[ type ] ); - } - return this; - } - if ( selector === false || typeof selector === "function" ) { - // ( types [, fn] ) - fn = selector; - selector = undefined; - } - if ( fn === false ) { - fn = returnFalse; - } - return this.each(function() { - jQuery.event.remove( this, types, fn, selector ); - }); - }, - - trigger: function( type, data ) { - return this.each(function() { - jQuery.event.trigger( type, data, this ); - }); - }, - triggerHandler: function( type, data ) { - var elem = this[0]; - if ( elem ) { - return jQuery.event.trigger( type, data, elem, true ); - } - } -}); -var isSimple = /^.[^:#\[\.,]*$/, - rparentsprev = /^(?:parents|prev(?:Until|All))/, - rneedsContext = jQuery.expr.match.needsContext, - // methods guaranteed to produce a unique set when starting from a unique set - guaranteedUnique = { - children: true, - contents: true, - next: true, - prev: true - }; - -jQuery.fn.extend({ - find: function( selector ) { - var i, - ret = [], - self = this, - len = self.length; - - if ( typeof selector !== "string" ) { - return this.pushStack( jQuery( selector ).filter(function() { - for ( i = 0; i < len; i++ ) { - if ( jQuery.contains( self[ i ], this ) ) { - return true; - } - } - }) ); - } - - for ( i = 0; i < len; i++ ) { - jQuery.find( selector, self[ i ], ret ); - } - - // Needed because $( selector, context ) becomes $( context ).find( selector ) - ret = this.pushStack( len > 1 ? jQuery.unique( ret ) : ret ); - ret.selector = this.selector ? this.selector + " " + selector : selector; - return ret; - }, - - has: function( target ) { - var i, - targets = jQuery( target, this ), - len = targets.length; - - return this.filter(function() { - for ( i = 0; i < len; i++ ) { - if ( jQuery.contains( this, targets[i] ) ) { - return true; - } - } - }); - }, - - not: function( selector ) { - return this.pushStack( winnow(this, selector || [], true) ); - }, - - filter: function( selector ) { - return this.pushStack( winnow(this, selector || [], false) ); - }, - - is: function( selector ) { - return !!winnow( - this, - - // If this is a positional/relative selector, check membership in the returned set - // so $("p:first").is("p:last") won't return true for a doc with two "p". - typeof selector === "string" && rneedsContext.test( selector ) ? - jQuery( selector ) : - selector || [], - false - ).length; - }, - - closest: function( selectors, context ) { - var cur, - i = 0, - l = this.length, - ret = [], - pos = rneedsContext.test( selectors ) || typeof selectors !== "string" ? - jQuery( selectors, context || this.context ) : - 0; - - for ( ; i < l; i++ ) { - for ( cur = this[i]; cur && cur !== context; cur = cur.parentNode ) { - // Always skip document fragments - if ( cur.nodeType < 11 && (pos ? - pos.index(cur) > -1 : - - // Don't pass non-elements to Sizzle - cur.nodeType === 1 && - jQuery.find.matchesSelector(cur, selectors)) ) { - - cur = ret.push( cur ); - break; - } - } - } - - return this.pushStack( ret.length > 1 ? jQuery.unique( ret ) : ret ); - }, - - // Determine the position of an element within - // the matched set of elements - index: function( elem ) { - - // No argument, return index in parent - if ( !elem ) { - return ( this[0] && this[0].parentNode ) ? this.first().prevAll().length : -1; - } - - // index in selector - if ( typeof elem === "string" ) { - return jQuery.inArray( this[0], jQuery( elem ) ); - } - - // Locate the position of the desired element - return jQuery.inArray( - // If it receives a jQuery object, the first element is used - elem.jquery ? elem[0] : elem, this ); - }, - - add: function( selector, context ) { - var set = typeof selector === "string" ? - jQuery( selector, context ) : - jQuery.makeArray( selector && selector.nodeType ? [ selector ] : selector ), - all = jQuery.merge( this.get(), set ); - - return this.pushStack( jQuery.unique(all) ); - }, - - addBack: function( selector ) { - return this.add( selector == null ? - this.prevObject : this.prevObject.filter(selector) - ); - } -}); - -function sibling( cur, dir ) { - do { - cur = cur[ dir ]; - } while ( cur && cur.nodeType !== 1 ); - - return cur; -} - -jQuery.each({ - parent: function( elem ) { - var parent = elem.parentNode; - return parent && parent.nodeType !== 11 ? parent : null; - }, - parents: function( elem ) { - return jQuery.dir( elem, "parentNode" ); - }, - parentsUntil: function( elem, i, until ) { - return jQuery.dir( elem, "parentNode", until ); - }, - next: function( elem ) { - return sibling( elem, "nextSibling" ); - }, - prev: function( elem ) { - return sibling( elem, "previousSibling" ); - }, - nextAll: function( elem ) { - return jQuery.dir( elem, "nextSibling" ); - }, - prevAll: function( elem ) { - return jQuery.dir( elem, "previousSibling" ); - }, - nextUntil: function( elem, i, until ) { - return jQuery.dir( elem, "nextSibling", until ); - }, - prevUntil: function( elem, i, until ) { - return jQuery.dir( elem, "previousSibling", until ); - }, - siblings: function( elem ) { - return jQuery.sibling( ( elem.parentNode || {} ).firstChild, elem ); - }, - children: function( elem ) { - return jQuery.sibling( elem.firstChild ); - }, - contents: function( elem ) { - return jQuery.nodeName( elem, "iframe" ) ? - elem.contentDocument || elem.contentWindow.document : - jQuery.merge( [], elem.childNodes ); - } -}, function( name, fn ) { - jQuery.fn[ name ] = function( until, selector ) { - var ret = jQuery.map( this, fn, until ); - - if ( name.slice( -5 ) !== "Until" ) { - selector = until; - } - - if ( selector && typeof selector === "string" ) { - ret = jQuery.filter( selector, ret ); - } - - if ( this.length > 1 ) { - // Remove duplicates - if ( !guaranteedUnique[ name ] ) { - ret = jQuery.unique( ret ); - } - - // Reverse order for parents* and prev-derivatives - if ( rparentsprev.test( name ) ) { - ret = ret.reverse(); - } - } - - return this.pushStack( ret ); - }; -}); - -jQuery.extend({ - filter: function( expr, elems, not ) { - var elem = elems[ 0 ]; - - if ( not ) { - expr = ":not(" + expr + ")"; - } - - return elems.length === 1 && elem.nodeType === 1 ? - jQuery.find.matchesSelector( elem, expr ) ? [ elem ] : [] : - jQuery.find.matches( expr, jQuery.grep( elems, function( elem ) { - return elem.nodeType === 1; - })); - }, - - dir: function( elem, dir, until ) { - var matched = [], - cur = elem[ dir ]; - - while ( cur && cur.nodeType !== 9 && (until === undefined || cur.nodeType !== 1 || !jQuery( cur ).is( until )) ) { - if ( cur.nodeType === 1 ) { - matched.push( cur ); - } - cur = cur[dir]; - } - return matched; - }, - - sibling: function( n, elem ) { - var r = []; - - for ( ; n; n = n.nextSibling ) { - if ( n.nodeType === 1 && n !== elem ) { - r.push( n ); - } - } - - return r; - } -}); - -// Implement the identical functionality for filter and not -function winnow( elements, qualifier, not ) { - if ( jQuery.isFunction( qualifier ) ) { - return jQuery.grep( elements, function( elem, i ) { - /* jshint -W018 */ - return !!qualifier.call( elem, i, elem ) !== not; - }); - - } - - if ( qualifier.nodeType ) { - return jQuery.grep( elements, function( elem ) { - return ( elem === qualifier ) !== not; - }); - - } - - if ( typeof qualifier === "string" ) { - if ( isSimple.test( qualifier ) ) { - return jQuery.filter( qualifier, elements, not ); - } - - qualifier = jQuery.filter( qualifier, elements ); - } - - return jQuery.grep( elements, function( elem ) { - return ( jQuery.inArray( elem, qualifier ) >= 0 ) !== not; - }); -} -function createSafeFragment( document ) { - var list = nodeNames.split( "|" ), - safeFrag = document.createDocumentFragment(); - - if ( safeFrag.createElement ) { - while ( list.length ) { - safeFrag.createElement( - list.pop() - ); - } - } - return safeFrag; -} - -var nodeNames = "abbr|article|aside|audio|bdi|canvas|data|datalist|details|figcaption|figure|footer|" + - "header|hgroup|mark|meter|nav|output|progress|section|summary|time|video", - rinlinejQuery = / jQuery\d+="(?:null|\d+)"/g, - rnoshimcache = new RegExp("<(?:" + nodeNames + ")[\\s/>]", "i"), - rleadingWhitespace = /^\s+/, - rxhtmlTag = /<(?!area|br|col|embed|hr|img|input|link|meta|param)(([\w:]+)[^>]*)\/>/gi, - rtagName = /<([\w:]+)/, - rtbody = /\s*$/g, - - // We have to close these tags to support XHTML (#13200) - wrapMap = { - option: [ 1, "" ], - legend: [ 1, "
", "
" ], - area: [ 1, "", "" ], - param: [ 1, "", "" ], - thead: [ 1, "", "
" ], - tr: [ 2, "", "
" ], - col: [ 2, "", "
" ], - td: [ 3, "", "
" ], - - // IE6-8 can't serialize link, script, style, or any html5 (NoScope) tags, - // unless wrapped in a div with non-breaking characters in front of it. - _default: jQuery.support.htmlSerialize ? [ 0, "", "" ] : [ 1, "X
", "
" ] - }, - safeFragment = createSafeFragment( document ), - fragmentDiv = safeFragment.appendChild( document.createElement("div") ); - -wrapMap.optgroup = wrapMap.option; -wrapMap.tbody = wrapMap.tfoot = wrapMap.colgroup = wrapMap.caption = wrapMap.thead; -wrapMap.th = wrapMap.td; - -jQuery.fn.extend({ - text: function( value ) { - return jQuery.access( this, function( value ) { - return value === undefined ? - jQuery.text( this ) : - this.empty().append( ( this[0] && this[0].ownerDocument || document ).createTextNode( value ) ); - }, null, value, arguments.length ); - }, - - append: function() { - return this.domManip( arguments, function( elem ) { - if ( this.nodeType === 1 || this.nodeType === 11 || this.nodeType === 9 ) { - var target = manipulationTarget( this, elem ); - target.appendChild( elem ); - } - }); - }, - - prepend: function() { - return this.domManip( arguments, function( elem ) { - if ( this.nodeType === 1 || this.nodeType === 11 || this.nodeType === 9 ) { - var target = manipulationTarget( this, elem ); - target.insertBefore( elem, target.firstChild ); - } - }); - }, - - before: function() { - return this.domManip( arguments, function( elem ) { - if ( this.parentNode ) { - this.parentNode.insertBefore( elem, this ); - } - }); - }, - - after: function() { - return this.domManip( arguments, function( elem ) { - if ( this.parentNode ) { - this.parentNode.insertBefore( elem, this.nextSibling ); - } - }); - }, - - // keepData is for internal use only--do not document - remove: function( selector, keepData ) { - var elem, - elems = selector ? jQuery.filter( selector, this ) : this, - i = 0; - - for ( ; (elem = elems[i]) != null; i++ ) { - - if ( !keepData && elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem ) ); - } - - if ( elem.parentNode ) { - if ( keepData && jQuery.contains( elem.ownerDocument, elem ) ) { - setGlobalEval( getAll( elem, "script" ) ); - } - elem.parentNode.removeChild( elem ); - } - } - - return this; - }, - - empty: function() { - var elem, - i = 0; - - for ( ; (elem = this[i]) != null; i++ ) { - // Remove element nodes and prevent memory leaks - if ( elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem, false ) ); - } - - // Remove any remaining nodes - while ( elem.firstChild ) { - elem.removeChild( elem.firstChild ); - } - - // If this is a select, ensure that it displays empty (#12336) - // Support: IE<9 - if ( elem.options && jQuery.nodeName( elem, "select" ) ) { - elem.options.length = 0; - } - } - - return this; - }, - - clone: function( dataAndEvents, deepDataAndEvents ) { - dataAndEvents = dataAndEvents == null ? false : dataAndEvents; - deepDataAndEvents = deepDataAndEvents == null ? dataAndEvents : deepDataAndEvents; - - return this.map( function () { - return jQuery.clone( this, dataAndEvents, deepDataAndEvents ); - }); - }, - - html: function( value ) { - return jQuery.access( this, function( value ) { - var elem = this[0] || {}, - i = 0, - l = this.length; - - if ( value === undefined ) { - return elem.nodeType === 1 ? - elem.innerHTML.replace( rinlinejQuery, "" ) : - undefined; - } - - // See if we can take a shortcut and just use innerHTML - if ( typeof value === "string" && !rnoInnerhtml.test( value ) && - ( jQuery.support.htmlSerialize || !rnoshimcache.test( value ) ) && - ( jQuery.support.leadingWhitespace || !rleadingWhitespace.test( value ) ) && - !wrapMap[ ( rtagName.exec( value ) || ["", ""] )[1].toLowerCase() ] ) { - - value = value.replace( rxhtmlTag, "<$1>" ); - - try { - for (; i < l; i++ ) { - // Remove element nodes and prevent memory leaks - elem = this[i] || {}; - if ( elem.nodeType === 1 ) { - jQuery.cleanData( getAll( elem, false ) ); - elem.innerHTML = value; - } - } - - elem = 0; - - // If using innerHTML throws an exception, use the fallback method - } catch(e) {} - } - - if ( elem ) { - this.empty().append( value ); - } - }, null, value, arguments.length ); - }, - - replaceWith: function() { - var - // Snapshot the DOM in case .domManip sweeps something relevant into its fragment - args = jQuery.map( this, function( elem ) { - return [ elem.nextSibling, elem.parentNode ]; - }), - i = 0; - - // Make the changes, replacing each context element with the new content - this.domManip( arguments, function( elem ) { - var next = args[ i++ ], - parent = args[ i++ ]; - - if ( parent ) { - // Don't use the snapshot next if it has moved (#13810) - if ( next && next.parentNode !== parent ) { - next = this.nextSibling; - } - jQuery( this ).remove(); - parent.insertBefore( elem, next ); - } - // Allow new content to include elements from the context set - }, true ); - - // Force removal if there was no new content (e.g., from empty arguments) - return i ? this : this.remove(); - }, - - detach: function( selector ) { - return this.remove( selector, true ); - }, - - domManip: function( args, callback, allowIntersection ) { - - // Flatten any nested arrays - args = core_concat.apply( [], args ); - - var first, node, hasScripts, - scripts, doc, fragment, - i = 0, - l = this.length, - set = this, - iNoClone = l - 1, - value = args[0], - isFunction = jQuery.isFunction( value ); - - // We can't cloneNode fragments that contain checked, in WebKit - if ( isFunction || !( l <= 1 || typeof value !== "string" || jQuery.support.checkClone || !rchecked.test( value ) ) ) { - return this.each(function( index ) { - var self = set.eq( index ); - if ( isFunction ) { - args[0] = value.call( this, index, self.html() ); - } - self.domManip( args, callback, allowIntersection ); - }); - } - - if ( l ) { - fragment = jQuery.buildFragment( args, this[ 0 ].ownerDocument, false, !allowIntersection && this ); - first = fragment.firstChild; - - if ( fragment.childNodes.length === 1 ) { - fragment = first; - } - - if ( first ) { - scripts = jQuery.map( getAll( fragment, "script" ), disableScript ); - hasScripts = scripts.length; - - // Use the original fragment for the last item instead of the first because it can end up - // being emptied incorrectly in certain situations (#8070). - for ( ; i < l; i++ ) { - node = fragment; - - if ( i !== iNoClone ) { - node = jQuery.clone( node, true, true ); - - // Keep references to cloned scripts for later restoration - if ( hasScripts ) { - jQuery.merge( scripts, getAll( node, "script" ) ); - } - } - - callback.call( this[i], node, i ); - } - - if ( hasScripts ) { - doc = scripts[ scripts.length - 1 ].ownerDocument; - - // Reenable scripts - jQuery.map( scripts, restoreScript ); - - // Evaluate executable scripts on first document insertion - for ( i = 0; i < hasScripts; i++ ) { - node = scripts[ i ]; - if ( rscriptType.test( node.type || "" ) && - !jQuery._data( node, "globalEval" ) && jQuery.contains( doc, node ) ) { - - if ( node.src ) { - // Hope ajax is available... - jQuery._evalUrl( node.src ); - } else { - jQuery.globalEval( ( node.text || node.textContent || node.innerHTML || "" ).replace( rcleanScript, "" ) ); - } - } - } - } - - // Fix #11809: Avoid leaking memory - fragment = first = null; - } - } - - return this; - } -}); - -// Support: IE<8 -// Manipulating tables requires a tbody -function manipulationTarget( elem, content ) { - return jQuery.nodeName( elem, "table" ) && - jQuery.nodeName( content.nodeType === 1 ? content : content.firstChild, "tr" ) ? - - elem.getElementsByTagName("tbody")[0] || - elem.appendChild( elem.ownerDocument.createElement("tbody") ) : - elem; -} - -// Replace/restore the type attribute of script elements for safe DOM manipulation -function disableScript( elem ) { - elem.type = (jQuery.find.attr( elem, "type" ) !== null) + "/" + elem.type; - return elem; -} -function restoreScript( elem ) { - var match = rscriptTypeMasked.exec( elem.type ); - if ( match ) { - elem.type = match[1]; - } else { - elem.removeAttribute("type"); - } - return elem; -} - -// Mark scripts as having already been evaluated -function setGlobalEval( elems, refElements ) { - var elem, - i = 0; - for ( ; (elem = elems[i]) != null; i++ ) { - jQuery._data( elem, "globalEval", !refElements || jQuery._data( refElements[i], "globalEval" ) ); - } -} - -function cloneCopyEvent( src, dest ) { - - if ( dest.nodeType !== 1 || !jQuery.hasData( src ) ) { - return; - } - - var type, i, l, - oldData = jQuery._data( src ), - curData = jQuery._data( dest, oldData ), - events = oldData.events; - - if ( events ) { - delete curData.handle; - curData.events = {}; - - for ( type in events ) { - for ( i = 0, l = events[ type ].length; i < l; i++ ) { - jQuery.event.add( dest, type, events[ type ][ i ] ); - } - } - } - - // make the cloned public data object a copy from the original - if ( curData.data ) { - curData.data = jQuery.extend( {}, curData.data ); - } -} - -function fixCloneNodeIssues( src, dest ) { - var nodeName, e, data; - - // We do not need to do anything for non-Elements - if ( dest.nodeType !== 1 ) { - return; - } - - nodeName = dest.nodeName.toLowerCase(); - - // IE6-8 copies events bound via attachEvent when using cloneNode. - if ( !jQuery.support.noCloneEvent && dest[ jQuery.expando ] ) { - data = jQuery._data( dest ); - - for ( e in data.events ) { - jQuery.removeEvent( dest, e, data.handle ); - } - - // Event data gets referenced instead of copied if the expando gets copied too - dest.removeAttribute( jQuery.expando ); - } - - // IE blanks contents when cloning scripts, and tries to evaluate newly-set text - if ( nodeName === "script" && dest.text !== src.text ) { - disableScript( dest ).text = src.text; - restoreScript( dest ); - - // IE6-10 improperly clones children of object elements using classid. - // IE10 throws NoModificationAllowedError if parent is null, #12132. - } else if ( nodeName === "object" ) { - if ( dest.parentNode ) { - dest.outerHTML = src.outerHTML; - } - - // This path appears unavoidable for IE9. When cloning an object - // element in IE9, the outerHTML strategy above is not sufficient. - // If the src has innerHTML and the destination does not, - // copy the src.innerHTML into the dest.innerHTML. #10324 - if ( jQuery.support.html5Clone && ( src.innerHTML && !jQuery.trim(dest.innerHTML) ) ) { - dest.innerHTML = src.innerHTML; - } - - } else if ( nodeName === "input" && manipulation_rcheckableType.test( src.type ) ) { - // IE6-8 fails to persist the checked state of a cloned checkbox - // or radio button. Worse, IE6-7 fail to give the cloned element - // a checked appearance if the defaultChecked value isn't also set - - dest.defaultChecked = dest.checked = src.checked; - - // IE6-7 get confused and end up setting the value of a cloned - // checkbox/radio button to an empty string instead of "on" - if ( dest.value !== src.value ) { - dest.value = src.value; - } - - // IE6-8 fails to return the selected option to the default selected - // state when cloning options - } else if ( nodeName === "option" ) { - dest.defaultSelected = dest.selected = src.defaultSelected; - - // IE6-8 fails to set the defaultValue to the correct value when - // cloning other types of input fields - } else if ( nodeName === "input" || nodeName === "textarea" ) { - dest.defaultValue = src.defaultValue; - } -} - -jQuery.each({ - appendTo: "append", - prependTo: "prepend", - insertBefore: "before", - insertAfter: "after", - replaceAll: "replaceWith" -}, function( name, original ) { - jQuery.fn[ name ] = function( selector ) { - var elems, - i = 0, - ret = [], - insert = jQuery( selector ), - last = insert.length - 1; - - for ( ; i <= last; i++ ) { - elems = i === last ? this : this.clone(true); - jQuery( insert[i] )[ original ]( elems ); - - // Modern browsers can apply jQuery collections as arrays, but oldIE needs a .get() - core_push.apply( ret, elems.get() ); - } - - return this.pushStack( ret ); - }; -}); - -function getAll( context, tag ) { - var elems, elem, - i = 0, - found = typeof context.getElementsByTagName !== core_strundefined ? context.getElementsByTagName( tag || "*" ) : - typeof context.querySelectorAll !== core_strundefined ? context.querySelectorAll( tag || "*" ) : - undefined; - - if ( !found ) { - for ( found = [], elems = context.childNodes || context; (elem = elems[i]) != null; i++ ) { - if ( !tag || jQuery.nodeName( elem, tag ) ) { - found.push( elem ); - } else { - jQuery.merge( found, getAll( elem, tag ) ); - } - } - } - - return tag === undefined || tag && jQuery.nodeName( context, tag ) ? - jQuery.merge( [ context ], found ) : - found; -} - -// Used in buildFragment, fixes the defaultChecked property -function fixDefaultChecked( elem ) { - if ( manipulation_rcheckableType.test( elem.type ) ) { - elem.defaultChecked = elem.checked; - } -} - -jQuery.extend({ - clone: function( elem, dataAndEvents, deepDataAndEvents ) { - var destElements, node, clone, i, srcElements, - inPage = jQuery.contains( elem.ownerDocument, elem ); - - if ( jQuery.support.html5Clone || jQuery.isXMLDoc(elem) || !rnoshimcache.test( "<" + elem.nodeName + ">" ) ) { - clone = elem.cloneNode( true ); - - // IE<=8 does not properly clone detached, unknown element nodes - } else { - fragmentDiv.innerHTML = elem.outerHTML; - fragmentDiv.removeChild( clone = fragmentDiv.firstChild ); - } - - if ( (!jQuery.support.noCloneEvent || !jQuery.support.noCloneChecked) && - (elem.nodeType === 1 || elem.nodeType === 11) && !jQuery.isXMLDoc(elem) ) { - - // We eschew Sizzle here for performance reasons: http://jsperf.com/getall-vs-sizzle/2 - destElements = getAll( clone ); - srcElements = getAll( elem ); - - // Fix all IE cloning issues - for ( i = 0; (node = srcElements[i]) != null; ++i ) { - // Ensure that the destination node is not null; Fixes #9587 - if ( destElements[i] ) { - fixCloneNodeIssues( node, destElements[i] ); - } - } - } - - // Copy the events from the original to the clone - if ( dataAndEvents ) { - if ( deepDataAndEvents ) { - srcElements = srcElements || getAll( elem ); - destElements = destElements || getAll( clone ); - - for ( i = 0; (node = srcElements[i]) != null; i++ ) { - cloneCopyEvent( node, destElements[i] ); - } - } else { - cloneCopyEvent( elem, clone ); - } - } - - // Preserve script evaluation history - destElements = getAll( clone, "script" ); - if ( destElements.length > 0 ) { - setGlobalEval( destElements, !inPage && getAll( elem, "script" ) ); - } - - destElements = srcElements = node = null; - - // Return the cloned set - return clone; - }, - - buildFragment: function( elems, context, scripts, selection ) { - var j, elem, contains, - tmp, tag, tbody, wrap, - l = elems.length, - - // Ensure a safe fragment - safe = createSafeFragment( context ), - - nodes = [], - i = 0; - - for ( ; i < l; i++ ) { - elem = elems[ i ]; - - if ( elem || elem === 0 ) { - - // Add nodes directly - if ( jQuery.type( elem ) === "object" ) { - jQuery.merge( nodes, elem.nodeType ? [ elem ] : elem ); - - // Convert non-html into a text node - } else if ( !rhtml.test( elem ) ) { - nodes.push( context.createTextNode( elem ) ); - - // Convert html into DOM nodes - } else { - tmp = tmp || safe.appendChild( context.createElement("div") ); - - // Deserialize a standard representation - tag = ( rtagName.exec( elem ) || ["", ""] )[1].toLowerCase(); - wrap = wrapMap[ tag ] || wrapMap._default; - - tmp.innerHTML = wrap[1] + elem.replace( rxhtmlTag, "<$1>" ) + wrap[2]; - - // Descend through wrappers to the right content - j = wrap[0]; - while ( j-- ) { - tmp = tmp.lastChild; - } - - // Manually add leading whitespace removed by IE - if ( !jQuery.support.leadingWhitespace && rleadingWhitespace.test( elem ) ) { - nodes.push( context.createTextNode( rleadingWhitespace.exec( elem )[0] ) ); - } - - // Remove IE's autoinserted from table fragments - if ( !jQuery.support.tbody ) { - - // String was a , *may* have spurious - elem = tag === "table" && !rtbody.test( elem ) ? - tmp.firstChild : - - // String was a bare or - wrap[1] === "
" && !rtbody.test( elem ) ? - tmp : - 0; - - j = elem && elem.childNodes.length; - while ( j-- ) { - if ( jQuery.nodeName( (tbody = elem.childNodes[j]), "tbody" ) && !tbody.childNodes.length ) { - elem.removeChild( tbody ); - } - } - } - - jQuery.merge( nodes, tmp.childNodes ); - - // Fix #12392 for WebKit and IE > 9 - tmp.textContent = ""; - - // Fix #12392 for oldIE - while ( tmp.firstChild ) { - tmp.removeChild( tmp.firstChild ); - } - - // Remember the top-level container for proper cleanup - tmp = safe.lastChild; - } - } - } - - // Fix #11356: Clear elements from fragment - if ( tmp ) { - safe.removeChild( tmp ); - } - - // Reset defaultChecked for any radios and checkboxes - // about to be appended to the DOM in IE 6/7 (#8060) - if ( !jQuery.support.appendChecked ) { - jQuery.grep( getAll( nodes, "input" ), fixDefaultChecked ); - } - - i = 0; - while ( (elem = nodes[ i++ ]) ) { - - // #4087 - If origin and destination elements are the same, and this is - // that element, do not do anything - if ( selection && jQuery.inArray( elem, selection ) !== -1 ) { - continue; - } - - contains = jQuery.contains( elem.ownerDocument, elem ); - - // Append to fragment - tmp = getAll( safe.appendChild( elem ), "script" ); - - // Preserve script evaluation history - if ( contains ) { - setGlobalEval( tmp ); - } - - // Capture executables - if ( scripts ) { - j = 0; - while ( (elem = tmp[ j++ ]) ) { - if ( rscriptType.test( elem.type || "" ) ) { - scripts.push( elem ); - } - } - } - } - - tmp = null; - - return safe; - }, - - cleanData: function( elems, /* internal */ acceptData ) { - var elem, type, id, data, - i = 0, - internalKey = jQuery.expando, - cache = jQuery.cache, - deleteExpando = jQuery.support.deleteExpando, - special = jQuery.event.special; - - for ( ; (elem = elems[i]) != null; i++ ) { - - if ( acceptData || jQuery.acceptData( elem ) ) { - - id = elem[ internalKey ]; - data = id && cache[ id ]; - - if ( data ) { - if ( data.events ) { - for ( type in data.events ) { - if ( special[ type ] ) { - jQuery.event.remove( elem, type ); - - // This is a shortcut to avoid jQuery.event.remove's overhead - } else { - jQuery.removeEvent( elem, type, data.handle ); - } - } - } - - // Remove cache only if it was not already removed by jQuery.event.remove - if ( cache[ id ] ) { - - delete cache[ id ]; - - // IE does not allow us to delete expando properties from nodes, - // nor does it have a removeAttribute function on Document nodes; - // we must handle all of these cases - if ( deleteExpando ) { - delete elem[ internalKey ]; - - } else if ( typeof elem.removeAttribute !== core_strundefined ) { - elem.removeAttribute( internalKey ); - - } else { - elem[ internalKey ] = null; - } - - core_deletedIds.push( id ); - } - } - } - } - }, - - _evalUrl: function( url ) { - return jQuery.ajax({ - url: url, - type: "GET", - dataType: "script", - async: false, - global: false, - "throws": true - }); - } -}); -jQuery.fn.extend({ - wrapAll: function( html ) { - if ( jQuery.isFunction( html ) ) { - return this.each(function(i) { - jQuery(this).wrapAll( html.call(this, i) ); - }); - } - - if ( this[0] ) { - // The elements to wrap the target around - var wrap = jQuery( html, this[0].ownerDocument ).eq(0).clone(true); - - if ( this[0].parentNode ) { - wrap.insertBefore( this[0] ); - } - - wrap.map(function() { - var elem = this; - - while ( elem.firstChild && elem.firstChild.nodeType === 1 ) { - elem = elem.firstChild; - } - - return elem; - }).append( this ); - } - - return this; - }, - - wrapInner: function( html ) { - if ( jQuery.isFunction( html ) ) { - return this.each(function(i) { - jQuery(this).wrapInner( html.call(this, i) ); - }); - } - - return this.each(function() { - var self = jQuery( this ), - contents = self.contents(); - - if ( contents.length ) { - contents.wrapAll( html ); - - } else { - self.append( html ); - } - }); - }, - - wrap: function( html ) { - var isFunction = jQuery.isFunction( html ); - - return this.each(function(i) { - jQuery( this ).wrapAll( isFunction ? html.call(this, i) : html ); - }); - }, - - unwrap: function() { - return this.parent().each(function() { - if ( !jQuery.nodeName( this, "body" ) ) { - jQuery( this ).replaceWith( this.childNodes ); - } - }).end(); - } -}); -var iframe, getStyles, curCSS, - ralpha = /alpha\([^)]*\)/i, - ropacity = /opacity\s*=\s*([^)]*)/, - rposition = /^(top|right|bottom|left)$/, - // swappable if display is none or starts with table except "table", "table-cell", or "table-caption" - // see here for display values: https://developer.mozilla.org/en-US/docs/CSS/display - rdisplayswap = /^(none|table(?!-c[ea]).+)/, - rmargin = /^margin/, - rnumsplit = new RegExp( "^(" + core_pnum + ")(.*)$", "i" ), - rnumnonpx = new RegExp( "^(" + core_pnum + ")(?!px)[a-z%]+$", "i" ), - rrelNum = new RegExp( "^([+-])=(" + core_pnum + ")", "i" ), - elemdisplay = { BODY: "block" }, - - cssShow = { position: "absolute", visibility: "hidden", display: "block" }, - cssNormalTransform = { - letterSpacing: 0, - fontWeight: 400 - }, - - cssExpand = [ "Top", "Right", "Bottom", "Left" ], - cssPrefixes = [ "Webkit", "O", "Moz", "ms" ]; - -// return a css property mapped to a potentially vendor prefixed property -function vendorPropName( style, name ) { - - // shortcut for names that are not vendor prefixed - if ( name in style ) { - return name; - } - - // check for vendor prefixed names - var capName = name.charAt(0).toUpperCase() + name.slice(1), - origName = name, - i = cssPrefixes.length; - - while ( i-- ) { - name = cssPrefixes[ i ] + capName; - if ( name in style ) { - return name; - } - } - - return origName; -} - -function isHidden( elem, el ) { - // isHidden might be called from jQuery#filter function; - // in that case, element will be second argument - elem = el || elem; - return jQuery.css( elem, "display" ) === "none" || !jQuery.contains( elem.ownerDocument, elem ); -} - -function showHide( elements, show ) { - var display, elem, hidden, - values = [], - index = 0, - length = elements.length; - - for ( ; index < length; index++ ) { - elem = elements[ index ]; - if ( !elem.style ) { - continue; - } - - values[ index ] = jQuery._data( elem, "olddisplay" ); - display = elem.style.display; - if ( show ) { - // Reset the inline display of this element to learn if it is - // being hidden by cascaded rules or not - if ( !values[ index ] && display === "none" ) { - elem.style.display = ""; - } - - // Set elements which have been overridden with display: none - // in a stylesheet to whatever the default browser style is - // for such an element - if ( elem.style.display === "" && isHidden( elem ) ) { - values[ index ] = jQuery._data( elem, "olddisplay", css_defaultDisplay(elem.nodeName) ); - } - } else { - - if ( !values[ index ] ) { - hidden = isHidden( elem ); - - if ( display && display !== "none" || !hidden ) { - jQuery._data( elem, "olddisplay", hidden ? display : jQuery.css( elem, "display" ) ); - } - } - } - } - - // Set the display of most of the elements in a second loop - // to avoid the constant reflow - for ( index = 0; index < length; index++ ) { - elem = elements[ index ]; - if ( !elem.style ) { - continue; - } - if ( !show || elem.style.display === "none" || elem.style.display === "" ) { - elem.style.display = show ? values[ index ] || "" : "none"; - } - } - - return elements; -} - -jQuery.fn.extend({ - css: function( name, value ) { - return jQuery.access( this, function( elem, name, value ) { - var len, styles, - map = {}, - i = 0; - - if ( jQuery.isArray( name ) ) { - styles = getStyles( elem ); - len = name.length; - - for ( ; i < len; i++ ) { - map[ name[ i ] ] = jQuery.css( elem, name[ i ], false, styles ); - } - - return map; - } - - return value !== undefined ? - jQuery.style( elem, name, value ) : - jQuery.css( elem, name ); - }, name, value, arguments.length > 1 ); - }, - show: function() { - return showHide( this, true ); - }, - hide: function() { - return showHide( this ); - }, - toggle: function( state ) { - if ( typeof state === "boolean" ) { - return state ? this.show() : this.hide(); - } - - return this.each(function() { - if ( isHidden( this ) ) { - jQuery( this ).show(); - } else { - jQuery( this ).hide(); - } - }); - } -}); - -jQuery.extend({ - // Add in style property hooks for overriding the default - // behavior of getting and setting a style property - cssHooks: { - opacity: { - get: function( elem, computed ) { - if ( computed ) { - // We should always get a number back from opacity - var ret = curCSS( elem, "opacity" ); - return ret === "" ? "1" : ret; - } - } - } - }, - - // Don't automatically add "px" to these possibly-unitless properties - cssNumber: { - "columnCount": true, - "fillOpacity": true, - "fontWeight": true, - "lineHeight": true, - "opacity": true, - "order": true, - "orphans": true, - "widows": true, - "zIndex": true, - "zoom": true - }, - - // Add in properties whose names you wish to fix before - // setting or getting the value - cssProps: { - // normalize float css property - "float": jQuery.support.cssFloat ? "cssFloat" : "styleFloat" - }, - - // Get and set the style property on a DOM Node - style: function( elem, name, value, extra ) { - // Don't set styles on text and comment nodes - if ( !elem || elem.nodeType === 3 || elem.nodeType === 8 || !elem.style ) { - return; - } - - // Make sure that we're working with the right name - var ret, type, hooks, - origName = jQuery.camelCase( name ), - style = elem.style; - - name = jQuery.cssProps[ origName ] || ( jQuery.cssProps[ origName ] = vendorPropName( style, origName ) ); - - // gets hook for the prefixed version - // followed by the unprefixed version - hooks = jQuery.cssHooks[ name ] || jQuery.cssHooks[ origName ]; - - // Check if we're setting a value - if ( value !== undefined ) { - type = typeof value; - - // convert relative number strings (+= or -=) to relative numbers. #7345 - if ( type === "string" && (ret = rrelNum.exec( value )) ) { - value = ( ret[1] + 1 ) * ret[2] + parseFloat( jQuery.css( elem, name ) ); - // Fixes bug #9237 - type = "number"; - } - - // Make sure that NaN and null values aren't set. See: #7116 - if ( value == null || type === "number" && isNaN( value ) ) { - return; - } - - // If a number was passed in, add 'px' to the (except for certain CSS properties) - if ( type === "number" && !jQuery.cssNumber[ origName ] ) { - value += "px"; - } - - // Fixes #8908, it can be done more correctly by specifing setters in cssHooks, - // but it would mean to define eight (for every problematic property) identical functions - if ( !jQuery.support.clearCloneStyle && value === "" && name.indexOf("background") === 0 ) { - style[ name ] = "inherit"; - } - - // If a hook was provided, use that value, otherwise just set the specified value - if ( !hooks || !("set" in hooks) || (value = hooks.set( elem, value, extra )) !== undefined ) { - - // Wrapped to prevent IE from throwing errors when 'invalid' values are provided - // Fixes bug #5509 - try { - style[ name ] = value; - } catch(e) {} - } - - } else { - // If a hook was provided get the non-computed value from there - if ( hooks && "get" in hooks && (ret = hooks.get( elem, false, extra )) !== undefined ) { - return ret; - } - - // Otherwise just get the value from the style object - return style[ name ]; - } - }, - - css: function( elem, name, extra, styles ) { - var num, val, hooks, - origName = jQuery.camelCase( name ); - - // Make sure that we're working with the right name - name = jQuery.cssProps[ origName ] || ( jQuery.cssProps[ origName ] = vendorPropName( elem.style, origName ) ); - - // gets hook for the prefixed version - // followed by the unprefixed version - hooks = jQuery.cssHooks[ name ] || jQuery.cssHooks[ origName ]; - - // If a hook was provided get the computed value from there - if ( hooks && "get" in hooks ) { - val = hooks.get( elem, true, extra ); - } - - // Otherwise, if a way to get the computed value exists, use that - if ( val === undefined ) { - val = curCSS( elem, name, styles ); - } - - //convert "normal" to computed value - if ( val === "normal" && name in cssNormalTransform ) { - val = cssNormalTransform[ name ]; - } - - // Return, converting to number if forced or a qualifier was provided and val looks numeric - if ( extra === "" || extra ) { - num = parseFloat( val ); - return extra === true || jQuery.isNumeric( num ) ? num || 0 : val; - } - return val; - } -}); - -// NOTE: we've included the "window" in window.getComputedStyle -// because jsdom on node.js will break without it. -if ( window.getComputedStyle ) { - getStyles = function( elem ) { - return window.getComputedStyle( elem, null ); - }; - - curCSS = function( elem, name, _computed ) { - var width, minWidth, maxWidth, - computed = _computed || getStyles( elem ), - - // getPropertyValue is only needed for .css('filter') in IE9, see #12537 - ret = computed ? computed.getPropertyValue( name ) || computed[ name ] : undefined, - style = elem.style; - - if ( computed ) { - - if ( ret === "" && !jQuery.contains( elem.ownerDocument, elem ) ) { - ret = jQuery.style( elem, name ); - } - - // A tribute to the "awesome hack by Dean Edwards" - // Chrome < 17 and Safari 5.0 uses "computed value" instead of "used value" for margin-right - // Safari 5.1.7 (at least) returns percentage for a larger set of values, but width seems to be reliably pixels - // this is against the CSSOM draft spec: http://dev.w3.org/csswg/cssom/#resolved-values - if ( rnumnonpx.test( ret ) && rmargin.test( name ) ) { - - // Remember the original values - width = style.width; - minWidth = style.minWidth; - maxWidth = style.maxWidth; - - // Put in the new values to get a computed value out - style.minWidth = style.maxWidth = style.width = ret; - ret = computed.width; - - // Revert the changed values - style.width = width; - style.minWidth = minWidth; - style.maxWidth = maxWidth; - } - } - - return ret; - }; -} else if ( document.documentElement.currentStyle ) { - getStyles = function( elem ) { - return elem.currentStyle; - }; - - curCSS = function( elem, name, _computed ) { - var left, rs, rsLeft, - computed = _computed || getStyles( elem ), - ret = computed ? computed[ name ] : undefined, - style = elem.style; - - // Avoid setting ret to empty string here - // so we don't default to auto - if ( ret == null && style && style[ name ] ) { - ret = style[ name ]; - } - - // From the awesome hack by Dean Edwards - // http://erik.eae.net/archives/2007/07/27/18.54.15/#comment-102291 - - // If we're not dealing with a regular pixel number - // but a number that has a weird ending, we need to convert it to pixels - // but not position css attributes, as those are proportional to the parent element instead - // and we can't measure the parent instead because it might trigger a "stacking dolls" problem - if ( rnumnonpx.test( ret ) && !rposition.test( name ) ) { - - // Remember the original values - left = style.left; - rs = elem.runtimeStyle; - rsLeft = rs && rs.left; - - // Put in the new values to get a computed value out - if ( rsLeft ) { - rs.left = elem.currentStyle.left; - } - style.left = name === "fontSize" ? "1em" : ret; - ret = style.pixelLeft + "px"; - - // Revert the changed values - style.left = left; - if ( rsLeft ) { - rs.left = rsLeft; - } - } - - return ret === "" ? "auto" : ret; - }; -} - -function setPositiveNumber( elem, value, subtract ) { - var matches = rnumsplit.exec( value ); - return matches ? - // Guard against undefined "subtract", e.g., when used as in cssHooks - Math.max( 0, matches[ 1 ] - ( subtract || 0 ) ) + ( matches[ 2 ] || "px" ) : - value; -} - -function augmentWidthOrHeight( elem, name, extra, isBorderBox, styles ) { - var i = extra === ( isBorderBox ? "border" : "content" ) ? - // If we already have the right measurement, avoid augmentation - 4 : - // Otherwise initialize for horizontal or vertical properties - name === "width" ? 1 : 0, - - val = 0; - - for ( ; i < 4; i += 2 ) { - // both box models exclude margin, so add it if we want it - if ( extra === "margin" ) { - val += jQuery.css( elem, extra + cssExpand[ i ], true, styles ); - } - - if ( isBorderBox ) { - // border-box includes padding, so remove it if we want content - if ( extra === "content" ) { - val -= jQuery.css( elem, "padding" + cssExpand[ i ], true, styles ); - } - - // at this point, extra isn't border nor margin, so remove border - if ( extra !== "margin" ) { - val -= jQuery.css( elem, "border" + cssExpand[ i ] + "Width", true, styles ); - } - } else { - // at this point, extra isn't content, so add padding - val += jQuery.css( elem, "padding" + cssExpand[ i ], true, styles ); - - // at this point, extra isn't content nor padding, so add border - if ( extra !== "padding" ) { - val += jQuery.css( elem, "border" + cssExpand[ i ] + "Width", true, styles ); - } - } - } - - return val; -} - -function getWidthOrHeight( elem, name, extra ) { - - // Start with offset property, which is equivalent to the border-box value - var valueIsBorderBox = true, - val = name === "width" ? elem.offsetWidth : elem.offsetHeight, - styles = getStyles( elem ), - isBorderBox = jQuery.support.boxSizing && jQuery.css( elem, "boxSizing", false, styles ) === "border-box"; - - // some non-html elements return undefined for offsetWidth, so check for null/undefined - // svg - https://bugzilla.mozilla.org/show_bug.cgi?id=649285 - // MathML - https://bugzilla.mozilla.org/show_bug.cgi?id=491668 - if ( val <= 0 || val == null ) { - // Fall back to computed then uncomputed css if necessary - val = curCSS( elem, name, styles ); - if ( val < 0 || val == null ) { - val = elem.style[ name ]; - } - - // Computed unit is not pixels. Stop here and return. - if ( rnumnonpx.test(val) ) { - return val; - } - - // we need the check for style in case a browser which returns unreliable values - // for getComputedStyle silently falls back to the reliable elem.style - valueIsBorderBox = isBorderBox && ( jQuery.support.boxSizingReliable || val === elem.style[ name ] ); - - // Normalize "", auto, and prepare for extra - val = parseFloat( val ) || 0; - } - - // use the active box-sizing model to add/subtract irrelevant styles - return ( val + - augmentWidthOrHeight( - elem, - name, - extra || ( isBorderBox ? "border" : "content" ), - valueIsBorderBox, - styles - ) - ) + "px"; -} - -// Try to determine the default display value of an element -function css_defaultDisplay( nodeName ) { - var doc = document, - display = elemdisplay[ nodeName ]; - - if ( !display ) { - display = actualDisplay( nodeName, doc ); - - // If the simple way fails, read from inside an iframe - if ( display === "none" || !display ) { - // Use the already-created iframe if possible - iframe = ( iframe || - jQuery("