diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv
index 372b4baee..f88ce5075 100644
--- a/core/cache_subsystem/cache_ctrl.sv
+++ b/core/cache_subsystem/cache_ctrl.sv
@@ -19,7 +19,7 @@
 
 
 module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
-    parameter logic [63:0] CACHE_START_ADDR  = 64'h4000_0000
+    parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig // contains cacheable regions
 ) (
     input  logic                                 clk_i,     // Clock
     input  logic                                 rst_ni,    // Asynchronous reset active low
@@ -250,7 +250,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
                     // -------------------------
                     // Check for cache-ability
                     // -------------------------
-                    if (tag_o < CACHE_START_ADDR[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH]) begin
+                    if (!is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}})) begin
                         mem_req_d.bypass = 1'b1;
                         state_d = WAIT_REFILL_GNT;
                     end
diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv
index 0523fb6b8..45009c47d 100644
--- a/core/cache_subsystem/std_cache_subsystem.sv
+++ b/core/cache_subsystem/std_cache_subsystem.sv
@@ -80,7 +80,7 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
    // Port 1: Load Unit
    // Port 2: Store Unit
    std_nbdcache #(
-      .CACHE_START_ADDR ( ArianeCfg.CachedRegionAddrBase )
+      .ArianeCfg        ( ArianeCfg          )
    ) i_nbdcache (
       .clk_i,
       .rst_ni,
diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv
index 873d1b687..55eb00f2c 100644
--- a/core/cache_subsystem/std_nbdcache.sv
+++ b/core/cache_subsystem/std_nbdcache.sv
@@ -14,7 +14,7 @@
 
 
 module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
-    parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000
+    parameter ariane_cfg_t ArianeCfg        = ArianeDefaultConfig // contains cacheable regions
 )(
     input  logic                           clk_i,       // Clock
     input  logic                           rst_ni,      // Asynchronous reset active low
@@ -88,7 +88,7 @@ import std_cache_pkg::*;
     generate
         for (genvar i = 0; i < 3; i++) begin : master_ports
             cache_ctrl  #(
-                .CACHE_START_ADDR      ( CACHE_START_ADDR     )
+                .ArianeCfg             ( ArianeCfg            )
             ) i_cache_ctrl (
                 .bypass_i              ( ~enable_i            ),
                 .busy_o                ( busy            [i]  ),
diff --git a/core/cache_subsystem/std_no_dcache.sv b/core/cache_subsystem/std_no_dcache.sv
index 339c7cf0e..d9a8245fc 100644
--- a/core/cache_subsystem/std_no_dcache.sv
+++ b/core/cache_subsystem/std_no_dcache.sv
@@ -12,7 +12,7 @@
 // Description: Bypass version of data cache
 
 module std_nbdcache #(
-    parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000
+    parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
 ) (
     input  logic                            clk_i,       // Clock
     input  logic                            rst_ni,      // Asynchronous reset active low