diff --git a/README.md b/README.md
index eee63bb18..965953483 100644
--- a/README.md
+++ b/README.md
@@ -13,7 +13,7 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b
 If you use CVA6 in your academic work you can cite us:
 
 ```
-@article{8777130,
+@article{zaruba2019cost,
    author={F. {Zaruba} and L. {Benini}},
    journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
    title={The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology},
@@ -50,6 +50,13 @@ Table of Contents
 
 Created by [gh-md-toc](https://github.com/ekalinin/github-markdown-toc)
 
+## Tool Requirements
+
+* `verilator >= 4.002`
+
+> There is currently a known issue with version 4.106 and 4.108. 4.106 does not
+> compile and 4.108 hangs after a couple of cycles simulation time.
+
 ## Getting Started
 
 Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information).
diff --git a/src/util/sram.sv b/src/util/sram.sv
index 4943cfc91..64c2b1d8c 100644
--- a/src/util/sram.sv
+++ b/src/util/sram.sv
@@ -51,44 +51,41 @@ always_comb begin : p_align
     rdata_o = rdata_aligned[DATA_WIDTH-1:0];
 end
 
-genvar k;
-generate
-    for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
-      if (DROMAJO_RAM) begin
-        dromajo_ram #(
-          .ADDR_WIDTH($clog2(NUM_WORDS)),
-          .DATA_DEPTH(NUM_WORDS),
-          .OUT_REGS (0)
-        ) i_ram (
-           .Clk_CI    ( clk_i                     ),
-           .Rst_RBI   ( rst_ni                    ),
-           .CSel_SI   ( req_i                     ),
-           .WrEn_SI   ( we_i                      ),
-           .BEn_SI    ( be_aligned[k*8 +: 8]      ),
-           .WrData_DI ( wdata_aligned[k*64 +: 64] ),
-           .Addr_DI   ( addr_i                    ),
-           .RdData_DO ( rdata_aligned[k*64 +: 64] )
-        );
-      end else begin
-        // unused byte-enable segments (8bits) are culled by the tool
-        SyncSpRamBeNx64 #(
-          .ADDR_WIDTH($clog2(NUM_WORDS)),
-          .DATA_DEPTH(NUM_WORDS),
-          .OUT_REGS (0),
-          // this initializes the memory with 0es. adjust to taste...
-          // 0: no init, 1: zero init, 2: random init, 3: deadbeef init
-          .SIM_INIT (1)
-        ) i_ram (
-           .Clk_CI    ( clk_i                     ),
-           .Rst_RBI   ( rst_ni                    ),
-           .CSel_SI   ( req_i                     ),
-           .WrEn_SI   ( we_i                      ),
-           .BEn_SI    ( be_aligned[k*8 +: 8]      ),
-           .WrData_DI ( wdata_aligned[k*64 +: 64] ),
-           .Addr_DI   ( addr_i                    ),
-           .RdData_DO ( rdata_aligned[k*64 +: 64] )
-        );
-      end
+  for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut
+    if (DROMAJO_RAM) begin : gen_dromajo
+      dromajo_ram #(
+        .ADDR_WIDTH($clog2(NUM_WORDS)),
+        .DATA_DEPTH(NUM_WORDS),
+        .OUT_REGS (0)
+      ) i_ram (
+          .Clk_CI    ( clk_i                     ),
+          .Rst_RBI   ( rst_ni                    ),
+          .CSel_SI   ( req_i                     ),
+          .WrEn_SI   ( we_i                      ),
+          .BEn_SI    ( be_aligned[k*8 +: 8]      ),
+          .WrData_DI ( wdata_aligned[k*64 +: 64] ),
+          .Addr_DI   ( addr_i                    ),
+          .RdData_DO ( rdata_aligned[k*64 +: 64] )
+      );
+    end else begin : gen_mem
+      // unused byte-enable segments (8bits) are culled by the tool
+      SyncSpRamBeNx64 #(
+        .ADDR_WIDTH($clog2(NUM_WORDS)),
+        .DATA_DEPTH(NUM_WORDS),
+        .OUT_REGS (0),
+        // this initializes the memory with 0es. adjust to taste...
+        // 0: no init, 1: zero init, 2: random init, 3: deadbeef init
+        .SIM_INIT (1)
+      ) i_ram (
+          .Clk_CI    ( clk_i                     ),
+          .Rst_RBI   ( rst_ni                    ),
+          .CSel_SI   ( req_i                     ),
+          .WrEn_SI   ( we_i                      ),
+          .BEn_SI    ( be_aligned[k*8 +: 8]      ),
+          .WrData_DI ( wdata_aligned[k*64 +: 64] ),
+          .Addr_DI   ( addr_i                    ),
+          .RdData_DO ( rdata_aligned[k*64 +: 64] )
+      );
     end
-endgenerate
+  end
 endmodule : sram
diff --git a/tb/ariane_tb.cpp b/tb/ariane_tb.cpp
index dc62baf6b..0b6651742 100644
--- a/tb/ariane_tb.cpp
+++ b/tb/ariane_tb.cpp
@@ -320,7 +320,7 @@ done_processing:
 
   // Preload memory.
   size_t mem_size = 0x100000;
-  memif.read(0x80000000, mem_size, (void *) top->ariane_testharness__DOT__i_sram__DOT__genblk1__BRA__0__KET____DOT__genblk2__DOT__i_ram__DOT__Mem_DP);
+  memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_ram__DOT__Mem_DP);
 
 #ifndef DROMAJO
   while (!dtm->done() && !jtag->done()) {