diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index 88adb53a7..3a409d592 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -901,10 +901,11 @@ module csr_regfile
       // increase instruction retired counter
       if (commit_ack_i[0] && !(ex_i.valid && CVA6Cfg.SpeculativeSb) && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2])))
         instret++;
-      for (int i = 1; i < CVA6Cfg.NrCommitPorts; i++) begin
-        if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2])))
-          instret++;
-      end
+      if (CVA6Cfg.NrCommitPorts != 0)
+        for (int i = 1; i < CVA6Cfg.NrCommitPorts; i++) begin
+          if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2])))
+            instret++;
+        end
       instret_d = instret;
       // increment the cycle count
       if (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[0]))
diff --git a/core/cva6_pipeline.sv b/core/cva6_pipeline.sv
index e5a7bb1ca..1db1becce 100644
--- a/core/cva6_pipeline.sv
+++ b/core/cva6_pipeline.sv
@@ -1063,7 +1063,7 @@ module cva6_pipeline
       .flush_dcache_i    (dcache_flush_o),
       .exception_o       (ex_commit),
       .dirty_fp_state_o  (dirty_fp_state),
-      .single_step_i     (single_step_csr_commit),         // // Accelerator /*FIXME*/ 
+      .single_step_i     (single_step_csr_commit),         // // Accelerator /*FIXME*/
       .commit_instr_i    (commit_instr_id_commit),
       .commit_drop_i     (commit_drop_id_commit),
       .commit_ack_o      (commit_ack_commit_id),
@@ -1093,7 +1093,7 @@ module cva6_pipeline
       .hfence_gvma_o     (hfence_gvma_commit_controller)
   );
 
-  assign commit_ack = commit_macro_ack & ~commit_drop_id_commit;
+  assign commit_ack = commit_macro_ack & ~(commit_drop_id_commit & CVA6Cfg.SpeculativeSb);
 
   // ---------
   // CSR