diff --git a/README.md b/README.md index 780862acb..cf9f51f6f 100644 --- a/README.md +++ b/README.md @@ -43,7 +43,7 @@ Check out the [contribution guide](CONTRIBUTING.md) ## User Mode Integer Tests -| **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | +| **Test Name** | **P/V** | **Test Name** | **P/V** | **Test Name** | **P/V** | |---------------|--------------------|---------------|--------------------|---------------|--------------------| | add | :white_check_mark: | lb | :white_check_mark: | sll | :white_check_mark: | | addi | :white_check_mark: | lbu | :white_check_mark: | slli | :white_check_mark: | @@ -57,7 +57,7 @@ Check out the [contribution guide](CONTRIBUTING.md) | bgeu | :white_check_mark: | ori | :white_check_mark: | srai | :white_check_mark: | | blt | :white_check_mark: | sb | :white_check_mark: | sraiw | :white_check_mark: | | bltu | :white_check_mark: | sd | :white_check_mark: | sraw | :white_check_mark: | -| bne | :white_check_mark: | sh | :white_check_mark: | srl | :white_check_mark: | +| bne | :white_check_mark: | sh | :white_check_mark: | srl | :white_check_mark: :white_check_mark:| | sub | :white_check_mark: | simple | :white_check_mark: | srli | :white_check_mark: | | subw | :white_check_mark: | jal | :white_check_mark: | srliw | :white_check_mark: | | sw | :white_check_mark: | jalr | :white_check_mark: | srlw | :white_check_mark: | @@ -66,9 +66,9 @@ Check out the [contribution guide](CONTRIBUTING.md) ## Compressed Instruction Tests -| **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | -|---------------|--------------------|---------------|-----------|---------------|-----------| -| rvc | :white_check_mark: | | | | | +| **Test Name** | **P/V** | **Test Name** | **P/V** | **Test Name** | **P/V** | +|---------------|--------------------|---------------|---------|---------------|---------| +| rvc | :white_check_mark: | | | | | ## Machine Mode Tests diff --git a/include/ariane_pkg.svh b/include/ariane_pkg.svh index 6a23a258c..4e690e4b6 100644 --- a/include/ariane_pkg.svh +++ b/include/ariane_pkg.svh @@ -282,6 +282,8 @@ package ariane_pkg; CSR_MARCHID = 12'hF12, CSR_MIMPID = 12'hF13, CSR_MHARTID = 12'hF14, + CSR_MCYCLE = 12'hB00, + CSR_MINSTRET = 12'hB02, // Counters and Timers CSR_CYCLE = 12'hC00, CSR_TIME = 12'hC01, diff --git a/riscv-tests b/riscv-tests index a5b39e05e..1495764f9 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit a5b39e05ee674fee0df32fdad5fdb763f4a31d19 +Subproject commit 1495764f9bf6d9eaca494ff818a23b2a29b5d210 diff --git a/src/branch_unit.sv b/src/branch_unit.sv index 28648f233..7fafd9dbe 100644 --- a/src/branch_unit.sv +++ b/src/branch_unit.sv @@ -93,7 +93,7 @@ module branch_unit ( // save PC - we need this to get the target row in the branch target buffer // we play this trick with the branch instruction which wraps a byte boundary: - // |---------- Place the prediction on this PC + // /---------- Place the prediction on this PC // \/ // ____________________________________________________ // |branch [15:0] | branch[31:16] | compressed 1[15:0] | diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv index b02d532a7..19c2a9e02 100644 --- a/src/csr_regfile.sv +++ b/src/csr_regfile.sv @@ -185,6 +185,8 @@ module csr_regfile #( CSR_MARCHID: csr_rdata = 64'b0; // PULP, anonymous source (no allocated ID yet) CSR_MIMPID: csr_rdata = 64'b0; // not implemented CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]}; + CSR_MCYCLE: csr_rdata = cycle_q; + CSR_MINSTRET: csr_rdata = instret_q; // Counters and Timers CSR_CYCLE: csr_rdata = cycle_q; CSR_TIME: csr_rdata = time_q; @@ -289,6 +291,8 @@ module csr_regfile #( CSR_MEPC: mepc_n = {csr_wdata[63:1], 1'b0}; CSR_MCAUSE: mcause_n = csr_wdata; CSR_MTVAL: mtval_n = csr_wdata; + CSR_MCYCLE: cycle_n = csr_wdata; + CSR_MINSTRET: instret_n = csr_wdata; default: update_access_exception = 1'b1; endcase // so we wrote something, TODO: this can be more fine grained (e.g.: did it have side effects?) @@ -398,12 +402,10 @@ module csr_regfile #( // set spie to 1 mstatus_n.spie = 1'b1; end - end - // -------------------- - // Timers and Counters - // -------------------- - always_comb begin : timers_counters + // -------------------- + // Timers and Counters + // -------------------- instret_n = instret_q; // just increment the cycle count cycle_n = cycle_q + 1'b1; diff --git a/src/ex_stage.sv b/src/ex_stage.sv index 8b7b56c7c..8d27f1802 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -124,7 +124,7 @@ module ex_stage #( // Branch Engine // -------------------- branch_unit branch_unit_i ( - .fu_valid_i ( alu_valid_i | lsu_valid_i | csr_valid_i ), // any functional unit is valid, check that there is no accidental mis-predict + .fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i ), // any functional unit is valid, check that there is no accidental mis-predict .* ); diff --git a/src/scoreboard.sv b/src/scoreboard.sv index 6fee6a568..28ec6d3c0 100644 --- a/src/scoreboard.sv +++ b/src/scoreboard.sv @@ -233,10 +233,10 @@ module scoreboard #( commit_pointer_q <= '0; issue_pointer_q <= '0; end else begin - mem_q <= mem_n; issue_cnt_q <= issue_cnt_n; - commit_pointer_q <= commit_pointer_n; issue_pointer_q <= issue_pointer_n; + mem_q <= mem_n; + commit_pointer_q <= commit_pointer_n; end end `ifndef SYNTHESIS diff --git a/src/util/instruction_trace_item.svh b/src/util/instruction_trace_item.svh index 48fba7cb0..3cc5c6e65 100755 --- a/src/util/instruction_trace_item.svh +++ b/src/util/instruction_trace_item.svh @@ -84,6 +84,9 @@ class instruction_trace_item; CSR_MARCHID: return "marchid"; CSR_MIMPID: return "mimpid"; CSR_MHARTID: return "mhartid"; + CSR_MCYCLE: return "mcycle"; + CSR_MINSTRET: return "minstret"; + CSR_CYCLE: return "cycle"; CSR_TIME: return "time"; CSR_INSTRET: return "instret";