diff --git a/config/gen_from_riscv_config/README.md b/config/gen_from_riscv_config/README.md index 5a60339a0..4de91244f 100644 --- a/config/gen_from_riscv_config/README.md +++ b/config/gen_from_riscv_config/README.md @@ -33,21 +33,23 @@ pip3 install -r requirements.txt ## Usage ```bash -#Generate the Markdown-text /Restructred-text documentation for Control and Status Registers (CSR) -python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -m .yaml -t < Config_Name> +#Generate Restructred-text documentation for Control and Status Registers (CSR) +python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml-m .yaml -t < Config_Name> -#Generate the Markdown-text /Restructred-text documentation for ISA extensions +#Generate Restructred-text documentation for ISA extensions python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -i .yaml -m .yaml -t < Config_Name> + ``` ## Usage with cv32a65x ```bash -#Generate the Markdown-text /Restructred-text documentation for Control and Status Registers (CSR) -python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x +#Generate the Restructred-text documentation for Control and Status Registers (CSR) +python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x -#Generate the Markdown-text /Restructred-text documentation for ISA extensions +#Generate the Restructred-text documentation for ISA extensions python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x + ``` You could find your output files in this directory : @@ -57,6 +59,7 @@ if the output is ISA Documentation: if the output is CSR Documentation : `/csr/` + for more details about How to write CSR or ISA Updater,see [UPDATERS](##Updaters) section @@ -64,6 +67,7 @@ for more details about How to write CSR or ISA Updater,see [UPDATERS](##Updaters for more details about How to write ISA template ,see [Annexes2](##Annexes2) section + ## Updaters diff --git a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst index e376cfd97..9f02642f2 100644 --- a/config/gen_from_riscv_config/cv32a65x/csr/csr.rst +++ b/config/gen_from_riscv_config/cv32a65x/csr/csr.rst @@ -40,62 +40,68 @@ value (typically zero). Register Summary ---------------- -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| Address | Register Name | Privilege | Description | -+=============+=====================+=============+====================================================================================================+ -| 0x300 | MSTATUS_ | MRW | The mstatus register keeps track of and controls the hart's current operating state. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x301 | MISA_ | MRW | misa is a read-write register reporting the ISA supported by the hart. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x304 | MIE_ | MRW | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x305 | MTVEC_ | MRW | MXLEN-bit read/write register that holds trap vector configuration. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x310 | MSTATUSH_ | MRW | The mstatush register keeps track of and controls the hart’s current operating state. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x323-0x33f | MHPMEVENT[3-31]_ | MRW | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x340 | MSCRATCH_ | MRW | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x341 | MEPC_ | MRW | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x342 | MCAUSE_ | MRW | The mcause register stores the information regarding the trap. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x343 | MTVAL_ | MRW | The mtval is a warl register that holds the address of the instruction which caused the exception. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x344 | MIP_ | MRW | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x3a0-0x3a3 | PMPCFG[0-3]_ | MRW | PMP configuration register | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0x3b0-0x3bf | PMPADDR[0-15]_ | MRW | Physical memory protection address register | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb00 | MCYCLE_ | MRW | Counts the number of clock cycles executed from an arbitrary point in time. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb02 | MINSTRET_ | MRW | Counts the number of instructions completed from an arbitrary point in time. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb03-0xb1f | MHPMCOUNTER[3-31]_ | MRW | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb80 | MCYCLEH_ | MRW | upper 32 bits of mcycle | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb82 | MINSTRETH_ | MRW | Upper 32 bits of minstret. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xb83-0xb9f | MHPMCOUNTER[3-31]H_ | MRW | The mhpmcounterh returns the upper half word in RV32I systems. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xf11 | MVENDORID_ | MRO | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xf12 | MARCHID_ | MRO | MXLEN-bit read-only register encoding the base microarchitecture of the hart. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xf13 | MIMPID_ | MRO | Provides a unique encoding of the version of the processor implementation. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xf14 | MHARTID_ | MRO | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ -| 0xf15 | MCONFIGPTR_ | MRO | MXLEN-bit read-only register that holds the physical address of a configuration data structure. | -+-------------+---------------------+-------------+----------------------------------------------------------------------------------------------------+ ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| Address | Register Name | Privilege | Description | ++=============+=============================================+=============+====================================================================================================+ +| 0x300 | `MSTATUS <#MSTATUS>`_ | MRW | The mstatus register keeps track of and controls the hart's current operating state. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x301 | `MISA <#MISA>`_ | MRW | misa is a read-write register reporting the ISA supported by the hart. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x304 | `MIE <#MIE>`_ | MRW | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x305 | `MTVEC <#MTVEC>`_ | MRW | MXLEN-bit read/write register that holds trap vector configuration. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x310 | `MSTATUSH <#MSTATUSH>`_ | MRW | The mstatush register keeps track of and controls the hart’s current operating state. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x323-0x33f | `MHPMEVENT[3-31] <#MHPMEVENT[3-31]>`_ | MRW | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x340 | `MSCRATCH <#MSCRATCH>`_ | MRW | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x341 | `MEPC <#MEPC>`_ | MRW | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x342 | `MCAUSE <#MCAUSE>`_ | MRW | The mcause register stores the information regarding the trap. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x343 | `MTVAL <#MTVAL>`_ | MRW | The mtval is a warl register that holds the address of the instruction which caused the exception. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x344 | `MIP <#MIP>`_ | MRW | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x3a0-0x3a3 | `PMPCFG[0-3] <#PMPCFG[0-3]>`_ | MRW | PMP configuration register | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x3b0-0x3bf | `PMPADDR[0-15] <#PMPADDR[0-15]>`_ | MRW | Physical memory protection address register | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x7c0 | `ICACHE <#ICACHE>`_ | MRW | the register controls the operation of the i-cache unit. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0x7c1 | `DCACHE <#DCACHE>`_ | MRW | the register controls the operation of the d-cache unit. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb00 | `MCYCLE <#MCYCLE>`_ | MRW | Counts the number of clock cycles executed from an arbitrary point in time. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb02 | `MINSTRET <#MINSTRET>`_ | MRW | Counts the number of instructions completed from an arbitrary point in time. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb03-0xb1f | `MHPMCOUNTER[3-31] <#MHPMCOUNTER[3-31]>`_ | MRW | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb80 | `MCYCLEH <#MCYCLEH>`_ | MRW | upper 32 bits of mcycle | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb82 | `MINSTRETH <#MINSTRETH>`_ | MRW | Upper 32 bits of minstret. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xb83-0xb9f | `MHPMCOUNTER[3-31]H <#MHPMCOUNTER[3-31]H>`_ | MRW | The mhpmcounterh returns the upper half word in RV32I systems. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xf11 | `MVENDORID <#MVENDORID>`_ | MRO | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xf12 | `MARCHID <#MARCHID>`_ | MRO | MXLEN-bit read-only register encoding the base microarchitecture of the hart. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xf13 | `MIMPID <#MIMPID>`_ | MRO | Provides a unique encoding of the version of the processor implementation. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xf14 | `MHARTID <#MHARTID>`_ | MRO | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ +| 0xf15 | `MCONFIGPTR <#MCONFIGPTR>`_ | MRO | MXLEN-bit read-only register that holds the physical address of a configuration data structure. | ++-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+ Register Description -------------------- + +.. .. _MSTATUS::: MSTATUS -------- +~~~~~~~ :Address: 0x300 :Reset Value: 0x00001800 @@ -112,7 +118,7 @@ MSTATUS +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ | 2 | RESERVED_2 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 3 | MIE | 0x0 | WLRL | 0 - 1 | Stores the state of the machine mode interrupts. | +| 3 | MIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ | 4 | UPIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts prior to the trap. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ @@ -120,7 +126,7 @@ MSTATUS +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ | 6 | UBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for user mode | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ -| 7 | MPIE | 0x0 | WLRL | 0 - 1 | Stores the state of the machine mode interrupts prior to the trap. | +| 7 | MPIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts prior to the trap. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ | 8 | SPP | 0x0 | ROCST | 0x0 | Stores the previous priority mode for supervisor. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ @@ -151,8 +157,10 @@ MSTATUS | 31 | SD | 0x0 | ROCST | 0x0 | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. | +---------+--------------+---------------+--------+----------------+-----------------------------------------------------------------------------------------------------------------+ + +.. .. _MISA::: MISA ----- +~~~~ :Address: 0x301 :Reset Value: 0x40001106 @@ -170,8 +178,10 @@ MISA | [31:30] | MXL | 0x1 | WARL | 0x1 | Encodes the native base integer ISA width. | +---------+--------------+---------------+--------+----------------+------------------------------------------------------------------------------------------------+ + +.. .. _MIE::: MIE ---- +~~~ :Address: 0x304 :Reset Value: 0x00000000 @@ -196,7 +206,7 @@ MIE +---------+--------------+---------------+--------+----------------+---------------------------------------+ | 6 | VSTIE | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 7 | MTIE | 0x0 | WLRL | 0 - 1 | Machine Timer Interrupt enable. | +| 7 | MTIE | 0x0 | ROVAR | 0x0 - 0x1 | Machine Timer Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ | 8 | UEIE | 0x0 | ROCST | 0x0 | User External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ @@ -204,15 +214,17 @@ MIE +---------+--------------+---------------+--------+----------------+---------------------------------------+ | 10 | VSEIE | 0x0 | ROCST | 0x0 | VS-level External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ -| 11 | MEIE | 0x0 | WLRL | 0 - 1 | Machine External Interrupt enable. | +| 11 | MEIE | 0x0 | ROVAR | 0x0 - 0x1 | Machine External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ | 12 | SGEIE | 0x0 | ROCST | 0x0 | HS-level External Interrupt enable. | +---------+--------------+---------------+--------+----------------+---------------------------------------+ | [31:13] | RESERVED_13 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+---------------------------------------+ + +.. .. _MTVEC::: MTVEC ------ +~~~~~ :Address: 0x305 :Reset Value: 0x80010000 @@ -228,8 +240,10 @@ MTVEC | [31:2] | BASE | 0x20004000 | WARL | 0x00000000 - 0x3FFFFFFF | Vector base address. | +--------+--------------+---------------+--------+-------------------------+----------------------+ + +.. .. _MSTATUSH::: MSTATUSH --------- +~~~~~~~~ :Address: 0x310 :Reset Value: 0x00000000 @@ -257,8 +271,10 @@ MSTATUSH | [31:10] | RESERVED_10 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------+ + +.. .. _MHPMEVENT[3-31]::: MHPMEVENT[3-31] ---------------- +~~~~~~~~~~~~~~~ :Address: 0x323-0x33f :Reset Value: 0x00000000 @@ -272,8 +288,10 @@ MHPMEVENT[3-31] | [31:0] | MHPMEVENT[I] | 0x00000000 | ROCST | 0x00000000 | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. | +--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------+ + +.. .. _MSCRATCH::: MSCRATCH --------- +~~~~~~~~ :Address: 0x340 :Reset Value: 0x00000000 @@ -287,8 +305,10 @@ MSCRATCH | [31:0] | MSCRATCH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. | +--------+--------------+---------------+--------+-------------------------+----------------------------------------------------------------------------------------------+ + +.. .. _MEPC::: MEPC ----- +~~~~ :Address: 0x341 :Reset Value: 0x00000000 @@ -302,8 +322,10 @@ MEPC | [31:0] | MEPC | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. | +--------+--------------+---------------+--------+-------------------------+-------------------------------------------------------------------------------------------------+ + +.. .. _MCAUSE::: MCAUSE ------- +~~~~~~ :Address: 0x342 :Reset Value: 0x00000000 @@ -319,8 +341,10 @@ MCAUSE | 31 | INTERRUPT | 0x0 | WLRL | 0x0 - 0x1 | Indicates whether the trap was due to an interrupt. | +--------+----------------+---------------+--------+----------------+-----------------------------------------------------+ + +.. .. _MTVAL::: MTVAL ------ +~~~~~ :Address: 0x343 :Reset Value: 0x00000000 @@ -334,8 +358,10 @@ MTVAL | [31:0] | MTVAL | 0x00000000 | ROCST | 0x00000000 | The mtval is a warl register that holds the address of the instruction which caused the exception. | +--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------------+ + +.. .. _MIP::: MIP ---- +~~~ :Address: 0x344 :Reset Value: 0x00000000 @@ -360,7 +386,7 @@ MIP +---------+--------------+---------------+--------+----------------+----------------------------------------+ | 6 | VSTIP | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 7 | MTIP | 0x0 | ROVAR | 0 - 1 | Machine Timer Interrupt Pending. | +| 7 | MTIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine Timer Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ | 8 | UEIP | 0x0 | ROCST | 0x0 | User External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ @@ -368,15 +394,17 @@ MIP +---------+--------------+---------------+--------+----------------+----------------------------------------+ | 10 | VSEIP | 0x0 | ROCST | 0x0 | VS-level External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ -| 11 | MEIP | 0x0 | ROVAR | 0 - 1 | Machine External Interrupt Pending. | +| 11 | MEIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ | 12 | SGEIP | 0x0 | ROCST | 0x0 | HS-level External Interrupt Pending. | +---------+--------------+---------------+--------+----------------+----------------------------------------+ | [31:13] | RESERVED_13 | 0x0 | WPRI | | *Reserved* | +---------+--------------+---------------+--------+----------------+----------------------------------------+ + +.. .. _PMPCFG[0-3]::: PMPCFG[0-3] ------------ +~~~~~~~~~~~ :Address: 0x3a0-0x3a3 :Reset Value: 0x00000000 @@ -395,8 +423,10 @@ PMPCFG[0-3] | [31:24] | PMP[I*4 + 3]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits | +---------+-----------------+---------------+--------+----------------+------------------------+ + +.. .. _PMPADDR[0-15]::: PMPADDR[0-15] -------------- +~~~~~~~~~~~~~ :Address: 0x3b0-0x3bf :Reset Value: 0x00000000 @@ -409,8 +439,46 @@ PMPADDR[0-15] | [31:0] | PMPADDR[I] | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register | +--------+--------------+---------------+--------+-------------------------+---------------------------------------------+ + +.. .. _ICACHE::: +ICACHE +~~~~~~ + +:Address: 0x7c0 +:Reset Value: 0x00000001 +:Privilege: MRW +:Description: the register controls the operation of the i-cache unit. + ++--------+--------------+---------------+--------+----------------+-------------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+================+===========================================+ +| 0 | ICACHE | 0x1 | RW | 0x1 | bit for cache-enable of instruction cache | ++--------+--------------+---------------+--------+----------------+-------------------------------------------+ +| [31:1] | RESERVED_1 | 0x0 | WPRI | | *Reserved* | ++--------+--------------+---------------+--------+----------------+-------------------------------------------+ + + +.. .. _DCACHE::: +DCACHE +~~~~~~ + +:Address: 0x7c1 +:Reset Value: 0x00000001 +:Privilege: MRW +:Description: the register controls the operation of the d-cache unit. + ++--------+--------------+---------------+--------+----------------+------------------------------------+ +| Bits | Field Name | Reset Value | Type | Legal Values | Description | ++========+==============+===============+========+================+====================================+ +| 0 | DCACHE | 0x1 | RW | 0x1 | bit for cache-enable of data cache | ++--------+--------------+---------------+--------+----------------+------------------------------------+ +| [31:1] | RESERVED_1 | 0x0 | WPRI | | *Reserved* | ++--------+--------------+---------------+--------+----------------+------------------------------------+ + + +.. .. _MCYCLE::: MCYCLE ------- +~~~~~~ :Address: 0xb00 :Reset Value: 0x00000000 @@ -424,8 +492,10 @@ MCYCLE | [31:0] | MCYCLE | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of clock cycles executed from an arbitrary point in time. | +--------+--------------+---------------+--------+-------------------------+-----------------------------------------------------------------------------+ + +.. .. _MINSTRET::: MINSTRET --------- +~~~~~~~~ :Address: 0xb02 :Reset Value: 0x00000000 @@ -439,8 +509,10 @@ MINSTRET | [31:0] | MINSTRET | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of instructions completed from an arbitrary point in time. | +--------+--------------+---------------+--------+-------------------------+------------------------------------------------------------------------------+ + +.. .. _MHPMCOUNTER[3-31]::: MHPMCOUNTER[3-31] ------------------ +~~~~~~~~~~~~~~~~~ :Address: 0xb03-0xb1f :Reset Value: 0x00000000 @@ -454,8 +526,10 @@ MHPMCOUNTER[3-31] | [31:0] | MHPMCOUNTER[I] | 0x00000000 | ROCST | 0x00000000 | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. | +--------+----------------+---------------+--------+----------------+---------------------------------------------------------------------------+ + +.. .. _MCYCLEH::: MCYCLEH -------- +~~~~~~~ :Address: 0xb80 :Reset Value: 0x00000000 @@ -468,8 +542,10 @@ MCYCLEH | [31:0] | MCYCLEH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | upper 32 bits of mcycle | +--------+--------------+---------------+--------+-------------------------+-------------------------+ + +.. .. _MINSTRETH::: MINSTRETH ---------- +~~~~~~~~~ :Address: 0xb82 :Reset Value: 0x00000000 @@ -482,8 +558,10 @@ MINSTRETH | [31:0] | MINSTRETH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Upper 32 bits of minstret. | +--------+--------------+---------------+--------+-------------------------+----------------------------+ + +.. .. _MHPMCOUNTER[3-31]H::: MHPMCOUNTER[3-31]H ------------------- +~~~~~~~~~~~~~~~~~~ :Address: 0xb83-0xb9f :Reset Value: 0x00000000 @@ -497,8 +575,10 @@ MHPMCOUNTER[3-31]H | [31:0] | MHPMCOUNTER[I]H | 0x00000000 | ROCST | 0x00000000 | The mhpmcounterh returns the upper half word in RV32I systems. | +--------+-----------------+---------------+--------+----------------+----------------------------------------------------------------+ + +.. .. _MVENDORID::: MVENDORID ---------- +~~~~~~~~~ :Address: 0xf11 :Reset Value: 0x00000602 @@ -512,8 +592,10 @@ MVENDORID | [31:0] | MVENDORID | 0x00000602 | ROCST | 0x00000602 | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. | +--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------------------------+ + +.. .. _MARCHID::: MARCHID -------- +~~~~~~~ :Address: 0xf12 :Reset Value: 0x00000003 @@ -527,8 +609,10 @@ MARCHID | [31:0] | MARCHID | 0x00000003 | ROCST | 0x00000003 | MXLEN-bit read-only register encoding the base microarchitecture of the hart. | +--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------+ + +.. .. _MIMPID::: MIMPID ------- +~~~~~~ :Address: 0xf13 :Reset Value: 0x00000000 @@ -542,8 +626,10 @@ MIMPID | [31:0] | MIMPID | 0x00000000 | ROCST | 0x00000000 | Provides a unique encoding of the version of the processor implementation. | +--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------+ + +.. .. _MHARTID::: MHARTID -------- +~~~~~~~ :Address: 0xf14 :Reset Value: 0x00000000 @@ -557,8 +643,10 @@ MHARTID | [31:0] | MHARTID | 0x00000000 | ROCST | 0x00000000 | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. | +--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------------------------+ + +.. .. _MCONFIGPTR::: MCONFIGPTR ----------- +~~~~~~~~~~ :Address: 0xf15 :Reset Value: 0x00000000 diff --git a/config/gen_from_riscv_config/scripts/libs/csr_updater.py b/config/gen_from_riscv_config/scripts/libs/csr_updater.py index 08e05b048..5a0b21299 100644 --- a/config/gen_from_riscv_config/scripts/libs/csr_updater.py +++ b/config/gen_from_riscv_config/scripts/libs/csr_updater.py @@ -25,18 +25,22 @@ def csr_recursive_update(original_dict, csr_update): original_dict[key] = value -def csr_formatter(srcfile, modifile): +def csr_formatter(srcfile, customfile, modifile): # Read original dictionary from YAML source file with open(srcfile, "r", encoding="utf-8") as file: original_dict = yaml.safe_load(file) - + with open(customfile, "r", encoding="utf-8") as file: + custom_dict = yaml.safe_load(file) + + isa_data = original_dict.copy() + isa_data['hart0'].update(custom_dict["hart0"]) updated_values = {} if modifile is not None: with open(modifile, "r", encoding="utf-8") as file: updated_values = yaml.safe_load(file) # Update original_dict with values from updated_values recursively - csr_recursive_update(original_dict["hart0"], updated_values) + csr_recursive_update(isa_data["hart0"], updated_values) # Identify and remove keys within the range specified for each register keys_to_remove = [] @@ -71,12 +75,12 @@ def csr_formatter(srcfile, modifile): for k in keys_to_remove: dictionary.pop(k) - remove_keys_recursive(original_dict["hart0"]) - remove_keys_recursive(original_dict["hart0"]) + remove_keys_recursive(isa_data["hart0"]) + remove_keys_recursive(isa_data["hart0"]) # Remove keys from original_dict for k in keys_to_remove: - original_dict["hart0"].pop(k, None) + isa_data["hart0"].pop(k, None) # Remove keys from original_dict for k in keys_to_remove: - original_dict.pop(k, None) - return original_dict + isa_data.pop(k, None) + return isa_data diff --git a/config/gen_from_riscv_config/scripts/libs/utils.py b/config/gen_from_riscv_config/scripts/libs/utils.py index 5bbe9b1a3..8348cd277 100644 --- a/config/gen_from_riscv_config/scripts/libs/utils.py +++ b/config/gen_from_riscv_config/scripts/libs/utils.py @@ -31,7 +31,7 @@ from libs.csr_updater import csr_formatter from libs.csr_factorizer import factorizer pattern_warl = ( - r"\b(?:warl|wlrl|ro_constant|ro_variable)\b" # pattern to detect warl in field + r"\b(?:warl|wlrl|ro_constant|ro_variable|rw|ro)\b" # pattern to detect warl in field ) pattern_legal_dict = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is dict pattern_legal_list = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is a list @@ -262,7 +262,7 @@ class RstAddressBlock(AddressBlockClass): def returnAsString(self): registerlist = sorted(self.registerList, key=lambda reg: reg.address) r = RstCloth(io.StringIO()) # with default parameter, sys.stdout is used - regNameList = [reg.name for reg in registerlist] + regNameList = [reg.name.upper() for reg in registerlist] regAddressList = [reg.address for reg in registerlist] regPrivModeList = [reg.access for reg in registerlist] regPrivAccessList = [self.get_access_privilege(reg) for reg in registerlist] @@ -328,7 +328,7 @@ This allows to clearly represent read-write registers holding a single legal val summary_table.append( [ regAddressList[i], - str(regNameList[i]).upper() + "_", + f"`{regNameList[i]} <#{regNameList[i]}>`_", # RW or RO privileges are set in the official RISC-V specification # and are encoded in bits [11:10] of the reg's address (2'b11 == "RO"). # See Tables 4 through 8 in section 2.2 of the Priv spec v20240411. @@ -345,7 +345,9 @@ This allows to clearly represent read-write registers holding a single legal val for reg in registerlist: if reg.RV32 | reg.RV64: reg_table = [] - r.h2(reg.name.upper()) + r.newline() + r.directive(".. _" + reg.name.upper() + ":") + r.h3(reg.name.upper()) r.newline() r.field("Address", (reg.address)) if reg.resetValue: @@ -670,8 +672,9 @@ class MdAddressBlock(AddressBlockClass): class CsrParser: """parse CSR RISC-V config yaml file""" - def __init__(self, srcFile, target, modiFile=None): + def __init__(self, srcFile,customFile, target, modiFile=None): self.srcFile = srcFile + self.customFile = customFile self.modiFile = modiFile self.target = target @@ -947,7 +950,7 @@ class CsrParser: def returnDocument(self): with open(self.srcFile, "r", encoding="utf-8") as f: data = yaml.safe_load(f) - data = csr_formatter(self.srcFile, self.modiFile) + data = csr_formatter(self.srcFile,self.customFile, self.modiFile) Registers = factorizer(data) docName = data["hart0"] d = DocumentClass(docName) diff --git a/config/gen_from_riscv_config/scripts/riscv_config_gen.py b/config/gen_from_riscv_config/scripts/riscv_config_gen.py index f8507bc03..78cd82263 100644 --- a/config/gen_from_riscv_config/scripts/riscv_config_gen.py +++ b/config/gen_from_riscv_config/scripts/riscv_config_gen.py @@ -29,7 +29,8 @@ from libs.utils import InstmdBlock if __name__ == "__main__": parser = argparse.ArgumentParser(description="GEN From RISC-V Config") - parser.add_argument("-s", "--srcFile", help="yaml input file") + parser.add_argument("-s", "--srcFile", help="isa_gen yaml input file") + parser.add_argument("-c", "--customFile", help=" custom_gen yaml input file") parser.add_argument("-d", "--destDir", help="write generated file to dir") parser.add_argument("-m", "--modif", help="ISA /CSR Formatter if exist") parser.add_argument("-i", "--temp", help="Full ISA /SPIKETemplate") @@ -47,7 +48,7 @@ if __name__ == "__main__": spike_generator = SpikeGenerator(args.target, args.temp, args.modif) spike_generator.generateSpike(document) else: - e = CsrParser(args.srcFile, args.target, args.modif) + e = CsrParser(args.srcFile, args.customFile, args.target, args.modif) document = e.returnDocument() generator = CsrGenerator(args.target) generator.generateCSR(RstAddressBlock, document) diff --git a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml index fd9092025..129ab5317 100644 --- a/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml +++ b/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml @@ -8,12 +8,31 @@ mip: meip: type: ro_variable: - - 0:1 + - 0x0:0x1 mtip: type: ro_variable: - - 0:1 - + - 0x0:0x1 +mie: + rv32: + meie: + type: + ro_variable: + - 0x0:0x1 + mtie: + type: + ro_variable: + - 0x0:0x1 +mstatus : + rv32 : + mie : + type : + wlrl: + - 0x0:0x1 + mpie : + type: + wlrl: + - 0x0:0x1 # Exclude mode exclude : key : priv_mode