diff --git a/src/mult.sv b/src/mult.sv
index 3d0215afb..dc9d11d28 100644
--- a/src/mult.sv
+++ b/src/mult.sv
@@ -39,6 +39,7 @@ module mult
     // ----------------
     // Mock Multiplier
     // ----------------
+    `ifndef SYNTHESIS
     assign mult_valid_o = mult_valid_i;
     assign mult_trans_id_o = trans_id_i;
     assign mult_ready_o = 1'b1;
@@ -55,11 +56,20 @@ module mult
                 result_o = mult_result[63:0];
             end
 
-            MULH:;
+            MULH: begin
+                mult_result = $signed(operand_a_i) * $signed(operand_b_i);
+                result_o = mult_result[127:64];
+            end
 
-            MULHU:;
+            MULHU: begin
+                mult_result = operand_a_i * operand_b_i;
+                result_o = mult_result[127:64];
+            end
 
-            MULHSU:;
+            MULHSU: begin
+                mult_result = $signed(operand_a_i) * $unsigned(operand_b_i);
+                result_o = mult_result[127:64];
+            end
 
             MULW:;
 
@@ -81,79 +91,5 @@ module mult
             REMUW:;
         endcase
     end
-    // // MUL and MULH is a two cycle instructions
-    // logic signed [63:0]  result_mult;
-    // logic signed [63:0]  result_multh;
-    // enum logic {FIRST_CYCLE, SECOND_CYCLE} multCS, multNS;
-    // logic [TRANS_ID_BITS-1:0] mult_trans_q, mult_trans_n;
-
-    // assign mult_trans_id_o = mult_trans_q;
-    // assign result_o        = is_low_part_i ? result_mult : result_multh;
-
-    // mult_datapath
-    // mult_dp
-    //     (
-    //         .operand_a_i    (operand_a_i  ),
-    //         .operand_b_i    (operand_b_i  ),
-    //         .sign_a_i       (sign_a_i     ),
-    //         .sign_b_i       (sign_b_i     ),
-    //         .result_low_o   (result_mult  ),
-    //         .result_high_o  (result_multh )
-    //     );
-
-    // always_comb begin
-    //     mult_valid_o = 1'b0;
-    //     mult_ready_o = 1'b0;
-    //     multNS       = multCS;
-    //     mult_trans_n = mult_trans_q;
-    //     unique case (multCS)
-    //         FIRST_CYCLE: begin
-    //             mult_valid_o = 1'b0;
-    //             mult_ready_o = 1'b0;
-    //             multNS       = mult_valid_i ? SECOND_CYCLE : multCS;
-    //         end
-    //         SECOND_CYCLE: begin
-    //             multNS       = FIRST_CYCLE;
-    //             mult_valid_o = 1'b1;
-    //             mult_ready_o = 1'b1;
-    //         end
-    //         default:;
-    //     endcase
-    // end
-
-    // always_ff @(posedge clk_i or negedge rst_ni) begin
-    //     if(~rst_ni) begin
-    //         multCS <= FIRST_CYCLE;
-    //     end else begin
-    //         multCS       <= multNS;
-    //         mult_trans_n <= mult_trans_q;
-    //     end
-    // end
-
-    // Check if we need sign extension
-
+    `endif
 endmodule
-
-// module mult_datapath
-// (
-//     input  logic [63:0]              operand_a_i,
-//     input  logic [63:0]              operand_b_i,
-//     input  logic                     sign_a_i,
-//     input  logic                     sign_b_i,
-//     output logic [63:0]              result_low_o,
-//     output logic [63:0]              result_high_o
-// );
-
-//     logic signed [129:0] mult_result;
-//     logic signed [64:0]  operand_a_ext;
-//     logic signed [64:0]  operand_b_ext;
-
-//     assign operand_a_ext  = $signed({sign_a_i & operand_a_i[63], operand_a_i});
-//     assign operand_b_ext  = $signed({sign_b_i & operand_b_i[63], operand_b_i});
-
-//     assign mult_result    = operand_a_ext * operand_b_ext;
-
-//     assign result_low_o   = $signed(mult_result[ 63: 0]);
-//     assign result_high_o  = $signed(mult_result[127:64]);
-
-// endmodule