diff --git a/core/commit_stage.sv b/core/commit_stage.sv
index 3381ac34a..1c80a51d9 100644
--- a/core/commit_stage.sv
+++ b/core/commit_stage.sv
@@ -148,7 +148,7 @@ module commit_stage
     // we will not commit the instruction if we took an exception
     // and we do not commit the instruction if we requested a halt
     if (commit_instr_i[0].valid && !commit_instr_i[0].ex.valid && !halt_i) begin
-      if (commit_instr_i[0].is_macro_instr && commit_instr_i[0].is_last_macro_instr)
+      if (CVA6Cfg.RVZCMP && commit_instr_i[0].is_macro_instr && commit_instr_i[0].is_last_macro_instr)
         commit_macro_ack[0] = 1'b1;
       else commit_macro_ack[0] = 1'b0;
       // we can definitely write the register file
@@ -292,7 +292,9 @@ module commit_stage
         end
       end
     end
-    commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
+    if (CVA6Cfg.RVZCMP)
+      commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
+    else commit_macro_ack_o = commit_ack_o;
   end
 
   // -----------------------------