From f0adb7680b44b3f3f44f82c6a1f6bb14fed4f9cf Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Mon, 27 May 2024 18:02:40 +0200 Subject: [PATCH] Update the specification following the last commits (RVF, SUPERSCALAR,...) (#2155) --- .../source/parameters_cv32a65x.rst | 54 +++++++++++++++++-- .../source/port_frontend.rst | 6 +-- .../source/port_id_stage.rst | 16 +++--- .../source/port_instr_queue.rst | 6 +-- .../source/port_issue_stage.rst | 10 ++-- .../source/port_scoreboard.rst | 20 +++---- 6 files changed, 77 insertions(+), 35 deletions(-) diff --git a/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst b/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst index a2958961a..91c64d617 100644 --- a/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst +++ b/docs/04_cv32a65x_design/source/parameters_cv32a65x.rst @@ -52,7 +52,11 @@ - Zicond RISC-V extension - False - * - FpuEn + * - RVF + - Floating Point + - False + + * - RVD - Floating Point - False @@ -72,6 +76,14 @@ - Non standard Vector Floating Point extension - False + * - PerfCounterEn + - Perf counters + - False + + * - MmuPresent + - MMU + - False + * - RVS - Supervisor mode - False @@ -182,7 +194,7 @@ * - MemTidWidth - TODO - - 2 + - 4 * - IcacheByteSize - Instruction cache size (in bytes) @@ -196,6 +208,14 @@ - Instruction cache line width - 128 + * - DCacheType + - Cache Type + - config_pkg::HPDCACHE + + * - DcacheIdWidth + - Data cache ID + - 1 + * - DcacheByteSize - Data cache size (in bytes) - 32768 @@ -212,6 +232,10 @@ - User field on data bus enable - 0 + * - WtDcacheWbufDepth + - Write-through data cache write buffer depth + - 2 + * - FetchUserEn - User field on fetch bus enable - 0 @@ -228,13 +252,21 @@ - Number of commit ports - 1 + * - NrLoadPipeRegs + - Load cycle latency number + - 0 + + * - NrStorePipeRegs + - Store cycle latency number + - 0 + * - NrScoreboardEntries - Scoreboard length - 4 * - NrLoadBufEntries - Load buffer entry buffer - - 1 + - 2 * - MaxOutstandingStores - Maximum number of outstanding stores @@ -251,3 +283,19 @@ * - BHTEntries - Branch history entries - 32 + + * - InstrTlbEntries + - MMU instruction TLB entries + - 2 + + * - DataTlbEntries + - MMU data TLB entries + - 2 + + * - UseSharedTlb + - MMU option to use shared TLB + - True + + * - SharedTlbDepth + - MMU depth of shared TLB + - 64 diff --git a/docs/04_cv32a65x_design/source/port_frontend.rst b/docs/04_cv32a65x_design/source/port_frontend.rst index d4477323d..f92b71fdb 100644 --- a/docs/04_cv32a65x_design/source/port_frontend.rst +++ b/docs/04_cv32a65x_design/source/port_frontend.rst @@ -106,19 +106,19 @@ - out - Handshake's data between fetch and decode - ID_STAGE - - fetch_entry_t + - fetch_entry_t[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_valid_o`` - out - Handshake's valid between fetch and decode - ID_STAGE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_ready_i`` - in - Handshake's ready between fetch and decode - ID_STAGE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_id_stage.rst b/docs/04_cv32a65x_design/source/port_id_stage.rst index f51e91417..687850512 100644 --- a/docs/04_cv32a65x_design/source/port_id_stage.rst +++ b/docs/04_cv32a65x_design/source/port_id_stage.rst @@ -40,49 +40,49 @@ - in - Handshake's data between fetch and decode - FRONTEND - - fetch_entry_t + - fetch_entry_t[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_valid_i`` - in - Handshake's valid between fetch and decode - FRONTEND - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_ready_o`` - out - Handshake's ready between fetch and decode - FRONTEND - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``issue_entry_o`` - out - Handshake's data between decode and issue - ISSUE - - scoreboard_entry_t + - scoreboard_entry_t[ariane_pkg::SUPERSCALAR:0] * - ``orig_instr_o`` - out - Instruction value - ISSUE - - logic[31:0] + - logic[ariane_pkg::SUPERSCALAR:0][31:0] * - ``issue_entry_valid_o`` - out - Handshake's valid between decode and issue - ISSUE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``is_ctrl_flow_o`` - out - Report if instruction is a control flow instruction - ISSUE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``issue_instr_ack_i`` - in - Handshake's acknowlege between decode and issue - ISSUE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``irq_i`` - in diff --git a/docs/04_cv32a65x_design/source/port_instr_queue.rst b/docs/04_cv32a65x_design/source/port_instr_queue.rst index bb932a9d6..b5a73da1a 100644 --- a/docs/04_cv32a65x_design/source/port_instr_queue.rst +++ b/docs/04_cv32a65x_design/source/port_instr_queue.rst @@ -106,19 +106,19 @@ - out - Handshake’s data with ID_STAGE - ID_STAGE - - fetch_entry_t + - fetch_entry_t[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_valid_o`` - out - Handshake’s valid with ID_STAGE - ID_STAGE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``fetch_entry_ready_i`` - in - Handshake’s ready with ID_STAGE - ID_STAGE - - logic + - logic[ariane_pkg::SUPERSCALAR:0] Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below diff --git a/docs/04_cv32a65x_design/source/port_issue_stage.rst b/docs/04_cv32a65x_design/source/port_issue_stage.rst index d7dd9bf2a..0fa740fd3 100644 --- a/docs/04_cv32a65x_design/source/port_issue_stage.rst +++ b/docs/04_cv32a65x_design/source/port_issue_stage.rst @@ -46,31 +46,31 @@ - in - Handshake's data with decode stage - ID_STAGE - - scoreboard_entry_t + - scoreboard_entry_t[SUPERSCALAR:0] * - ``orig_instr_i`` - in - instruction value - ID_STAGE - - logic[31:0] + - logic[SUPERSCALAR:0][31:0] * - ``decoded_instr_valid_i`` - in - Handshake's valid with decode stage - ID_STAGE - - logic + - logic[SUPERSCALAR:0] * - ``is_ctrl_flow_i`` - in - Is instruction a control flow instruction - ID_STAGE - - logic + - logic[SUPERSCALAR:0] * - ``decoded_instr_ack_o`` - out - Handshake's acknowlege with decode stage - ID_STAGE - - logic + - logic[SUPERSCALAR:0] * - ``rs1_forwarding_o`` - out diff --git a/docs/04_cv32a65x_design/source/port_scoreboard.rst b/docs/04_cv32a65x_design/source/port_scoreboard.rst index 0959761cb..aa3b2bf47 100644 --- a/docs/04_cv32a65x_design/source/port_scoreboard.rst +++ b/docs/04_cv32a65x_design/source/port_scoreboard.rst @@ -48,12 +48,6 @@ - TO_BE_COMPLETED - logic - * - ``unresolved_branch_i`` - - in - - We have an unresolved branch - - TO_BE_COMPLETED - - logic - * - ``rd_clobber_gpr_o`` - out - TO_BE_COMPLETED @@ -136,43 +130,43 @@ - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - scoreboard_entry_t + - scoreboard_entry_t[ariane_pkg::SUPERSCALAR:0] * - ``orig_instr_i`` - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic[31:0] + - logic[ariane_pkg::SUPERSCALAR:0][31:0] * - ``decoded_instr_valid_i`` - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``decoded_instr_ack_o`` - out - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``orig_instr_o`` - out - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic[31:0] + - logic[ariane_pkg::SUPERSCALAR:0][31:0] * - ``issue_instr_valid_o`` - out - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``issue_ack_i`` - in - TO_BE_COMPLETED - TO_BE_COMPLETED - - logic + - logic[ariane_pkg::SUPERSCALAR:0] * - ``resolved_branch_i`` - in