diff --git a/src/regfile_ff.sv b/src/regfile_ff.sv
index b33ae937c..f0cdf74ba 100644
--- a/src/regfile_ff.sv
+++ b/src/regfile_ff.sv
@@ -26,7 +26,7 @@
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
 
-module regfile_ff
+module regfile
 #(
   parameter DATA_WIDTH    = 32
 )
@@ -97,4 +97,4 @@ module regfile_ff
   assign rdata_a_o = rf_reg[raddr_a_i];
   assign rdata_b_o = rf_reg[raddr_b_i];
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src_files.yml b/src_files.yml
index 903b20235..0690382a5 100644
--- a/src_files.yml
+++ b/src_files.yml
@@ -32,10 +32,29 @@ ariane:
     src/mult.sv,
     src/pcgen_stage.sv,
     src/ptw.sv,
-    src/regfile.sv,
     src/scoreboard.sv,
     src/store_buffer.sv,
     src/store_unit.sv,
     src/tlb.sv
     ]
+riscv_regfile_rtl:
+  targets: [
+    rtl,
+  ]
+  incdirs: [
+    include,
+  ]
+  files: [
+    src/regfile.sv,
+  ]
 
+riscv_regfile_fpga:
+  targets: [
+    xilinx,
+  ]
+  incdirs: [
+    include,
+  ]
+  files: [
+    src/regfile_ff.sv,
+  ]