diff --git a/verif/docs/VerifPlans/AXI/VP_IP005.yml b/verif/docs/VerifPlans/AXI/VP_IP005.yml index 05353b025..add6db6c5 100644 --- a/verif/docs/VerifPlans/AXI/VP_IP005.yml +++ b/verif/docs/VerifPlans/AXI/VP_IP005.yml @@ -7,7 +7,7 @@ subfeatures: !!omap - 000_Control_Signals: !Subfeature name: 000_Control_Signals tag: VP_IP005_P000 - next_elt_id: 12 + next_elt_id: 16 display_order: 0 items: !!omap - '000': !VerifItem @@ -20,28 +20,28 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxBURST == 0b01 is always true while AX_VALID is - asserted. + verif_goals: Ensure that AxBURST == 0b01 is always true while AxVALID is asserted. pfc: 4 test_type: 3 - cov_method: 2 + cov_method: 1 cores: 56 coverage_loc: '' comments: '' - '001': !VerifItem name: '001' tag: VP_1_F005_S000_I001 - description: All Read transaction performed by CVA6 are of burst lenght less - or equal to 2. ARLEN = 0b01 + description: All Read transaction performed by CVA6 are of burst length less + or equal to ICACHE_LINE_WIDTH/64. ARLEN = 0b01 or 0b00 reqt_doc: AXI Design doc - Address structure ref_mode: '' ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. + verif_goals: Ensure that ARLEN == 0b01 || ARLEN == 0b00 is always true while + ARVALID is asserted. pfc: 4 test_type: 3 - cov_method: 2 + cov_method: 1 cores: 56 coverage_loc: '' comments: '' @@ -55,10 +55,10 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. + verif_goals: Ensure that AWLEN == 0b00 is always true while AWVALID is asserted. pfc: 4 test_type: 3 - cov_method: 2 + cov_method: 1 cores: 56 coverage_loc: '' comments: '' @@ -73,32 +73,67 @@ subfeatures: !!omap ref_section: '' ref_viewer: '' verif_goals: Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while - AR_VALID is asserted. + ARVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 cores: 56 coverage_loc: '' comments: '' - - '007': !VerifItem - name: '007' - tag: VP_1_F005_S000_I007 - description: Exclusive access transactions cannot have a length greater than - 16 beats - reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) - ref_mode: '' + - '013': !VerifItem + name: '013' + tag: VP_AXI_F005_S000_I013 + description: The maximum value can be taken by AxSIZE is XLEN/8 + reqt_doc: '' + ref_mode: page ref_page: '' ref_section: '' - ref_viewer: '' - verif_goals: Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID - is asserted. - pfc: 4 - test_type: 3 - cov_method: 2 + ref_viewer: firefox + verif_goals: Ensure that AxSIZE <= clog2(XLEN/8) + pfc: -1 + test_type: 1 + cov_method: 1 cores: 56 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' + - '014': !VerifItem + name: '014' + tag: VP_AXI_F005_S000_I014 + description: "if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1, the maximum load + instruction size is 4 bytes\nARSIZE can not be equal to 0, 1 or 2 if ARLOCK + = 1" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Ensure that ARSIZE != 3 when ARID = 1 and ARLEN = 0\nEnsure + that ARSIZE != 0, 1 or 2 when ARID = 0\nEnsure that ARSIZE != 0, 1 or 2 + when ARLOCK = 1" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '015': !VerifItem + name: '015' + tag: VP_AXI_F005_S000_I015 + description: if(RVA) AxLOCK = 1 => AxSIZE > 1, CVA6 doesn't perform exclusive + transaction with size lower than 4 bytes + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Ensure that AWSIZE > 1 when AWLOCK = 1 + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP006.yml b/verif/docs/VerifPlans/AXI/VP_IP006.yml index 768ff9560..f38eaeca5 100644 --- a/verif/docs/VerifPlans/AXI/VP_IP006.yml +++ b/verif/docs/VerifPlans/AXI/VP_IP006.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 9 +next_elt_id: 10 name: Signals id: 6 display_order: 6 @@ -7,20 +7,22 @@ subfeatures: !!omap - 000_ID: !Subfeature name: 000_ID tag: VP_IP006_P000 - next_elt_id: 3 + next_elt_id: 4 display_order: 0 items: !!omap - '000': !VerifItem name: '000' tag: VP_1_F006_S000_I000 description: The CVA6 identify read transaction with an ID equal to 0 or 1 + for normal transaction, and 3 for exclusive transaction reqt_doc: AXI Design doc - Transaction Identifiers ref_mode: '' ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 is always true while - AR_VALID is asserted. + verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 || (ARID == 0b11 && + (Exclusive_Access || Atomic_transaction)) is always true while ARVALID is + asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -30,13 +32,15 @@ subfeatures: !!omap - '001': !VerifItem name: '001' tag: VP_1_F006_S000_I001 - description: The CVA6 identify write transaction with an ID equal to 1 + description: The CVA6 identify write transaction with an ID equal to 1 for + normal transaction, and 3 for exclusive transaction or atomic operations reqt_doc: AXI Design doc - Transaction Identifiers ref_mode: '' ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AWID == 0b01 is always true while AW_VALID is asserted. + verif_goals: Ensure that AWID == 0b01 || AWID == 0b11 && (Exclusive_Access + || Atomic_transaction) is always true while AWVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -59,7 +63,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. + verif_goals: Ensure that AxUSER = 0b00 is always true while AxVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -76,7 +80,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that BUSER = 0b00 is always true while B_VALID is asserted. + verif_goals: Ensure that BUSER = 0b00 is always true while BVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -98,7 +102,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. + verif_goals: Ensure that AxQOS = 0b0000 is always true while AxVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -114,13 +118,13 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_1_F006_S003_I000 - description: AxCACHE always take 0b0000. + description: AxCACHE always take 0b0010. reqt_doc: 'AXI Design Doc - Transaction Attributes: Memory types' ref_mode: '' ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxCACHE = 0b0000 is always true while AX_VALID is + verif_goals: Ensure that AxCACHE = 0b0010 is always true while AxVALID is asserted. pfc: 4 test_type: 3 @@ -143,7 +147,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. + verif_goals: Ensure that AxPROT = 0b000 is always true while AxVALID is asserted. pfc: 4 test_type: 3 cov_method: 2 @@ -165,7 +169,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Ensure that AxREGION = 0b0000 is always true while AX_VALID is + verif_goals: Ensure that AxREGION = 0b0000 is always true while AxVALID is asserted. pfc: 4 test_type: 3 @@ -173,7 +177,48 @@ subfeatures: !!omap cores: 56 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +- 009_Strob: !Subfeature + name: 009_Strob + tag: VP_AXI_F006_S009 + next_elt_id: 2 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_AXI_F006_S009_I000 + description: CVA6 does not performe unaligned memory accesses, therefore WSTRB + takes only combinations for aligned accesses + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Ensure that WSTRB does not take value different than 1, 2, 3, + 4, 8, 12, 15, 16, 32, 48, 64, 128, 192, 240 and 255 + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_AXI_F006_S009_I001 + description: If(RV32) WSTRB < 255, Since AWSIZE lower than 3, so the data + bus cannot have more than 4 valid byte lanes + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Ensure that WSTRB does not take 255 + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 24 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP007.yml b/verif/docs/VerifPlans/AXI/VP_IP007.yml index 202bd170b..4ec70f0e1 100644 --- a/verif/docs/VerifPlans/AXI/VP_IP007.yml +++ b/verif/docs/VerifPlans/AXI/VP_IP007.yml @@ -1,5 +1,5 @@ !Feature -next_elt_id: 1 +next_elt_id: 2 name: Clock and Reset id: 7 display_order: 7 @@ -58,7 +58,30 @@ subfeatures: !!omap cores: 56 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +- 001_Hard_Reset: !Subfeature + name: 001_Hard_Reset + tag: VP_AXI_F007_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_AXI_F007_S001_I000 + description: Random hard reset during simulation. + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Ensure that the CVA6 restarts the test from the start address + and does not crash after disabling the reset. + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP008.yml b/verif/docs/VerifPlans/AXI/VP_IP008.yml index 642c70531..ce5475ea4 100644 --- a/verif/docs/VerifPlans/AXI/VP_IP008.yml +++ b/verif/docs/VerifPlans/AXI/VP_IP008.yml @@ -61,10 +61,10 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: "Ensure that no errors are encountered as the testbench injects\ - \ random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY\ - \ is asserted on or after same cycle as ARVALID\nARREADY is asserted and\ - \ deasserted during an interval when ARVALID is de-asserted" + verif_goals: "Ensure that no errors are encountered as the testbench injects + random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY + is asserted on or after same cycle as ARVALID\nARREADY is asserted and deasserted + during an interval when ARVALID is de-asserted" pfc: 0 test_type: 3 cov_method: 1 @@ -81,13 +81,13 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: "Ensure that no errors are encountered as the testbench injects\ - \ random Ready-to-Valid delays. There are four cases to consider: \n \ - \ \nAWREADY is asserted on or after\ - \ same cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on\ - \ or after same cycle as WVALID and AWVALID is de-asserted\nAWREADY is\ - \ asserted on or after same cycle as AWVALID and WVALID\nAWREADY is asserted\ - \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + verif_goals: "Ensure that no errors are encountered as the testbench injects + random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nAWREADY is asserted on or after same + cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on or after + same cycle as WVALID and AWVALID is de-asserted\nAWREADY is asserted on + or after same cycle as AWVALID and WVALID\nAWREADY is asserted and deasserted + during an interval when AWVALID and WVALID is de-asserted" pfc: 0 test_type: 3 cov_method: 1 @@ -104,13 +104,13 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: "Ensure that no errors are encountered as the testbench injects\ - \ random Ready-to-Valid delays. There are four cases to consider: \n \ - \ \nWREADY is asserted on or\ - \ after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted\ - \ on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is\ - \ asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted\ - \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + verif_goals: "Ensure that no errors are encountered as the testbench injects + random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nWREADY is asserted on or + after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted + on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is + asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted + and deasserted during an interval when AWVALID and WVALID is de-asserted" pfc: 0 test_type: 3 cov_method: 1 @@ -135,7 +135,7 @@ subfeatures: !!omap cores: 56 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP009.yml b/verif/docs/VerifPlans/AXI/VP_IP009.yml new file mode 100644 index 000000000..8c327aef9 --- /dev/null +++ b/verif/docs/VerifPlans/AXI/VP_IP009.yml @@ -0,0 +1,33 @@ +!Feature +next_elt_id: 2 +name: Error Injection +id: 9 +display_order: 9 +subfeatures: !!omap +- 000_Protocol errors: !Subfeature + name: 000_Protocol errors + tag: VP_AXI_F009_S000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '003': !VerifItem + name: '003' + tag: VP_AXI_F009_S000_I003 + description: Injection error by randomizing resp signal. + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Randomize xRESP signals. The CVA6 shouldn’t crash if RESP signal + indicate an error in a transaction. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/runme.sh b/verif/docs/VerifPlans/AXI/runme.sh index 6d283b80b..bf7e7f285 100644 --- a/verif/docs/VerifPlans/AXI/runme.sh +++ b/verif/docs/VerifPlans/AXI/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -sh $ROOTDIR/../../../../verif/core-v-verif/tools/vptool/vptool.sh $* +sh $ROOTDIR/../../../core-v-verif/tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/source/dvplan_AXI.md b/verif/docs/VerifPlans/source/dvplan_AXI.md index a7399eca0..1e6b422e3 100644 --- a/verif/docs/VerifPlans/source/dvplan_AXI.md +++ b/verif/docs/VerifPlans/source/dvplan_AXI.md @@ -12,10 +12,10 @@ All transaction performed by CVA6 are of type INCR. AxBURST = 0b01 * **Verification Goals** - Ensure that AxBURST == 0b01 is always true while AX_VALID is asserted. + Ensure that AxBURST == 0b01 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random -* **Coverage Method:** Assertion Coverage +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 * **Unique verification tag:** VP_1_F005_S000_I000 * **Link to Coverage:** @@ -28,13 +28,13 @@ * **Requirement location:** AXI Design doc - Address structure * **Feature Description** - All Read transaction performed by CVA6 are of burst lenght less or equal to 2. ARLEN = 0b01 + All Read transaction performed by CVA6 are of burst length less or equal to ICACHE_LINE_WIDTH/64. ARLEN = 0b01 or 0b00 * **Verification Goals** - Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. + Ensure that ARLEN == 0b01 || ARLEN == 0b00 is always true while ARVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random -* **Coverage Method:** Assertion Coverage +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 * **Unique verification tag:** VP_1_F005_S000_I001 * **Link to Coverage:** @@ -50,10 +50,10 @@ All write transaction performed by CVA6 are of burst lenght equal to 1. AWLEN = 0b00 * **Verification Goals** - Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. + Ensure that AWLEN == 0b00 is always true while AWVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random -* **Coverage Method:** Assertion Coverage +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 * **Unique verification tag:** VP_1_F005_S000_I002 * **Link to Coverage:** @@ -69,7 +69,7 @@ The size of a read transfer does not exceed the width of the data interface. The maximum value can be taking by AxSIZE is 3. * **Verification Goals** - Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while AR_VALID is asserted. + Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while ARVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -80,20 +80,61 @@ *(none)* -#### Item: 007 +#### Item: 013 -* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) +* **Requirement location:** * **Feature Description** - Exclusive access transactions cannot have a length greater than 16 beats + The maximum value can be taken by AxSIZE is XLEN/8 * **Verification Goals** - Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID is asserted. -* **Pass/Fail Criteria:** Assertion -* **Test Type:** Constrained Random -* **Coverage Method:** Assertion Coverage + Ensure that AxSIZE <= clog2(XLEN/8) +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 -* **Unique verification tag:** VP_1_F005_S000_I007 +* **Unique verification tag:** VP_AXI_F005_S000_I013 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 014 + +* **Requirement location:** +* **Feature Description** + + if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1, the maximum load instruction size is 4 bytes + ARSIZE can not be equal to 0, 1 or 2 if ARLOCK = 1 +* **Verification Goals** + + Ensure that ARSIZE != 3 when ARID = 1 and ARLEN = 0 + Ensure that ARSIZE != 0, 1 or 2 when ARID = 0 + Ensure that ARSIZE != 0, 1 or 2 when ARLOCK = 1 +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_AXI_F005_S000_I014 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 015 + +* **Requirement location:** +* **Feature Description** + + if(RVA) AxLOCK = 1 => AxSIZE > 1, CVA6 doesn't perform exclusive transaction with size lower than 4 bytes +* **Verification Goals** + + Ensure that AWSIZE > 1 when AWLOCK = 1 +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_AXI_F005_S000_I015 * **Link to Coverage:** * **Comments** @@ -108,10 +149,10 @@ * **Requirement location:** AXI Design doc - Transaction Identifiers * **Feature Description** - The CVA6 identify read transaction with an ID equal to 0 or 1 + The CVA6 identify read transaction with an ID equal to 0 or 1 for normal transaction, and 3 for exclusive transaction * **Verification Goals** - Ensure that ARID == 0b01 || ARID == 0b00 is always true while AR_VALID is asserted. + Ensure that ARID == 0b01 || ARID == 0b00 || (ARID == 0b11 && (Exclusive_Access || Atomic_transaction)) is always true while ARVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -127,10 +168,10 @@ * **Requirement location:** AXI Design doc - Transaction Identifiers * **Feature Description** - The CVA6 identify write transaction with an ID equal to 1 + The CVA6 identify write transaction with an ID equal to 1 for normal transaction, and 3 for exclusive transaction or atomic operations * **Verification Goals** - Ensure that AWID == 0b01 is always true while AW_VALID is asserted. + Ensure that AWID == 0b01 || AWID == 0b11 && (Exclusive_Access || Atomic_transaction) is always true while AWVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -151,7 +192,7 @@ User-defined extension for the write and read address channel is not supported. AxUSER = 0b00 * **Verification Goals** - Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. + Ensure that AxUSER = 0b00 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -170,7 +211,7 @@ User-defined extension for the write response channel is not supported. * **Verification Goals** - Ensure that BUSER = 0b00 is always true while B_VALID is asserted. + Ensure that BUSER = 0b00 is always true while BVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -191,7 +232,7 @@ Quality of Service identifier is not supported. AxQOS = 0b0000 * **Verification Goals** - Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. + Ensure that AxQOS = 0b0000 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -209,10 +250,10 @@ * **Requirement location:** AXI Design Doc - Transaction Attributes: Memory types * **Feature Description** - AxCACHE always take 0b0000. + AxCACHE always take 0b0010. * **Verification Goals** - Ensure that AxCACHE = 0b0000 is always true while AX_VALID is asserted. + Ensure that AxCACHE = 0b0010 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -233,7 +274,7 @@ Protection attributes always take the 0b000 * **Verification Goals** - Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. + Ensure that AxPROT = 0b000 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -254,7 +295,7 @@ Region indicator is not supported. AxREGION = 0b0000 * **Verification Goals** - Ensure that AxREGION = 0b0000 is always true while AX_VALID is asserted. + Ensure that AxREGION = 0b0000 is always true while AxVALID is asserted. * **Pass/Fail Criteria:** Assertion * **Test Type:** Constrained Random * **Coverage Method:** Assertion Coverage @@ -265,6 +306,46 @@ *(none)* +### Sub-feature: 009_Strob + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + CVA6 does not performe unaligned memory accesses, therefore WSTRB takes only combinations for aligned accesses +* **Verification Goals** + + Ensure that WSTRB does not take value different than 1, 2, 3, 4, 8, 12, 15, 16, 32, 48, 64, 128, 192, 240 and 255 +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_AXI_F006_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** +* **Feature Description** + + If(RV32) WSTRB < 255, Since AWSIZE lower than 3, so the data bus cannot have more than 4 valid byte lanes +* **Verification Goals** + + Ensure that WSTRB does not take 255 +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2 +* **Unique verification tag:** VP_AXI_F006_S009_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + ## Feature: Clock and Reset ### Sub-feature: 000_Signals_Value @@ -326,6 +407,27 @@ *(none)* +### Sub-feature: 001_Hard_Reset + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Random hard reset during simulation. +* **Verification Goals** + + Ensure that the CVA6 restarts the test from the start address and does not crash after disabling the reset. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_AXI_F007_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + ## Feature: Handshake_Process ### Sub-feature: 000_Stability @@ -459,3 +561,26 @@ *(none)* +## Feature: Error Injection + +### Sub-feature: 000_Protocol errors + +#### Item: 003 + +* **Requirement location:** +* **Feature Description** + + Injection error by randomizing resp signal. +* **Verification Goals** + + Randomize xRESP signals. The CVA6 shouldn’t crash if RESP signal indicate an error in a transaction. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_AXI_F009_S000_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* +