diff --git a/Flist.ariane b/Flist.ariane
index 8b24022ee..940999ae0 100644
--- a/Flist.ariane
+++ b/Flist.ariane
@@ -77,6 +77,8 @@ src/axi_mem_if/src/axi2mem.sv
 src/tech_cells_generic/src/pulp_clock_gating.sv
 src/tech_cells_generic/src/cluster_clock_inverter.sv
 src/tech_cells_generic/src/pulp_clock_mux2.sv
+src/pmp/src/pmp.sv
+src/pmp/src/pmp_entry.sv
 src/axi_adapter.sv
 src/alu.sv
 src/fpu_wrap.sv
diff --git a/openpiton/ariane_verilog_wrap.sv b/openpiton/ariane_verilog_wrap.sv
index c1e5833d0..e90c49b8e 100644
--- a/openpiton/ariane_verilog_wrap.sv
+++ b/openpiton/ariane_verilog_wrap.sv
@@ -13,7 +13,9 @@
 // Description: Ariane Top-level wrapper to break out SV structs to logic vectors.
 
 
-module ariane_verilog_wrap #(
+module ariane_verilog_wrap
+    import ariane_pkg::*;
+#(
   parameter int unsigned               RASDepth              = 2,
   parameter int unsigned               BTBEntries            = 32,
   parameter int unsigned               BHTEntries            = 128,