From fac99d2ccf78b57033ed4b714d7bd26c1d78a2e4 Mon Sep 17 00:00:00 2001
From: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
Date: Tue, 18 Mar 2025 11:44:38 +0100
Subject: [PATCH] csr_regfile : condition RTL to improve code coverage

---
 core/csr_regfile.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index d5a184b57..88adb53a7 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -2613,7 +2613,7 @@ module csr_regfile
       wfi_q                  <= 1'b0;
       // pmp
       for (int i = 0; i < 64; i++) begin
-        if (i < CVA6Cfg.NrPMPEntries) begin
+        if (CVA6Cfg.NrPMPEntries != 0 && i < CVA6Cfg.NrPMPEntries) begin
           pmpcfg_q[i]  <= riscv::pmpcfg_t'(CVA6Cfg.PMPCfgRstVal[i]);
           pmpaddr_q[i] <= CVA6Cfg.PMPAddrRstVal[i][CVA6Cfg.PLEN-3:0];
         end else begin