diff --git a/CHANGELOG b/CHANGELOG
index 632d109f9..eab8fed0c 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,5 @@
+v 0.2.1
+    - Add support for Torture test framework
 v 0.2.0
     - Virtual memory support according to riscv privilege specification 1.11
     - IPC improvements
diff --git a/Makefile b/Makefile
index 9fbb3feeb..453b86679 100644
--- a/Makefile
+++ b/Makefile
@@ -110,13 +110,13 @@ $(library):
 	vlib${questa_version} ${library}
 
 sim: build
-	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +ASMTEST=$(riscv-test-dir)/$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 simc: build
-	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +ASMTEST=$(riscv-test-dir)/$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +signature=output/test.rtlsim.sig +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 run-asm-tests: build
-	$(foreach test, $(riscv-tests), vsim$(questa_version) +UVM_TESTNAME=$(test_case) +ASMTEST=$(riscv-test-dir)/$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $(library).$(test_top_level)_optimized;)
+	$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $(library).$(test_top_level)_optimized;)
 
 # Run the specified test case
 $(tests): build
diff --git a/ariane-run-torture b/ariane-run-torture
index 0bc5d8cab..d7ebc9ac2 100755
--- a/ariane-run-torture
+++ b/ariane-run-torture
@@ -3,6 +3,5 @@
 cd output && make
 cd ../..
 # start the simulation
-vsim-10.6 -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +ASMTEST=riscv-torture/$3 -coverage -classdebug -do "run -a"
-# move the signature file to the appropriate place
-mv test.ariane.sig riscv-torture/output/test.rtlsim.sig
+vsim-10.6 -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +BASEDIR=riscv-torture $1 +ASMTEST=$3 -coverage -classdebug -do "run -a"
+
diff --git a/tb/core_tb.sv b/tb/core_tb.sv
index 9167d6369..070114dc8 100644
--- a/tb/core_tb.sv
+++ b/tb/core_tb.sv
@@ -171,11 +171,16 @@ module core_tb;
         longint unsigned begin_signature_address;
 
         string file;
+        string file_name;
+        string base_dir;
         string test;
         // offset the temporary RAM
         logic [7:0] rmem [`DRAM_BASE:`DRAM_BASE + 32768];
         // get the file name from a command line plus arg
-        void'(uvcl.get_arg_value("+ASMTEST=",file));
+        void'(uvcl.get_arg_value("+BASEDIR=", base_dir));
+        void'(uvcl.get_arg_value("+ASMTEST=", file_name));
+
+        file = {base_dir, "/", file_name};
 
         $display("Pre-loading memory from file: %s\n", file);
         // read elf file (DPI call)
diff --git a/tb/env/core/core_eoc.svh b/tb/env/core/core_eoc.svh
index a90c57f5d..2fe9fb215 100755
--- a/tb/env/core/core_eoc.svh
+++ b/tb/env/core/core_eoc.svh
@@ -22,6 +22,11 @@ class core_eoc extends uvm_component;
     logic got_write = 1'b0;
     int exit_code = 0;
     int f;
+    string sig_dump_name;
+    string base_dir;
+    // get the command line processor for parsing the plus args
+    static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
+
     //------------------------------------------
     // Methods
     //------------------------------------------
@@ -35,6 +40,15 @@ class core_eoc extends uvm_component;
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
+        // get the signature dump file name
+        void'(uvcl.get_arg_value("+BASEDIR=", base_dir));
+        // check if the argument was supplied
+        if(uvcl.get_arg_value("+signature=", sig_dump_name) == 0) begin
+            sig_dump_name = "test.ariane.sig";
+        end
+
+        sig_dump_name = {base_dir, "/", sig_dump_name};
+
         if (!uvm_config_db #(longint unsigned)::get(this, "", "tohost", tohost))
             `uvm_fatal("VIF CONFIG", "Cannot get() interface core_if from uvm_config_db. Have you set() it?")
 
@@ -47,6 +61,7 @@ class core_eoc extends uvm_component;
 
     function void write (dcache_if_seq_item seq_item);
 
+        // get the tohost value -> for details see the riscv-fesvr implementation
         if (seq_item.address == tohost) begin
             exit_code = seq_item.wdata >> 1;
             if (exit_code)
@@ -71,8 +86,8 @@ class core_eoc extends uvm_component;
         super.extract_phase(phase);
         // Dump Signature
         if (this.begin_signature != '0) begin
-            this.f = $fopen("test.ariane.sig" ,"w");
-            // extract 256 byte + 1024 byte memory dump starting from begin_signature symbol
+            this.f = $fopen(sig_dump_name, "w");
+            // extract 256 byte register dump + 1024 byte memory dump starting from begin_signature symbol
             for (int i = this.begin_signature; i < this.begin_signature + 162; i += 2)
                 $fwrite(this.f, "%x%x\n", $root.core_tb.core_mem_i.ram_i.mem[i + 1], $root.core_tb.core_mem_i.ram_i.mem[i]);