*~
*.nm
*.elf
*.hex
*.itb
*.map
*.o
*.objdump
*.readelf
*.gtkw
*.vcd
*.vsif
*.sve
*.sdb
test_build
dsim.env
dsim.log
dsim_results
metrics.db
metrics_history.db
xrun_results
vsim_results
vmgr_sessions
__pycache__
*.swp
/.cproject
/.project
.dvt/
dvt_build.log
xrun.history
xrun.log
xrun.key
xcelium.d/
waves.shm/
*.log
stdout.txt
.vscode
tests/riscv-compliance/
tests/riscv-arch-test/
tests/riscv-tests/
tests/riscv-isa-sim/
sim/vcs_results
sim/verilator_work
sim/out_*
sim/Mem_init.txt
sim/*.txt
sim/trace*
sim/simv*
sim/ucli.key
sim/.inter*
sim/.vcs*
sim/inter*
sim/novas*
sim/verdiLog
sim/Verdi.ses*
riviera_results/
*/vendor_lib/dpi_dasm_spike/
*/vendor_lib/verilab/svlib/
work*
vsim.dbg
*.wlf
transcript
.lib-rtl
.opt-rtl
tools/spike
tools/verilator*
*_results/
*.signature_output
ucli.key
vcs.cmd