adapter_khz     1000

interface ftdi
ftdi_vid_pid 0x0403 0x6010

# Channel 1 is taken by Xilinx JTAG
ftdi_channel 0

# links:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
#
# Bit  MPSSE     FT2232    JTAG    Type   Description
# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O
# this corresponds to the following in/out layout, with TMS initially set to 1
ftdi_layout_init 0x0018 0x001b
# we only have to specify nTRST, the others are assigned correctly by default
ftdi_layout_signal nTRST -ndata 0x0010

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv

gdb_report_data_abort enable
gdb_report_register_access_error enable

riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120

# prefer to use sba for system bus access
riscv set_prefer_sba off

init
halt
echo "Ready for Remote Connections"