////
   Copyright 2022 Thales DIS design services SAS
   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
   You may obtain a copy of the License at https://solderpad.org/licenses/

   Original Author: Jean-Roch COULON - Thales
////

[[architecture-and-modules]]
Architecture and Modules
------------------------

The {ohg-config} is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.

For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.

The {ohg-config} subsystem is composed of 8 modules.

image:subsystems.png[{ohg-config} modules]

Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.

image:{ohg-config}_subsystems.png[{ohg-config} pipeline and modules]

include::cv32a6_frontend.adoc[]
include::cva6_id_stage.adoc[]
include::cva6_issue_stage.adoc[]
include::cv32a6_execute.adoc[]
include::cva6_commit_stage.adoc[]
include::cva6_controller.adoc[]
include::cva6_csr_regfile.adoc[]
include::cva6_caches.adoc[]
