CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:top_artya7:0.1"
description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
filesets:
  files_rtl_artya7:
    depend:
      - lowrisc:ibex:ibex_core
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/top_artya7.sv
    file_type: systemVerilogSource

  files_constraints:
    files:
      - data/pins_artya7.xdc
    file_type: xdc

parameters:
  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
  # --SRAM_INIT_FILE=$PWD/sw/led/led.vmem
  # XXX: The VMEM file should be added to the sources of the Vivado project to
  # make the Vivado dependency tracking work. However this requires changes to
  # fusesoc first.
  SRAM_INIT_FILE:
    datatype: str
    description: SRAM initialization file in vmem hex format
    default: "../../../../../examples/sw/led/led.vmem"
    paramtype: vlogdefine

  FPGA_XILINX:
    datatype: str
    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
    default: 1
    paramtype: vlogdefine

targets:
  synth:
    default_tool: vivado
    filesets:
      - files_rtl_artya7
      - files_constraints
    toplevel: top_artya7
    parameters:
      - SRAM_INIT_FILE
      - FPGA_XILINX
    tools:
      vivado:
        part: "xc7a100tcsg324-1"  # Default to Arty A7-100
