CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_simple_system"
description: "Generic simple system for running binaries on ibex using verilator"
filesets:
  files_sim_verilator:
    depend:
      - lowrisc:dv_verilator:memutil_verilator
      - lowrisc:dv_verilator:simutil_verilator
      - lowrisc:ibex:ibex_core_tracing
      - lowrisc:ibex:sim_shared
      - lowrisc:dv_verilator:ibex_pcounts
    files:
      - rtl/ibex_simple_system.sv
      - ibex_simple_system.cc: { file_type: cppSource }
    file_type: systemVerilogSource

  files_verilator_waiver:
    files:
      - lint/verilator_waiver.vlt: {file_type: vlt}


parameters:
  RV32M:
    datatype: int
    paramtype: vlogparam
    default: 1
    description: Enable the M ISA extension (hardware multiply/divide) [0/1]
  RV32E:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enable the E ISA extension (reduced register set) [0/1]
  RV32B:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enable the B ISA extension (bit manipulation EXPERIMENTAL) [0/1]
  SRAM_INIT_FILE:
    datatype: str
    paramtype: vlogdefine
    description: Path to a vmem file to initialize the RAM with
  MultiplierImplementation:
    datatype: str
    paramtype: vlogparam
    description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
    default: "fast"
  BranchTargetALU:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
  WritebackStage:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enables third pipeline stage (EXPERIMENTAL)

targets:
  sim:
    default_tool: verilator
    filesets:
      - tool_verilator ? (files_verilator_waiver)
      - files_sim_verilator
    parameters:
      - RV32M
      - RV32E
      - RV32B
      - MultiplierImplementation
      - BranchTargetALU
      - WritebackStage
      - SRAM_INIT_FILE
    toplevel: ibex_simple_system
    tools:
      vcs:
        vcs_options:
          - '-debug_access+r'
      verilator:
        mode: cc
        verilator_options:
# Disabling tracing reduces compile times by multiple times, but doesn't have a
# huge influence on runtime performance. (Based on early observations.)
          - '--trace'
          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
# compiler flags
#
# -O
#   Optimization levels have a large impact on the runtime performance of the
#   simulation model. -O2 and -O3 are pretty similar, -Os is slower than -O2/-O3
          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g -O0"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"
          - "-Wno-PINCONNECTEMPTY"
          # XXX: Cleanup all warnings and remove this option
          # (or make it more fine-grained at least)
          - "-Wno-fatal"
          # RAM primitives wider than 64bit (required for ECC) fail to build in
          # Verilator without increasing the unroll count (see Verilator#1266)
          - "--unroll-count 72"

