CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_riscv_compliance:0.1"
description: "Ibex simulation for RISC-V compliance testing (using Verilator)"
filesets:
  files_sim_verilator:
    depend:
      - lowrisc:dv_verilator:memutil_verilator
      - lowrisc:dv_verilator:simutil_verilator
      - lowrisc:ibex:ibex_core_tracing
      - lowrisc:ibex:sim_shared

    files:
      - rtl/ibex_riscv_compliance.sv
      - ibex_riscv_compliance.cc: { file_type: cppSource }
      - rtl/riscv_testutil.sv
    file_type: systemVerilogSource

  files_verilator_waiver:
    files:
      - lint/verilator_waiver.vlt: {file_type: vlt}


parameters:
  RV32M:
    datatype: int
    paramtype: vlogparam
    default: 1
    description: Enable the M ISA extension (hardware multiply/divide)
  RV32E:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enable the E ISA extension (reduced register set)
  RV32B:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enable the B ISA extension (bit manipulation EXPERIMENTAL)
  MultiplierImplementation:
    datatype: str
    paramtype: vlogparam
    description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
    default: "fast"
  BranchTargetALU:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
  WritebackStage:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: Enables third pipeline stage (EXPERIMENTAL)

targets:
  sim:
    default_tool: verilator
    filesets:
      - tool_verilator ? (files_verilator_waiver)
      - files_sim_verilator
    parameters:
      - RV32M
      - RV32E
      - RV32B
      - MultiplierImplementation
      - BranchTargetALU
      - WritebackStage
    toplevel: ibex_riscv_compliance
    tools:
      verilator:
        mode: cc
        verilator_options:
          # Disabling tracing reduces compile times but doesn't have a
          # huge influence on runtime performance.
          - '--trace'
          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
          # Remove FST options for VCD trace (~100 x faster but larger files)
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"
          - "-Wno-PINCONNECTEMPTY"
          # XXX: Cleanup all warnings and remove this option
          # (or make it more fine-grained at least)
          - "-Wno-fatal"
        make_options:
          # Optimization levels have a large impact on the runtime performance
          # of the simulation model. -O2 and -O3 are pretty similar, -Os is
          # slower than -O2/-O3
          - OPT_FAST="-O2"
