diff --git a/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv b/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
index a3c9da7d..1abe4050 100644
--- a/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
+++ b/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
@@ -21,35 +21,19 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
     // with ibex.
     cfg.check_misa_init_val = 1'b0;
     cfg.check_xstatus = 1'b0;
-    // The ibex core load the program from 0x80
-    // Some address is reserved for hardware interrupt handling, need to decide if we need to copy
-    // the init program from crt0.S later.
     instr_stream.push_back(".macro init");
     instr_stream.push_back(".endm");
     instr_stream.push_back(".section .text.init");
     instr_stream.push_back(".globl _start");
     instr_stream.push_back(".option norvc");
-    // 0x0 - 0x4F is reserved for trap/interrupt handling
-    repeat (20) begin
-      instr_stream.push_back("j mtvec_handler");
-    end
-    // 0x50 debug mode entry
+    // 0x0 debug mode entry
     instr_stream.push_back("j debug_rom");
-    // 0x54 debug mode exception handler
+    // 0x4 debug mode exception handler
     instr_stream.push_back("j debug_exception");
     // Align the start section to 0x80
     instr_stream.push_back(".align 7");
-    instr_stream.push_back("_start: j _reset_entry");
-    // ibex reserves 0x84-0x8C for trap handling, redirect everything mtvec_handler
-    // 0x84 illegal instruction
-    instr_stream.push_back("j mtvec_handler");
-    // 0x88 ECALL instruction handler
-    instr_stream.push_back("j mtvec_handler");
-    // 0x8C LSU error
-    instr_stream.push_back("j mtvec_handler");
     instr_stream.push_back(".option rvc");
-    // Starting point of the reset entry
-    instr_stream.push_back("_reset_entry:");
+    instr_stream.push_back("_start:");
   endfunction
 
 endclass
diff --git a/dv/uvm/riscv_dv_extension/ibex_core_setting.sv b/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
index 38b84121..4f4c5987 100644
--- a/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
+++ b/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
@@ -34,6 +34,9 @@ riscv_instr_name_t unsupported_instr[] = {FENCEI};
 // ISA supported by the processor
 riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
 
+// Interrupt mode support
+mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};
+
 // Debug mode support
 bit support_debug_mode = 1;
 
diff --git a/dv/uvm/tb/core_ibex_tb_top.sv b/dv/uvm/tb/core_ibex_tb_top.sv
index 183337d3..20013921 100644
--- a/dv/uvm/tb/core_ibex_tb_top.sv
+++ b/dv/uvm/tb/core_ibex_tb_top.sv
@@ -18,8 +18,8 @@ module core_ibex_tb_top;
   core_ibex_dut_probe_if dut_if(.clk(clk));
 
   // TODO(taliu) Resolve the tied-off ports
-  ibex_core_tracing #(.DmHaltAddr(`BOOT_ADDR + 'h50),
-                      .DmExceptionAddr(`BOOT_ADDR + 'h54)) dut (
+  ibex_core_tracing #(.DmHaltAddr(`BOOT_ADDR + 'h0),
+                      .DmExceptionAddr(`BOOT_ADDR + 'h4)) dut (
     .clk_i(clk),
     .rst_ni(rst_n),
     .test_en_i(1'b1),