diff --git a/dv/uvm/riscv_dv_extension/riscv_core_setting.sv b/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
index dbcdc34c..621aeeeb 100644
--- a/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
+++ b/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
@@ -137,3 +137,22 @@ parameter privileged_reg_t implemented_csr[] = {
     DSCRATCH0,        // Debug scratch register 0
     DSCRATCH1         // Debug scratch register 1
 };
+
+// --------------------------------------------------------------------------
+// Supported interrupt/exception setting, used for functional coverage
+// --------------------------------------------------------------------------
+
+parameter interrupt_cause_t implemented_interrupt[] = {
+  M_SOFTWARE_INTR,
+  M_TIMER_INTR,
+  M_EXTERNAL_INTR
+};
+
+parameter exception_cause_t implemented_exception[] = {
+  INSTRUCTION_ACCESS_FAULT,
+  ILLEGAL_INSTRUCTION,
+  BREAKPOINT,
+  LOAD_ACCESS_FAULT,
+  STORE_AMO_ACCESS_FAULT,
+  ECALL_MMODE
+};
diff --git a/dv/uvm/riscv_dv_extension/testlist.yaml b/dv/uvm/riscv_dv_extension/testlist.yaml
index 7b1d8ed2..d57cabdd 100644
--- a/dv/uvm/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/riscv_dv_extension/testlist.yaml
@@ -152,12 +152,12 @@
     +no_csr_instr=1
     +no_fence=1
     +num_of_sub_program=0
-    +num_debug_sub_program=3
+    +num_debug_sub_program=2
     +randomize_csr=1
   rtl_test: core_ibex_debug_intr_basic_test
   sim_opts: >
     +require_signature_addr=1
-    +max_interval=2000
+    +max_interval=3000
     +enable_debug_stress_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -172,11 +172,12 @@
     +require_signature_addr=1
     +gen_debug_section=1
     +no_ebreak=1
-    +instr_cnt=3000
+    +instr_cnt=6000
     +no_csr_instr=1
     +no_fence=1
     +no_wfi=0
     +randomize_csr=1
+    +num_of_sub_program=0
   rtl_test: core_ibex_debug_wfi_test
   sim_opts: >
     +require_signature_addr=1
@@ -239,6 +240,7 @@
     +no_wfi=1
     +instr_cnt=6000
     +randomize_csr=1
+    +num_of_sub_program=0
   rtl_test: core_ibex_debug_ebreakm_test
   sim_opts: >
     +require_signature_addr=1
diff --git a/dv/uvm/sim.py b/dv/uvm/sim.py
index 86ee1b26..c3ea22d9 100644
--- a/dv/uvm/sim.py
+++ b/dv/uvm/sim.py
@@ -167,6 +167,12 @@ def compare(test_list, iss, output_dir, verbose):
   """
   report = ("%s/regr.log" % output_dir).rstrip()
   for test in test_list:
+    compare_opts = test.get('compare_opts', {})
+    in_order_mode = compare_opts.get('in_order_mode', 1)
+    coalescing_limit = compare_opts.get('coalescing_limit', 0)
+    verbose = compare_opts.get('verbose', 0)
+    mismatch = compare_opts.get('mismatch_print_limit', 5)
+    compare_final = compare_opts.get('compare_final_value_only', 0)
     for i in range(0, test['iterations']):
       elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
       logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
@@ -193,12 +199,6 @@ def compare(test_list, iss, output_dir, verbose):
           check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
         else:
           if 'compare_opts' in test:
-            compare_opts = test.get('compare_opts')
-            in_order_mode = compare_opts.get('in_order_mode', 1)
-            coalescing_limit = compare_opts.get('coalescing_limit', 0)
-            verbose = compare_opts.get('verbose', 0)
-            mismatch = compare_opts.get('mismatch_print_limit', 5)
-            compare_final = compare_opts.get('compare_final_value_only', 0)
             compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report,
                               in_order_mode, coalescing_limit, verbose,
                               mismatch, compare_final)
diff --git a/dv/uvm/tests/core_ibex_base_test.sv b/dv/uvm/tests/core_ibex_base_test.sv
index 5b73bd22..6bd56356 100644
--- a/dv/uvm/tests/core_ibex_base_test.sv
+++ b/dv/uvm/tests/core_ibex_base_test.sv
@@ -10,7 +10,7 @@ class core_ibex_base_test extends uvm_test;
   virtual core_ibex_dut_probe_if                  dut_vif;
   mem_model_pkg::mem_model                        mem;
   core_ibex_vseq                                  vseq;
-  int unsigned                                    timeout_in_cycles = 3000000;
+  int unsigned                                    timeout_in_cycles = 5000000;
   // If no signature_addr handshake functionality is desired between the testbench and the generated
   // code, the test will wait for the specifield number of cycles before starting stimulus
   // sequences (irq and debug)
diff --git a/dv/uvm/tests/core_ibex_test_lib.sv b/dv/uvm/tests/core_ibex_test_lib.sv
index 9b4b0a7e..6a33f9d8 100644
--- a/dv/uvm/tests/core_ibex_test_lib.sv
+++ b/dv/uvm/tests/core_ibex_test_lib.sv
@@ -346,6 +346,7 @@ class core_ibex_debug_wfi_test extends core_ibex_directed_test;
     // is detected, and before any stimulus is sent to the core
     forever begin
       wait (dut_vif.wfi === 1'b1);
+      wait (dut_vif.core_sleep === 1'b1);
       clk_vif.wait_clks($urandom_range(100));
       vseq.start_debug_single_seq();
       // After assserting this signal, core should wake up and jump into debug mode from WFI state