diff --git a/cve2.core b/cve2.core
index 572ea317..ec43f9cb 100644
--- a/cve2.core
+++ b/cve2.core
@@ -44,9 +44,10 @@ filesets:
     files:
       - lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
 
-  files_check_tool_requirements:
-    depend:
-     - lowrisc:tool:check_tool_requirements
+  files_clk_gate:
+    files:
+    - bhv/cve2_sim_clock_gate.sv
+    file_type: systemVerilogSource
 
 parameters:
   RVFI:
@@ -147,6 +148,7 @@ targets:
       - tool_veriblelint ? (files_lint_verible)
       - files_rtl
       - target_sim? (files_clk_gate)
+      - target_sim-opt? (files_clk_gate)
     toplevel: ibex_core
     parameters:
       - tool_vivado ? (FPGA_XILINX=true)
diff --git a/rtl/cve2_sleep_unit.sv b/rtl/cve2_sleep_unit.sv
index 70caef4e..80388031 100644
--- a/rtl/cve2_sleep_unit.sv
+++ b/rtl/cve2_sleep_unit.sv
@@ -41,9 +41,7 @@
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
 
-module cv32e40p_sleep_unit #(
-    parameter PULP_CLUSTER = 0
-) (
+module cve2_sleep_unit (
     // Clock, reset interface
     input  logic clk_ungated_i,  // Free running clock
     input  logic rst_n,