diff --git a/shared/rtl/bus.sv b/shared/rtl/bus.sv
index d25abb3b..87067ac7 100644
--- a/shared/rtl/bus.sv
+++ b/shared/rtl/bus.sv
@@ -15,8 +15,8 @@
  * - Host (master) arbitration is strictly priority based.
  */
 module bus #(
-  parameter NrDevices,
-  parameter NrHosts,
+  parameter NrDevices    = 1,
+  parameter NrHosts      = 1,
   parameter DataWidth    = 32,
   parameter AddressWidth = 32
 ) (
diff --git a/shared/rtl/ram_1p.sv b/shared/rtl/ram_1p.sv
index 665a4335..244c3902 100644
--- a/shared/rtl/ram_1p.sv
+++ b/shared/rtl/ram_1p.sv
@@ -5,6 +5,9 @@
 /**
  * Single-port RAM with 1 cycle read/write delay, 32 bit words
  */
+
+`include "prim_assert.sv"
+
 module ram_1p #(
     parameter int Depth = 128
 ) (
@@ -75,7 +78,7 @@ module ram_1p #(
   `endif
 
   `ifdef SRAM_INIT_FILE
-    localparam MEM_FILE = `"`SRAM_INIT_FILE`";
+    localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
     initial begin
       $display("Initializing SRAM from %s", MEM_FILE);
       $readmemh(MEM_FILE, mem);
diff --git a/shared/rtl/ram_2p.sv b/shared/rtl/ram_2p.sv
index d583fb4f..2eb77fa8 100644
--- a/shared/rtl/ram_2p.sv
+++ b/shared/rtl/ram_2p.sv
@@ -12,6 +12,9 @@
  * Simultaneous write operations by both ports to the same address are to be avoided: The data
  * written to memory is not determined.
  */
+
+`include "prim_assert.sv"
+
 module ram_2p #(
     parameter int Depth = 128
 ) (
@@ -116,7 +119,7 @@ module ram_2p #(
   `endif
 
   `ifdef SRAM_INIT_FILE
-    localparam MEM_FILE = `"`SRAM_INIT_FILE`";
+    localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
     initial begin
       $display("Initializing SRAM from %s", MEM_FILE);
       $readmemh(MEM_FILE, mem);