diff --git a/doc/Makefile b/doc/Makefile index a1008113..2b8ed89d 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -4,7 +4,7 @@ # You can set these variables from the command line. SPHINXOPTS = SPHINXBUILD = sphinx-build -SPHINXPROJ = zero-riscy +SPHINXPROJ = ibex SOURCEDIR = . BUILDDIR = _build @@ -17,4 +17,4 @@ help: # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). %: Makefile - @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) \ No newline at end of file + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/doc/conf.py b/doc/conf.py index ebe3e038..8c07273b 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# zero-riscy documentation build configuration file, created by +# ibex documentation build configuration file, created by # sphinx-quickstart on Thu Nov 8 15:42:18 2018. # # This file is execfile()d with the current directory set to its @@ -48,9 +48,9 @@ source_suffix = '.rst' master_doc = 'index' # General information about the project. -project = u'ZERO-RISCY' -copyright = u'2017-2018, ETH Zurich and University of Bologna' -author = u'Pasquale Davide Schiavone' +project = u'Ibex' +copyright = u'2017-2018, ETH Zurich and University of Bologna, 2018-present lowRISC' +author = u'lowRISC contributors' from setuptools_scm import get_version release = get_version(root='..', relative_to=__file__) @@ -97,7 +97,7 @@ html_theme = 'sphinx_rtd_theme' html_theme_options = { } -html_logo = 'images/pulp.png' +html_logo = '' # Add any paths that contain custom static files (such as style sheets) here, # relative to this directory. They are copied after the builtin static files, @@ -107,7 +107,7 @@ html_logo = 'images/pulp.png' # -- Options for HTMLHelp output ------------------------------------------ # Output file base name for HTML help builder. -htmlhelp_basename = 'zero-riscydoc' +htmlhelp_basename = 'ibexdoc' @@ -135,18 +135,18 @@ latex_elements = { # (source start file, target name, title, # author, documentclass [howto, manual, or own class]). latex_documents = [ - (master_doc, 'zero-riscy.tex', u'ZERO-RISCY Documentation', - u'ETH Zurich and University of Bologna', 'manual'), + (master_doc, 'ibex.tex', u'Ibex Documentation', + u'lowRISC', 'manual'), ] -latex_logo = 'images/pulp_title.png' +latex_logo = '' # -- Options for manual page output --------------------------------------- # One entry per manual page. List of tuples # (source start file, name, description, authors, manual section). man_pages = [ - (master_doc, 'zero-riscy', u'zero-riscy Documentation', + (master_doc, 'ibex', u'Ibex Documentation', [author], 1) ] @@ -157,7 +157,7 @@ man_pages = [ # (source start file, target name, title, author, # dir menu entry, description, category) texinfo_documents = [ - (master_doc, 'zero-riscy', u'zero-riscy Documentation', - author, 'zero-riscy', 'One line description of project.', + (master_doc, 'ibex', u'Ibex Documentation', + author, 'ibex', 'Ibex RV32 CPU core', 'Miscellaneous'), ] diff --git a/doc/cs_registers.rst b/doc/cs_registers.rst index ee17d1e8..35bc9a24 100644 --- a/doc/cs_registers.rst +++ b/doc/cs_registers.rst @@ -3,7 +3,7 @@ Control and Status Registers ============================ -ZERO-RISCY does not implement all control and status registers specified in the RISC-V privileged specifications, but is limited to the registers that were needed for the PULP system. The reason for this is that we wanted to keep the footprint of the core as low as possible and avoid any overhead that we do not explicitly need. +Ibex does not implement all control and status registers specified in the RISC-V privileged specifications, but is limited to the registers that were needed for the PULP system. The reason for this is that we wanted to keep the footprint of the core as low as possible and avoid any overhead that we do not explicitly need. .. tabularcolumns:: |p{1cm}|p{.6cm}|p{.6cm}|p{1cm}|p{1cm}|p{1.5cm}|p{1.2cm}|p{6cm}| diff --git a/doc/exception_interrupts.rst b/doc/exception_interrupts.rst index 62d3a7f9..691e4432 100644 --- a/doc/exception_interrupts.rst +++ b/doc/exception_interrupts.rst @@ -3,7 +3,7 @@ Exceptions and Interrupts ========================= -ZERO-RISCY supports interrupts, exceptions on illegal instructions. +Ibex supports interrupts, exceptions on illegal instructions. +------------+-----------------------------+ | Address | Description | @@ -38,6 +38,6 @@ The illegal instruction exception and ecall instruction exceptions cannot be dis Handling -------- -ZERO-RISCY does support nested interrupt/exception handling. Exceptions inside interrupt/exception handlers cause another exception, thus exceptions during the critical part of your exception handlers, i.e. before having saved the MEPC and MESTATUS registers, will cause those register to be overwritten. Interrupts during interrupt/exception handlers are disabled by default, but can be explicitly enabled if desired. +Ibex does support nested interrupt/exception handling. Exceptions inside interrupt/exception handlers cause another exception, thus exceptions during the critical part of your exception handlers, i.e. before having saved the MEPC and MESTATUS registers, will cause those register to be overwritten. Interrupts during interrupt/exception handlers are disabled by default, but can be explicitly enabled if desired. Upon executing an mret instruction, the core jumps to the program counter saved in the CSR register MEPC and restores the MPIE value of the register MSTATUS to IE. When entering an interrupt/exception handler, the core sets MEPC to the current program counter and saves the current value of MIE in MPIE of the MSTATUS register. diff --git a/doc/images/pulp.png b/doc/images/pulp.png deleted file mode 100644 index 99b9a657..00000000 Binary files a/doc/images/pulp.png and /dev/null differ diff --git a/doc/images/pulp_title.png b/doc/images/pulp_title.png deleted file mode 100644 index 46bc5429..00000000 Binary files a/doc/images/pulp_title.png and /dev/null differ diff --git a/doc/index.rst b/doc/index.rst index bd00cbe8..6e51a851 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -1,9 +1,4 @@ -.. zero-riscy documentation master file, created by - sphinx-quickstart on Thu Nov 8 15:42:18 2018. - You can adapt this file completely to your liking, but it should at least - contain the root `toctree` directive. - -ZERO-RISCY: User Manual +Ibex: User Manual ======================= .. toctree:: @@ -26,4 +21,3 @@ ZERO-RISCY: User Manual :hidden: copyright - diff --git a/doc/instruction_fetch.rst b/doc/instruction_fetch.rst index 69849d78..b436f9ab 100644 --- a/doc/instruction_fetch.rst +++ b/doc/instruction_fetch.rst @@ -53,7 +53,7 @@ The protocol used to communicate with the instruction cache or the instruction m {"name": "clk", "wave": "p......"}, {"name": "data_addr_o", "wave": "x===xxx", "data": ["Address", "Address", "Address"]}, {"name": "data_req_o", "wave": "01..0.."}, - {"name": "data_gnt_i", "wave": "0..10.."}, + {"name": "data_gnt_i", "wave": "0..10.."}, {"name": "data_rvalid_i", "wave": "0....10"}, {"name": "data_rdata_i", "wave": "xxxxx=x", "data": ["RData"]} ], diff --git a/doc/integration.rst b/doc/integration.rst index 48f53a5b..55b26ed5 100644 --- a/doc/integration.rst +++ b/doc/integration.rst @@ -1,14 +1,14 @@ Core Integration ================ -The main module is named ``zeroriscy_core`` and can be found in ``zeroriscy_core.sv``. In the following the instantiation template is given and the parameters and interfaces are described. +The main module is named ``ibex_core`` and can be found in ``ibex_core.sv``. In the following the instantiation template is given and the parameters and interfaces are described. Instantiation Template ---------------------- .. code-block:: verilog - zeroriscy_core + ibex_core #(.N_EXT_PERF_COUNTERS (0), .RV32E (0), .RV32M (1)) @@ -16,7 +16,6 @@ Instantiation Template (// Clock and reset .clk_i (), .rst_ni (), - .clock_en_i (), .test_en_i (), // Configuration @@ -92,9 +91,6 @@ Interfaces +-------------------------+-------------------------+-----+----------------------------------------+ | ``rst_ni`` | 1 | in |Active-low synchronous reset | +-------------------------+-------------------------+-----+----------------------------------------+ -| ``clock_en_i`` | 1 | in | Clock gating input | -| | | | (0: clock gated, 1: clock running) | -+-------------------------+-------------------------+-----+----------------------------------------+ | ``test_en_i`` | 1 | in | Test input, enables clock | +-------------------------+-------------------------+-----+----------------------------------------+ | ``core_id_i`` | 4 | in | Core id, usually static, can be read | @@ -116,6 +112,3 @@ Interfaces +-------------------------+-------------------------+-----+----------------------------------------+ | ``ext_perf_counters_i`` | ``N_EXT_PERF_COUNTERS`` | in | External performance counter | +-------------------------+-------------------------+-----+----------------------------------------+ - - - diff --git a/doc/introduction.rst b/doc/introduction.rst index c50097c5..b9847387 100644 --- a/doc/introduction.rst +++ b/doc/introduction.rst @@ -6,12 +6,12 @@ Introduction Block Diagram -ZERO-RISCY is a 2-stage in-order 32b RISC-V processor core. ZERO-RISCY has been designed to be small and efficient. Via two parameters, the core is configurable to support four ISA configurations. :numref:`blockdiagram` shows a block diagram of the core. +Ibex is a 2-stage in-order 32b RISC-V processor core. Ibex has been designed to be small and efficient. Via two parameters, the core is configurable to support four ISA configurations. :numref:`blockdiagram` shows a block diagram of the core. Supported Instruction Set ------------------------- -ZERO-RISCY supports the following instructions: +Ibex supports the following instructions: * Full support for RV32I Base Integer Instruction Set * Full support for RV32E Base Integer Instruction Set @@ -23,14 +23,14 @@ The RV32M and RV32E can be enable and disable using two parameters. ASIC Synthesis -------------- -ASIC synthesis is supported for ZERO-RISCY. The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops. See Chapter 4 for more details about the register file. The core occupies an area of about 18.9 kGE when the latch based register file and the RV32IMC ISA is used or 11.6 kGE when the RV32EC is used . +ASIC synthesis is supported for Ibex. The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops. See Chapter 4 for more details about the register file. The core occupies an area of about 18.9 kGE when the latch based register file and the RV32IMC ISA is used or 11.6 kGE when the RV32EC is used . FPGA Synthesis -------------- -FPGA synthesis is supported for ZERO-RISCY when the flip-flop based register file is used. Since latches are not well supported on FPGAs, it is crucial to select the flip-flop based register file. +FPGA synthesis is supported for Ibex when the flip-flop based register file is used. Since latches are not well supported on FPGAs, it is crucial to select the flip-flop based register file. Outline ------- -This document summarizes all the functionality of the ZERO-RISCY core in more detail. First, the instruction and data interfaces are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`. :ref:`register-file` explains the register file. Control and status registers are explained in :ref:`cs-registers` and Chapter :ref:`performance-counters` gives an overview of all performance counters. Chapter :ref:`exceptions-interrupts` deals with exceptions and interrupts, and finally Chapter :ref:`debug-unit` summarizes the accessible debug registers. +This document summarizes all the functionality of the Ibex core in more detail. First, the instruction and data interfaces are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`. :ref:`register-file` explains the register file. Control and status registers are explained in :ref:`cs-registers` and Chapter :ref:`performance-counters` gives an overview of all performance counters. Chapter :ref:`exceptions-interrupts` deals with exceptions and interrupts, and finally Chapter :ref:`debug-unit` summarizes the accessible debug registers. diff --git a/doc/make.bat b/doc/make.bat index efdcb3d8..8a1058b7 100644 --- a/doc/make.bat +++ b/doc/make.bat @@ -9,7 +9,7 @@ if "%SPHINXBUILD%" == "" ( ) set SOURCEDIR=. set BUILDDIR=_build -set SPHINXPROJ=zero-riscy +set SPHINXPROJ=ibex if "%1" == "" goto help diff --git a/doc/performance_counters.rst b/doc/performance_counters.rst index 347b438f..64e1fbfc 100644 --- a/doc/performance_counters.rst +++ b/doc/performance_counters.rst @@ -3,7 +3,7 @@ Performance Counters ==================== -Performance Counters in ZERO-RISCY are placed inside the Control and Status Registers and can be accessed with csrr and csrw instructions. +Performance Counters in Ibex are placed inside the Control and Status Registers and can be accessed with csrr and csrw instructions. Performance Counter Mode Register (PCMR) diff --git a/doc/register_file.rst b/doc/register_file.rst index 98466257..b892dd5a 100644 --- a/doc/register_file.rst +++ b/doc/register_file.rst @@ -3,7 +3,7 @@ Register File ============= -ZERO-RISCY has 31 or 15 32-bit wide registers depending if the RV32E extension is enabled. Register x0 is statically bound to 0 and can only be read, it does not contain any sequential logic. +Ibex has 31 or 15 32-bit wide registers depending if the RV32E extension is enabled. Register x0 is statically bound to 0 and can only be read, it does not contain any sequential logic. There are two flavors of register file available: @@ -17,7 +17,7 @@ Latch-based Register File The latch based register file contains manually instantiated clock gating cells to keep the clock inactive when the latches are not written. -It is assumed that there is a clock gating cell for the target technology that is wrapped in a module called ``cluster_clock_gating`` and has the following ports: +It is assumed that there is a clock gating cell for the target technology that is wrapped in a module called ``prim_clock_gating`` and has the following ports: * ``clk_i``: Clock Input * ``en_i``: Clock Enable Input