diff --git a/alu.sv b/alu.sv index 157444b3..3ca9880b 100644 --- a/alu.sv +++ b/alu.sv @@ -137,10 +137,10 @@ module alu end // adder consisting of four slices - assign {carry_out[0], adder_result[ 7: 0]} = adder_op_a[ 7: 0] + adder_op_b[ 7: 0] + carry_in[0]; - assign {carry_out[1], adder_result[15: 8]} = adder_op_a[15: 8] + adder_op_b[15: 8] + carry_in[1]; - assign {carry_out[2], adder_result[23:16]} = adder_op_a[23:16] + adder_op_b[23:16] + carry_in[2]; - assign {carry_out[3], adder_result[31:24]} = adder_op_a[31:24] + adder_op_b[31:24] + carry_in[3]; + assign {carry_out[0], adder_result[ 7: 0]} = adder_op_a[ 7: 0] + adder_op_b[ 7: 0] + {7'b0, carry_in[0]}; + assign {carry_out[1], adder_result[15: 8]} = adder_op_a[15: 8] + adder_op_b[15: 8] + {7'b0, carry_in[1]}; + assign {carry_out[2], adder_result[23:16]} = adder_op_a[23:16] + adder_op_b[23:16] + {7'b0, carry_in[2]}; + assign {carry_out[3], adder_result[31:24]} = adder_op_a[31:24] + adder_op_b[31:24] + {7'b0, carry_in[3]}; // averaging by right shifting of one bit @@ -617,12 +617,7 @@ module alu `ALU_NOP: ; // Do nothing - default: - begin - //synopsys translate_off - - //synopsys translate_on - end + default: ; endcase //~case(operator_i) end diff --git a/compressed_decoder.sv b/compressed_decoder.sv index 1da4ab0a..3d48f20a 100644 --- a/compressed_decoder.sv +++ b/compressed_decoder.sv @@ -28,6 +28,7 @@ module compressed_decoder ( input logic [31:0] instr_i, output logic [31:0] instr_o, + output logic is_compressed_o, output logic illegal_instr_o ); @@ -43,6 +44,7 @@ module compressed_decoder always_comb begin illegal_instr_o = 1'b0; + is_compressed_o = 1'b1; instr_o = '0; unique case (instr_i[1:0]) @@ -258,6 +260,7 @@ module compressed_decoder 2'b11: begin // 32 bit (or more) instruction instr_o = instr_i; + is_compressed_o = 1'b0; end endcase end diff --git a/cs_registers.sv b/cs_registers.sv index 3a56d506..6f7f87d5 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -308,18 +308,18 @@ module cs_registers if (is_pcmr) begin unique case (csr_op_i) `CSR_OP_NONE: ; - `CSR_OP_WRITE: PCMR_n = csr_wdata_i; - `CSR_OP_SET: PCMR_n = csr_wdata_i | PCMR_q; - `CSR_OP_CLEAR: PCMR_n = csr_wdata_i & ~(PCMR_q); + `CSR_OP_WRITE: PCMR_n = csr_wdata_i[1:0]; + `CSR_OP_SET: PCMR_n = csr_wdata_i[1:0] | PCMR_q; + `CSR_OP_CLEAR: PCMR_n = csr_wdata_i[1:0] & ~(PCMR_q); endcase end if (is_pcer) begin unique case (csr_op_i) `CSR_OP_NONE: ; - `CSR_OP_WRITE: PCER_n = csr_wdata_i; - `CSR_OP_SET: PCER_n = csr_wdata_i | PCER_q; - `CSR_OP_CLEAR: PCER_n = csr_wdata_i & ~(PCER_q); + `CSR_OP_WRITE: PCER_n = csr_wdata_i[N_PERF_REGS-1:0]; + `CSR_OP_SET: PCER_n = csr_wdata_i[N_PERF_REGS-1:0] | PCER_q; + `CSR_OP_CLEAR: PCER_n = csr_wdata_i[N_PERF_REGS-1:0] & ~(PCER_q); endcase end end @@ -336,8 +336,8 @@ module cs_registers for(int i = 0; i < N_PERF_REGS; i++) begin - PCCR_q[i] <= 'h0; - PCCR_inc_q[i] <= 'h0; + PCCR_q[i] <= '0; + PCCR_inc_q[i] <= '0; end end else diff --git a/ex_stage.sv b/ex_stage.sv index 086d4a33..e95eaa34 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -171,10 +171,7 @@ module ex_stage .adder_lsu_o ( alu_adder_lsu_int ), - .result_o ( alu_result ), - .overflow_o ( ), - .carry_o ( ), - .flag_o ( ) + .result_o ( alu_result ) ); @@ -196,12 +193,8 @@ module ex_stage .op_a_i ( alu_operand_a_i ), .op_b_i ( alu_operand_b_i ), .mac_i ( alu_operand_c_i ), - .carry_i ( 1'b0 ), - .result_o ( mult_result ), - - .carry_o ( ), - .overflow_o ( ) + .result_o ( mult_result ) ); diff --git a/include/defines.sv b/include/defines.sv index 3a7f235e..19373998 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -149,6 +149,7 @@ `define REG_D 11:07 +`ifndef SYNTHESIS // synopsys translate_off `define TRACE_EXECUTION @@ -178,6 +179,7 @@ function void prettyPrintInstruction(input [31:0] instr, input [31:0] pc); end endfunction // prettyPrintInstruction // synopsys translate_on +`endif diff --git a/mult.sv b/mult.sv index 5fd1b7a4..c5c0d77e 100644 --- a/mult.sv +++ b/mult.sv @@ -43,19 +43,17 @@ module mult input logic [31:0] op_b_i, input logic [31:0] mac_i, - output logic [31:0] result_o, - output logic carry_o, - output logic overflow_o + output logic [31:0] result_o ); - logic [32:0] result; + logic [31:0] result; logic [31:0] op_a_sel; logic [31:0] op_b_sel; - logic [32:0] mac_int; + logic [31:0] mac_int; - assign mac_int = (mac_en_i == 1'b1) ? {1'b0, mac_i} : 33'b0; + assign mac_int = (mac_en_i == 1'b1) ? mac_i : 32'b0; // this block performs the subword selection and sign extensions always_comb @@ -86,14 +84,13 @@ module mult case(vector_mode_i) default: // VEC_MODE32, VEC_MODE216 begin - result[32: 0] = mac_int + op_a_sel * op_b_sel; + result[31: 0] = mac_int + op_a_sel * op_b_sel; end `VEC_MODE16: begin result[15: 0] = mac_int[15: 0] + op_a_sel[15: 0] * op_b_sel[15: 0]; result[31:16] = mac_int[31:16] + op_a_sel[31:16] * op_b_sel[31:16]; - result[32] = 1'b0; end `VEC_MODE8: @@ -102,18 +99,11 @@ module mult result[15: 8] = mac_int[15: 8] + op_a_sel[15: 8] * op_b_sel[15: 8]; result[23:16] = mac_int[23:16] + op_a_sel[23:16] * op_b_sel[23:16]; result[31:24] = mac_int[31:24] + op_a_sel[31:24] * op_b_sel[31:24]; - result[32] = 1'b0; end endcase; // case (vec_mode_i) end assign result_o = result[31:0]; - assign carry_o = result[32]; - - // overflow is only used for MAC - // If the MSB of the input MAC and the result is not the same => overflow occurred - assign overflow_o = mac_i[31] ^ result[31]; - endmodule // mult diff --git a/register_file.sv b/register_file.sv index f52254d5..3a6af5e7 100644 --- a/register_file.sv +++ b/register_file.sv @@ -35,11 +35,11 @@ module riscv_register_file logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS]; - logic [NUM_WORDS-1:0] WAddrOneHotxDa; - logic [NUM_WORDS-1:0] WAddrOneHotxDb; - logic [NUM_WORDS-1:0] WAddrOneHotxDb_reg; + logic [NUM_WORDS-1:1] WAddrOneHotxDa; + logic [NUM_WORDS-1:1] WAddrOneHotxDb; + logic [NUM_WORDS-1:1] WAddrOneHotxDb_reg; - logic [NUM_WORDS-1:0] ClocksxC; + logic [NUM_WORDS-1:1] ClocksxC; logic [DATA_WIDTH-1:0] WDataIntxDa; logic [DATA_WIDTH-1:0] WDataIntxDb; diff --git a/riscv_core.sv b/riscv_core.sv index fcb4dafb..48461bbb 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -722,6 +722,7 @@ module riscv_core +`ifndef SYNTHESIS // Execution trace generation // synopsys translate_off `ifdef TRACE_EXECUTION @@ -964,6 +965,7 @@ module riscv_core `endif // TRACE_EXECUTION // synopsys translate_on +`endif ///////////////////