diff --git a/examples/sim/tb/ibex_tracer_tb.sv b/examples/sim/tb/ibex_tracer_tb.sv
index 572f9af5..f03bfeeb 100644
--- a/examples/sim/tb/ibex_tracer_tb.sv
+++ b/examples/sim/tb/ibex_tracer_tb.sv
@@ -40,8 +40,11 @@ module ibex_tracer_tb;
     #10ns instr_rdata = 32'h60008113;
     #10ns instr_rdata = 32'h00000013;
     #10ns instr_rdata = 32'h00000113;
+    #30ns instr_rdata = 32'h00000013;
+    #10ns instr_rdata = 32'h0000000f;
     #10ns instr_rdata = 32'h00000013;
     #10ns instr_rdata = 32'h00000013;
+    #10ns instr_rdata = 32'h0000000f;
   end
 
   ibex_core_tracer ibex_i (
diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv
index a1def12f..a4cf1a2e 100644
--- a/rtl/ibex_tracer.sv
+++ b/rtl/ibex_tracer.sv
@@ -395,6 +395,8 @@ module ibex_tracer #(
           // LOAD & STORE
           INSTR_LOAD:       trace.printLoadInstr();
           INSTR_STORE:      trace.printStoreInstr();
+          // MISC-MEM
+          INSTR_FENCE:      trace.printMnemonic("fence");
           default:          trace.printMnemonic("INVALID");
         endcase // unique case (instr_i)
       end
diff --git a/rtl/ibex_tracer_defines.sv b/rtl/ibex_tracer_defines.sv
index e119abb4..a07b6f38 100644
--- a/rtl/ibex_tracer_defines.sv
+++ b/rtl/ibex_tracer_defines.sv
@@ -68,4 +68,7 @@ parameter logic [31:0] INSTR_PMULHU  = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCOD
 parameter logic [31:0] INSTR_LOAD    = {25'b?,                            {OPCODE_LOAD } };
 parameter logic [31:0] INSTR_STORE   = {25'b?,                            {OPCODE_STORE} };
 
+// MISC-MEM
+parameter logic [31:0] INSTR_FENCE   = { 17'b?,             3'b000, 5'b?, {OPCODE_MISC_MEM} };
+
 endpackage