diff --git a/dv/uvm/Makefile b/dv/uvm/Makefile
index 60c50498..1d581fe4 100644
--- a/dv/uvm/Makefile
+++ b/dv/uvm/Makefile
@@ -146,7 +146,7 @@ fcov:
           --core ibex \
           --dir ${OUT}/rtl_sim \
           -o ${OUT}/fcov \
-          ${RISCV_DV_OPTS} \
+          --custom_target ${DV_DIR}/riscv_dv_extension \
 
 # Load verdi to review coverage
 cov:
diff --git a/dv/uvm/riscv_dv_extension/cov_testlist.yaml b/dv/uvm/riscv_dv_extension/cov_testlist.yaml
new file mode 100644
index 00000000..b1ade51d
--- /dev/null
+++ b/dv/uvm/riscv_dv_extension/cov_testlist.yaml
@@ -0,0 +1,18 @@
+- test: riscv_instr_cov_debug_test
+  description: >
+    Functional coverage debug test, this is not a functional test to the core.
+  iterations: 1
+  gen_test: riscv_instr_cov_debug_test
+  no_iss: 1
+  no_gcc: 1
+  no_post_compare: 1
+
+- test: riscv_instr_cov_test
+  description: >
+    Parse the instruction information from the CSV trace log, sample functional
+    coverage from the instruction trace.
+  iterations: 1
+  gen_test: riscv_instr_cov_test
+  no_iss: 1
+  no_gcc: 1
+  no_post_compare: 1
diff --git a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
index 128c6f9e..54fa136e 100644
--- a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
+++ b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
@@ -64,7 +64,6 @@ def process_ibex_sim_log(ibex_log, csv, full_trace = 1):
 
                 # Extract all missing operand values
                 if full_trace:
-                  logging.info("full trace enabled")
                   o = re.search(r"(?P<instr_name>[a-z.]*)\s+(?P<operands>.*)", rv_instr_trace.instr_str)
                   if o:
                     operands = o.group("operands").split(",")