diff --git a/controller.sv b/controller.sv
index c5cafe9f..3d123a54 100644
--- a/controller.sv
+++ b/controller.sv
@@ -830,7 +830,8 @@ module controller
 
       `OPCODE_HWLOOP: begin // hardware loop instructions
         unique case (instr_rdata_i[14:12])
-          3'b000: begin // lp.starti set start address
+          3'b000: begin
+            // lp.starti set start address
             hwloop_wb_mux_sel_o = 1'b1;
             hwloop_we_o[0]      = 1'b1;                     // set we for start addr reg
             alu_op_a_mux_sel_o  = `OP_A_CURRPC;
@@ -838,7 +839,8 @@ module controller
             alu_operator        = `ALU_ADD;
             // $display("%t: hwloop start address: %h", $time, instr_rdata_i);
           end
-          3'b001: begin // lp.endi set end address
+          3'b001: begin
+            // lp.endi set end address
             hwloop_wb_mux_sel_o = 1'b1;
             hwloop_we_o[1]      = 1'b1;                     // set we for end addr reg
             alu_op_a_mux_sel_o  = `OP_A_CURRPC;
@@ -846,18 +848,22 @@ module controller
             alu_operator        = `ALU_ADD;
             // $display("%t: hwloop end address: %h", $time, instr_rdata_i);
           end
-          3'b010: begin // lp.count initialize counter from register
+          3'b010: begin
+            // lp.count initialize counter from rs1
             hwloop_cnt_mux_sel_o = 2'b11;
-            hwloop_we_o[2]       = 1'b1;                     // set we for counter reg
+            hwloop_we_o[2]       = 1'b1;
             rega_used            = 1'b1;
             // $display("%t: hwloop counter: %h", $time, instr_rdata_i);
           end
-          3'b011: begin // lp.counti initialize counter from immediate
+          3'b011: begin
+            // lp.counti initialize counter from I-type immediate
             hwloop_cnt_mux_sel_o = 2'b01;
-            hwloop_we_o[2]       = 1'b1;                     // set we for counter reg
+            hwloop_we_o[2]       = 1'b1;
             // $display("%t: hwloop counter imm: %h", $time, instr_rdata_i);
           end
-          3'b100: begin // lp.setup
+          3'b100: begin
+            // lp.setup: initialize counter from rs1, set start address to
+            // next instruction and end address to PC + I-type immediate
             hwloop_wb_mux_sel_o  = 1'b0;
             hwloop_cnt_mux_sel_o = 2'b11;
             hwloop_we_o          = 3'b111;                     // set we for counter/start/end reg
@@ -868,7 +874,10 @@ module controller
             rega_used            = 1'b1;
             // $display("%t: hwloop setup: %h", $time, instr_rdata_i);
           end
-          3'b101: begin // lp.setupi
+          3'b101: begin
+            // lp.setupi: initialize counter from I-type immediate, set start
+            // address to next instruction and end address to PC + shifted
+            // z-type immediate
             hwloop_wb_mux_sel_o  = 1'b0;
             hwloop_cnt_mux_sel_o = 2'b10;
             hwloop_we_o          = 3'b111;                     // set we for counter/start/end reg
diff --git a/id_stage.sv b/id_stage.sv
index 91c64030..18e09b95 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -328,11 +328,10 @@ module id_stage
   always_comb
   begin : hwloop_cnt_mux
     unique case (hwloop_cnt_mux_sel)
-      2'b00:   hwloop_cnt = 32'b0;
-      2'b01:   hwloop_cnt = imm_i_type;
-      2'b10:   hwloop_cnt = 32'b0;
+      2'b00:   hwloop_cnt = imm_i_type;
+      2'b01:   hwloop_cnt = { imm_z_type[30:0], 1'b0 };
       2'b11:   hwloop_cnt = operand_a_fw_id;
-    endcase; // case (hwloop_cnt_mux_sel)
+    endcase;
   end
 
   // hwloop register id
diff --git a/riscv_core.sv b/riscv_core.sv
index a5b8da56..44d21927 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -180,7 +180,7 @@ module riscv_core
   logic        save_pc_id;
 
 
-  // hwloop data from ALU
+  // Hardware loop data from ALU
   logic [31:0] hwlp_cnt_ex;        // from id to ex stage (hwloop_regs)
   logic [2:0]  hwlp_we_ex;         // from id to ex stage (hwloop_regs)
   logic [1:0]  hwlp_regid_ex;      // from id to ex stage (hwloop_regs)
@@ -189,14 +189,7 @@ module riscv_core
   logic [31:0] hwlp_end_data_ex;   // hwloop data to write to hwloop_regs
   logic [31:0] hwlp_cnt_data_ex;   // hwloop data to write to hwloop_regs
 
-  // Access to hwloop registers
-  logic [31:0] hwlp_start_data;
-  logic [31:0] hwlp_end_data;
-  logic [31:0] hwlp_cnt_data;
-  logic [2:0]  hwlp_we;
-  logic [1:0]  hwlp_regid;
-
-  // hwloop controller signals
+  // Hardware loop controller signals
   logic [`HWLOOP_REGS-1:0] [31:0] hwlp_start_addr;  // to hwloop controller
   logic [`HWLOOP_REGS-1:0] [31:0] hwlp_end_addr;    // to hwloop controller
   logic [`HWLOOP_REGS-1:0] [31:0] hwlp_counter;     // to hwloop controller
@@ -612,11 +605,11 @@ module riscv_core
     .rst_n                   ( rst_n               ),
 
     // from ex stage
-    .hwloop_start_data_i     ( hwlp_start_data     ),
-    .hwloop_end_data_i       ( hwlp_end_data       ),
-    .hwloop_cnt_data_i       ( hwlp_cnt_data       ),
-    .hwloop_we_i             ( hwlp_we             ),
-    .hwloop_regid_i          ( hwlp_regid          ),
+    .hwloop_start_data_i     ( hwlp_start_data_ex  ),
+    .hwloop_end_data_i       ( hwlp_end_data_ex    ),
+    .hwloop_cnt_data_i       ( hwlp_cnt_data_ex    ),
+    .hwloop_we_i             ( hwlp_we_ex          ),
+    .hwloop_regid_i          ( hwlp_regid_ex       ),
 
     // from controller
     .stall_id_i              ( stall_id            ),
@@ -630,12 +623,6 @@ module riscv_core
     .hwloop_dec_cnt_i        ( hwlp_dec_cnt        )
   );
 
-  assign hwlp_start_data = hwlp_start_data_ex;
-  assign hwlp_end_data   = hwlp_end_data_ex;
-  assign hwlp_cnt_data   = hwlp_cnt_data_ex;
-  assign hwlp_regid      = hwlp_regid_ex;
-  assign hwlp_we         = hwlp_we_ex;
-
 
   /////////////////////////////////////////////////////////////
   //  ____  _____ ____  _   _  ____   _   _ _   _ ___ _____  //