diff --git a/alu.sv b/alu.sv
index 95da1135..e8c29a31 100644
--- a/alu.sv
+++ b/alu.sv
@@ -31,7 +31,6 @@
 
 module alu
 (
-   // Inputs of the ALU
    input  logic [`ALU_OP_WIDTH-1:0] operator_i,
    input  logic [31:0]              operand_a_i,
    input  logic [31:0]              operand_b_i,
diff --git a/ex_stage.sv b/ex_stage.sv
index f52063fe..580cd570 100644
--- a/ex_stage.sv
+++ b/ex_stage.sv
@@ -27,9 +27,6 @@
 //                                                                            //
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
-// int = internal signals
-// wb  = writeback
-// sp  = special registers
 
 `include "defines.sv"
 
@@ -100,15 +97,16 @@ module ex_stage
 
 
   // Internal output of the LU
-  logic [31:0]  alu_result;
+  logic [31:0] alu_result;
+  logic        alu_flag;
 
-  logic [31:0]  alu_adder_lsu_int; // to LS unit
+  logic [31:0] alu_adder_lsu_int; // to LS unit
 
-  logic [31:0]  mult_result;
+  logic [31:0] mult_result;
 
 
-  assign regfile_alu_we_fw_o       = regfile_alu_we_i;
-  assign regfile_alu_waddr_fw_o    = regfile_alu_waddr_i;
+  assign regfile_alu_we_fw_o    = regfile_alu_we_i;
+  assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
 
   always_comb
   begin
@@ -139,7 +137,7 @@ module ex_stage
   assign hwloop_cnt_data_o = hwloop_cnt_i;
 
   // Branch is taken when result[0] == 1'b1
-  assign branch_decision_o = alu_result[0];
+  assign branch_decision_o = alu_flag;
   assign jump_target_o     = alu_operand_c_i;
 
 
@@ -163,7 +161,8 @@ module ex_stage
 
    .adder_lsu_o   ( alu_adder_lsu_int   ),
 
-   .result_o      ( alu_result          )
+   .result_o      ( alu_result          ),
+   .flag_o        ( alu_flag            )
   );
 
 
diff --git a/exc_controller.sv b/exc_controller.sv
index 120e658e..5176255e 100644
--- a/exc_controller.sv
+++ b/exc_controller.sv
@@ -97,9 +97,9 @@ module exc_controller
   // - illegal instruction exception and IIE bit is set
   // - IRQ and INTE bit is set and no exception is currently running
   // - Debuger requests halt
-  assign trap_hit_o    = trap_insn_i || dbg_flush_pipe_i || dbg_st_en_i || (illegal_insn_i & dbg_dsr_i[`DSR_IIE]) || (irq_present_o & dbg_dsr_i[`DSR_INTE] & (~exc_running_p));
+  assign trap_hit_o    = trap_insn_i || dbg_flush_pipe_i || dbg_st_en_i || (illegal_insn_i && dbg_dsr_i[`DSR_IIE]) || (irq_present_o && dbg_dsr_i[`DSR_INTE] && (~exc_running_p));
 
-  assign irq_present_o = (irq_i || irq_nm_i) & irq_enable_i;
+  assign irq_present_o = (irq_i || irq_nm_i) && irq_enable_i;
 
   // Decoder for exc_reason signal
   // this signal tells the exception controller which is the exception