diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
index 5efbf270..f7449ec1 100644
--- a/examples/fpga/artya7/rtl/top_artya7.sv
+++ b/examples/fpga/artya7/rtl/top_artya7.sv
@@ -8,10 +8,13 @@ module top_artya7 (
     output [3:0]        LED
 );
 
-  parameter int          MEM_SIZE     = 256 * 1024; // 256 kB
-  parameter logic [31:0] MEM_START    = 32'h00000000;
-  parameter logic [31:0] MEM_MASK     = MEM_SIZE-1;
-  parameter              SRAMInitFile = "";
+  parameter int          FPGAPowerAnalysis = 0;
+  // Choose 64kb memory for normal builds and 256kb for FPGAPowerAnalysis builds. The latter will
+  // not fit in the Arty A7-35 Board FPGA.
+  parameter int          MEM_SIZE          = FPGAPowerAnalysis == 0 ? 64 * 1024 : 256 * 1024;
+  parameter logic [31:0] MEM_START         = 32'h00000000;
+  parameter logic [31:0] MEM_MASK          = MEM_SIZE-1;
+  parameter              SRAMInitFile      = "";
 
   logic clk_sys, rst_sys_n;