diff --git a/dv/uvm/tb/prim_clock_gating.sv b/dv/uvm/tb/prim_clock_gating.sv
index 9ebb18e2..3a8b7458 100644
--- a/dv/uvm/tb/prim_clock_gating.sv
+++ b/dv/uvm/tb/prim_clock_gating.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Dummy clock gating module
+// Dummy clock gating module compatible with latch-based register file
 
 module prim_clock_gating #(
     parameter Impl = "default"
@@ -13,6 +13,14 @@ module prim_clock_gating #(
     output logic clk_o
 );
 
-  assign clk_o = en_i ? clk_i : 0;
+  logic clk_en;
+
+  always_latch begin
+    if (clk_i == 1'b0) begin
+      clk_en <= en_i | test_en_i;
+    end
+  end
+
+  assign clk_o = clk_i & clk_en;
 
 endmodule