diff --git a/dv/riscv_compliance/ibex_riscv_compliance.core b/dv/riscv_compliance/ibex_riscv_compliance.core
index d86bcfbe..c6b03044 100644
--- a/dv/riscv_compliance/ibex_riscv_compliance.core
+++ b/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -9,13 +9,11 @@ filesets:
     depend:
       - lowrisc:dv_verilator:simutil_verilator
       - lowrisc:ibex:ibex_core_tracing
+      - lowrisc:ibex:sim_shared
 
     files:
       - rtl/ibex_riscv_compliance.sv
       - ibex_riscv_compliance.cc: { file_type: cppSource }
-      - rtl/prim_clock_gating.sv
-      - rtl/ram_1p.sv
-      - rtl/bus.sv
       - rtl/riscv_testutil.sv
     file_type: systemVerilogSource
 
diff --git a/dv/riscv_compliance/rtl/bus.sv b/shared/rtl/bus.sv
similarity index 100%
rename from dv/riscv_compliance/rtl/bus.sv
rename to shared/rtl/bus.sv
diff --git a/dv/riscv_compliance/rtl/prim_clock_gating.sv b/shared/rtl/prim_clock_gating.sv
similarity index 100%
rename from dv/riscv_compliance/rtl/prim_clock_gating.sv
rename to shared/rtl/prim_clock_gating.sv
diff --git a/dv/riscv_compliance/rtl/ram_1p.sv b/shared/rtl/ram_1p.sv
similarity index 100%
rename from dv/riscv_compliance/rtl/ram_1p.sv
rename to shared/rtl/ram_1p.sv
diff --git a/shared/sim_shared.core b/shared/sim_shared.core
new file mode 100644
index 00000000..cf4aa080
--- /dev/null
+++ b/shared/sim_shared.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ibex:sim_shared"
+description: "Collection of useful RTL for building simulations"
+filesets:
+  files_sim_sv:
+    files:
+      - ./rtl/prim_clock_gating.sv
+      - ./rtl/ram_1p.sv
+      - ./rtl/bus.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_sim_sv
+