diff --git a/riscv_core.sv b/riscv_core.sv
index 146f0795..dbc56e7c 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -767,6 +767,8 @@ module riscv_core
     .clk              ( clk                                  ),
     .rst_n            ( rst_n                                ),
 
+    .fetch_enable     ( fetch_enable_i                       ),
+    .boot_addr        ( boot_addr_i                          ),
     .core_id          ( core_id_i                            ),
     .cluster_id       ( cluster_id_i                         ),
 
diff --git a/riscv_simchecker.sv b/riscv_simchecker.sv
index 02863594..994c9c86 100644
--- a/riscv_simchecker.sv
+++ b/riscv_simchecker.sv
@@ -33,6 +33,8 @@ module riscv_simchecker
   input  logic        clk,
   input  logic        rst_n,
 
+  input  logic        fetch_enable,
+  input  logic [31:0] boot_addr,
   input  logic [4:0]  core_id,
   input  logic [4:0]  cluster_id,
 
@@ -110,8 +112,9 @@ module riscv_simchecker
   // simchecker initialization
   initial
   begin
-    #1;
-    dpi_simdata = riscv_checker_init(32'h80, core_id, cluster_id);
+    wait(rst_n == 1'b1);
+    wait(fetch_enable == 1'b1);
+    dpi_simdata = riscv_checker_init(boot_addr, core_id, cluster_id);
   end
 
   // virtual ID/EX pipeline