diff --git a/rtl/ibex_alu.sv b/rtl/ibex_alu.sv
index 1438ff5c..695eb821 100644
--- a/rtl/ibex_alu.sv
+++ b/rtl/ibex_alu.sv
@@ -228,11 +228,12 @@ module ibex_alu #(
   logic [5:0] shift_amt;
   logic [5:0] shift_amt_compl; // complementary shift amount (32 - shift_amt)
 
-  logic [31:0] shift_operand;
-  logic [32:0] shift_result_ext;
-  logic        unused_shift_result_ext;
-  logic [31:0] shift_result;
-  logic [31:0] shift_result_rev;
+  logic        [31:0] shift_operand;
+  logic signed [32:0] shift_result_ext_signed;
+  logic        [32:0] shift_result_ext;
+  logic               unused_shift_result_ext;
+  logic        [31:0] shift_result;
+  logic        [31:0] shift_result_rev;
 
   // zbf
   logic bfp_op;
@@ -319,9 +320,9 @@ module ibex_alu #(
       endcase
     end
 
-    shift_result_ext =
-        $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>>
-                  shift_amt[4:0]);
+    shift_result_ext_signed =
+        $signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0];
+    shift_result_ext = $unsigned(shift_result_ext_signed);
 
     shift_result            = shift_result_ext[31:0];
     unused_shift_result_ext = shift_result_ext[32];
diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv
index c209642b..2ab41a2d 100644
--- a/rtl/ibex_controller.sv
+++ b/rtl/ibex_controller.sv
@@ -823,8 +823,10 @@ module ibex_controller #(
   // FCOV //
   //////////
   `FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN));
-  `FCOV_SIGNAL(logic, debug_entry_if, (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF));
-  `FCOV_SIGNAL(logic, debug_entry_id, (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID));
+  `FCOV_SIGNAL(logic, debug_entry_if,
+      (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF));
+  `FCOV_SIGNAL(logic, debug_entry_id,
+      (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID));
   `FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH));
 
   ////////////////
diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv
index 738d3620..abf4088f 100644
--- a/rtl/ibex_cs_registers.sv
+++ b/rtl/ibex_cs_registers.sv
@@ -1284,6 +1284,9 @@ module ibex_cs_registers #(
     logic [DbgHwBreakNum-1:0] tmatch_control_q;
     logic [31:0]              tmatch_value_d;
     logic [31:0]              tmatch_value_q[DbgHwBreakNum];
+    logic                     selected_tmatch_control;
+    logic [31:0]              selected_tmatch_value;
+
     // Write enables
     logic                     tselect_we;
     logic [DbgHwBreakNum-1:0] tmatch_control_we;
@@ -1355,26 +1358,35 @@ module ibex_cs_registers #(
     localparam int unsigned TSelectRdataPadlen = DbgHwNumLen >= 32 ? 0 : (32 - DbgHwNumLen);
     assign tselect_rdata = {{TSelectRdataPadlen{1'b0}}, tselect_q};
 
+    if (DbgHwBreakNum > 1) begin : g_dbg_tmatch_multiple_select
+      assign selected_tmatch_control = tmatch_control_q[tselect_q];
+      assign selected_tmatch_value   = tmatch_value_q[tselect_q];
+    end else begin : g_dbg_tmatch_single_select
+      assign selected_tmatch_control = tmatch_control_q[0];
+      assign selected_tmatch_value   = tmatch_value_q[0];
+    end
+
     // TDATA0 - only support simple address matching
-    assign tmatch_control_rdata = {4'h2,                         // type    : address/data match
-                                   1'b1,                         // dmode   : access from D mode only
-                                   6'h00,                        // maskmax : exact match only
-                                   1'b0,                         // hit     : not supported
-                                   1'b0,                         // select  : address match only
-                                   1'b0,                         // timing  : match before execution
-                                   2'b00,                        // sizelo  : match any access
-                                   4'h1,                         // action  : enter debug mode
-                                   1'b0,                         // chain   : not supported
-                                   4'h0,                         // match   : simple match
-                                   1'b1,                         // m       : match in m-mode
-                                   1'b0,                         // 0       : zero
-                                   1'b0,                         // s       : not supported
-                                   1'b1,                         // u       : match in u-mode
-                                   tmatch_control_q[tselect_q],  // execute : match instruction address
-                                   1'b0,                         // store   : not supported
-                                   1'b0};                        // load    : not supported
+    assign tmatch_control_rdata = {4'h2,                    // type    : address/data match
+                                   1'b1,                    // dmode   : access from D mode only
+                                   6'h00,                   // maskmax : exact match only
+                                   1'b0,                    // hit     : not supported
+                                   1'b0,                    // select  : address match only
+                                   1'b0,                    // timing  : match before execution
+                                   2'b00,                   // sizelo  : match any access
+                                   4'h1,                    // action  : enter debug mode
+                                   1'b0,                    // chain   : not supported
+                                   4'h0,                    // match   : simple match
+                                   1'b1,                    // m       : match in m-mode
+                                   1'b0,                    // 0       : zero
+                                   1'b0,                    // s       : not supported
+                                   1'b1,                    // u       : match in u-mode
+                                   selected_tmatch_control, // execute : match instruction address
+                                   1'b0,                    // store   : not supported
+                                   1'b0};                   // load    : not supported
+
     // TDATA1 - address match value only
-    assign tmatch_value_rdata = tmatch_value_q[tselect_q];
+    assign tmatch_value_rdata = selected_tmatch_value;
 
     // Breakpoint matching
     // We match against the next address, as the breakpoint must be taken before execution
diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv
index b61520ed..84a3a8a2 100644
--- a/rtl/ibex_decoder.sv
+++ b/rtl/ibex_decoder.sv
@@ -151,6 +151,13 @@ module ibex_decoder #(
       end
     end
   end else begin : gen_no_rs3_flop
+    logic unused_clk;
+    logic unused_rst_n;
+
+    // Clock and reset unused when there's no rs3 flop
+    assign unused_clk = clk_i;
+    assign unused_rst_n = rst_ni;
+
     // always zero
     assign use_rs3_q = use_rs3_d;
   end