diff --git a/controller.sv b/controller.sv index e8e15ff9..cb960acb 100644 --- a/controller.sv +++ b/controller.sv @@ -299,6 +299,13 @@ module controller ctrl_fsm_ns = DECODE; end + // Store core ID in x18 (a0) // TODO: Temporary hack + alu_op_a_mux_sel_o = `OP_A_ZERO; + alu_op_b_mux_sel_o = `OP_B_IMM; + immediate_mux_sel_o = `IMM_CID; + alu_operator = `ALU_ADD; + regfile_alu_we = 1'b1; + // hwloop detected, jump to start address! // Attention: This has to be done in the DECODE and the FIRST_FETCH states if (hwloop_jump_i == 1'b1) @@ -1226,7 +1233,10 @@ module controller // Jump and Branch handling // //////////////////////////////////////////////////////////////////////////////////////////// + //assign force_nop_o = (jump_in_id_o != 2'b00)? 1'b1 : 1'b0; assign force_nop_o = (jump_in_id_o != 2'b00 || jump_in_ex_i != 2'b00)? 1'b1 : 1'b0; + //assign force_nop_o = (!instr_ack_stall && (jump_in_id_o != 2'b00 || jump_in_ex_i != 2'b00))? 1'b1 : 1'b0; + //assign force_nop_o = (!stall_ex_o && jump_in_id_o == 2'b01)? 1'b1 : 1'b0; assign drop_instruction_o = 1'b0; //////////////////////////////////////////////////////////////////////////////////////////// @@ -1237,8 +1247,8 @@ module controller // we unstall the if_stage if the debug unit wants to set a new // pc, so that the new value gets written into current_pc_if and is // used by the instr_core_interface - stall_if_o = (instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i | (~pc_valid_i)); - stall_id_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i; + stall_if_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i | (~pc_valid_i); + stall_id_o = instr_ack_stall | mfspr_stall | mtspr_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_stall_i; stall_ex_o = instr_ack_stall | lsu_stall | dbg_stall_i; stall_wb_o = lsu_stall | dbg_stall_i; end @@ -1293,6 +1303,12 @@ module controller operand_a_fw_mux_sel_o = `SEL_FW_EX; operand_b_fw_mux_sel_o = `SEL_REGFILE; end + + // Make sure x0 is never forwarded + if (instr_rdata_i[`REG_S1] == 5'b0) + operand_a_fw_mux_sel_o = `SEL_REGFILE; + if (instr_rdata_i[`REG_S2] == 5'b0) + operand_b_fw_mux_sel_o = `SEL_REGFILE; end // update registers diff --git a/ex_stage.sv b/ex_stage.sv index f05d5274..fd2cfde4 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -126,7 +126,7 @@ module ex_stage // To IF: Jump and branch target and decision output logic [31:0] jump_target_o, - output logic [1:0] jump_in_ex_o, + //output logic [1:0] jump_in_ex_o, output logic branch_decision_o `ifdef TCDM_ADDR_PRECAL @@ -269,7 +269,7 @@ module ex_stage regfile_rb_data_wb_o <= 32'h0000_0000; sp_we_wb_o <= 1'b0; eoc_o <= 1'b0; - jump_in_ex_o <= '0; + //jump_in_ex_o <= '0; end else begin @@ -282,7 +282,7 @@ module ex_stage regfile_rb_data_wb_o <= regfile_rb_data_i; sp_we_wb_o <= sp_we_i; eoc_o <= eoc_i; - jump_in_ex_o <= jump_in_id_i; + //jump_in_ex_o <= jump_in_id_i; end end end diff --git a/id_stage.sv b/id_stage.sv index de360a5a..44f4fe80 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -38,6 +38,8 @@ module id_stage input logic clk, input logic rst_n, + input logic [4:0] core_id_i, + input logic fetch_enable_i, output logic core_busy_o, @@ -49,7 +51,8 @@ module id_stage // Jumps and branches output logic [1:0] jump_in_id_o, - input logic [1:0] jump_in_ex_i, + //input logic [1:0] jump_in_ex_i, + output logic [1:0] jump_in_ex_o, // IF and ID stage signals //output logic [31:0] pc_from_immediate_o, // TODO: remove @@ -197,7 +200,9 @@ module id_stage // Signals running between controller and exception controller //logic jump_in_id; - //logic jump_in_ex; // registered copy of jump_in_id + logic jump_in_ex; // registered copy of jump_in_id + assign jump_in_ex_o = jump_in_ex; + logic illegal_insn; logic trap_insn; logic pipe_flush; @@ -453,6 +458,7 @@ module id_stage `IMM_S: immediate_b = imm_s_type; `IMM_U: immediate_b = imm_u_type; `IMM_HEX4: immediate_b = 32'h4; + `IMM_CID: immediate_b = core_id_i; // TODO: Temporary hack default: immediate_b = 32'h4; endcase; // case (immediate_mux_sel) end @@ -676,7 +682,7 @@ module id_stage .operand_c_fw_mux_sel_o ( operand_c_fw_mux_sel ), // To controller (TODO: Remove when control/decode separated and moved) - .jump_in_ex_i ( jump_in_ex_i ), + .jump_in_ex_i ( jump_in_ex_o ), // To EX: Jump/Branch indication .jump_in_id_o ( jump_in_id_o ), @@ -841,6 +847,8 @@ module id_stage hwloop_wb_mux_sel_ex_o <= 1'b0; hwloop_cnt_o <= 32'b0; + jump_in_ex <= 1'b0; + eoc_ex_o <= 1'b0; `ifdef TCDM_ADDR_PRECAL @@ -914,6 +922,8 @@ module id_stage hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel; hwloop_cnt_o <= hwloop_cnt; + jump_in_ex <= jump_in_id_o; + eoc_ex_o <= eoc; `ifdef TCDM_ADDR_PRECAL diff --git a/if_stage.sv b/if_stage.sv index f0a7a6d6..d252a2ff 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -178,6 +178,10 @@ module if_stage begin : ENABLED_PIPE current_pc_if_o <= next_pc; end + else if ( jump_in_ex_i == 2'b01 ) + begin + current_pc_if_o <= next_pc; + end end end diff --git a/include/defines.sv b/include/defines.sv index 12651ba4..e0ad2f35 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -343,10 +343,12 @@ endfunction // prettyPrintInstruction `define OP_C_JT 1'b1 // operand b immediate selection -`define IMM_I 2'b00 -`define IMM_S 2'b01 -`define IMM_U 2'b10 -`define IMM_HEX4 2'b11 +`define IMM_I 3'b000 +`define IMM_S 3'b001 +`define IMM_U 3'b010 +`define IMM_HEX4 3'b011 +`define IMM_CID 3'b100 // core id +`define IMM_CLID 3'b100 // cluster id /* not used: `define IMM_SB 3'b011 `define IMM_UJ 3'b101 diff --git a/riscv_core.sv b/riscv_core.sv index 582758c6..42e17a04 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -343,11 +343,13 @@ module riscv_core .clk ( clk ), .rst_n ( rst_n ), + .core_id_i ( core_id_i ), // TODO: Temporary hack + // Processor Enable .fetch_enable_i ( fetch_enable_i ), .jump_in_id_o ( jump_in_id ), - .jump_in_ex_i ( jump_in_ex ), + .jump_in_ex_o ( jump_in_ex ), .core_busy_o ( core_busy_o ), @@ -565,7 +567,7 @@ module riscv_core // To IF: Jump and branch target and decision .jump_target_o ( jump_target ), - .jump_in_ex_o ( jump_in_ex ), + //.jump_in_ex_o ( jump_in_ex ), .branch_decision_o ( branch_decision ), // To ID stage: Forwarding signals