diff --git a/alu.sv b/alu.sv
index 467a8a42..151f9aaf 100644
--- a/alu.sv
+++ b/alu.sv
@@ -908,7 +908,12 @@ module riscv_alu
       `ALU_GTU,   `ALU_GEU,
       `ALU_LTU,   `ALU_LEU,
       `ALU_GTS,   `ALU_GES,
-      `ALU_LTS,   `ALU_LES,
+      `ALU_LTS,   `ALU_LES: begin
+          result_o[31:24] = {8{cmp_result[3]}};
+          result_o[23:16] = {8{cmp_result[2]}};
+          result_o[15: 8] = {8{cmp_result[1]}};
+          result_o[ 7: 0] = {8{cmp_result[0]}};
+       end
       `ALU_SLTS,  `ALU_SLTU,
       `ALU_SLETS, `ALU_SLETU: result_o = {31'b0, comparison_result_o};
 
diff --git a/decoder.sv b/decoder.sv
index c4abe740..000b2537 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -795,9 +795,9 @@ module riscv_decoder
           // comparisons, always have bit 26 set
           6'b00000_1: begin alu_operator_o = `ALU_EQ;  imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmpeq
           6'b00001_1: begin alu_operator_o = `ALU_NE;  imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmpne
-          6'b00010_1: begin alu_operator_o = `ALU_GTU; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmpgt
+          6'b00010_1: begin alu_operator_o = `ALU_GTS; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmpgt
           6'b00011_1: begin alu_operator_o = `ALU_GES; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmpge
-          6'b00100_1: begin alu_operator_o = `ALU_LTU; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmplt
+          6'b00100_1: begin alu_operator_o = `ALU_LTS; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmplt
           6'b00101_1: begin alu_operator_o = `ALU_LES; imm_b_mux_sel_o     = `IMMB_VS; end // pv.cmple
           6'b00110_1: begin alu_operator_o = `ALU_GTU; imm_b_mux_sel_o     = `IMMB_VU; end // pv.cmpgtu
           6'b00111_1: begin alu_operator_o = `ALU_GEU; imm_b_mux_sel_o     = `IMMB_VU; end // pv.cmpgeu