From 4b952c8264c479f2571c14960a3d6234137624a1 Mon Sep 17 00:00:00 2001 From: udinator Date: Mon, 16 Mar 2020 09:07:50 -0700 Subject: [PATCH] [dv] coverage generation (#704) Signed-off-by: Udi --- dv/uvm/core_ibex/Makefile | 27 ++++++------ dv/uvm/core_ibex/sim.py | 50 +++++++++++++++++++++-- dv/uvm/core_ibex/yaml/rtl_simulation.yaml | 2 +- 3 files changed, 63 insertions(+), 16 deletions(-) diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile index 6c9d0854..060ca4d4 100644 --- a/dv/uvm/core_ibex/Makefile +++ b/dv/uvm/core_ibex/Makefile @@ -89,7 +89,7 @@ all: sim instr: iss_sim -sim: post_compare +sim: post_compare cov .PHONY: clean clean: @@ -101,7 +101,7 @@ COMMON_OPTS := $(if $(call equal,$(VERBOSE),1),--verbose,) # Options for all targets that depend on the tests we're running. TEST_OPTS := $(COMMON_OPTS) \ --seed=${SEED} \ - --test"=${TEST}" \ + --test="${TEST}" \ --testlist=${TESTLIST} \ --iterations=${ITERATIONS} @@ -386,7 +386,7 @@ $(OUT-SEED)/regr.log: \ post_compare: $(OUT-SEED)/regr.log ############################################################################### -# Generate functional coverage +# Generate RISCV-DV functional coverage fcov: python3 ${GEN_DIR}/cov.py \ --core ibex \ @@ -395,12 +395,15 @@ fcov: --isa rv32imc \ --custom_target riscv_dv_extension -# Load verdi to review coverage -cov_vcs: - cd ${OUT}/rtl_sim; verdi -cov -covdir test.vdb & - -cov_ius: - if [ ! -d "${OUT}/rtl_sim/cov_work/scope/merged_cov" ]; \ - then imc -execcmd "merge -out ${OUT}/rtl_sim/cov_work/scope/merged_cov ${OUT}/rtl_sim/cov_work/scope/test_*"; \ - fi - imc -load ${OUT}/rtl_sim/cov_work/scope/merged_cov & +# Merge coverage in the directory +cov: + @rm -rf ${OUT}/rtl_sim/test.vdb + @./sim.py \ + --steps=cov \ + ${TEST_OPTS} \ + --simulator="${SIMULATOR}" \ + --o="${OUT}" \ + --lsf_cmd="${LSF_CMD}"; + @if [ -d "test.vdb" ]; then \ + mv -f test.vdb ./${OUT}/rtl_sim/; \ + fi diff --git a/dv/uvm/core_ibex/sim.py b/dv/uvm/core_ibex/sim.py index dc74a93d..1aff1024 100755 --- a/dv/uvm/core_ibex/sim.py +++ b/dv/uvm/core_ibex/sim.py @@ -227,7 +227,9 @@ def get_test_sim_cmd(base_cmd, test, idx, output_dir, bin_dir, lsf_cmd): { 'sim_dir': sim_dir, 'rtl_test': test['rtl_test'], - 'binary': binary + 'binary': binary, + 'test_name': test_name, + 'iteration': str(idx) }) if not os.path.exists(binary): @@ -413,6 +415,43 @@ def compare(test_list, iss, output_dir): return fails == 0 +#TODO(udinator) - support IUS, DSim, and Riviera +def gen_cov(base_dir, simulator, lsf_cmd): + """Generate a merged coverage directory. + + Args: + base_dir: the base simulation output directory (default: out/) + simulator: the chosen RTL simulator + lsf_cmd: command to run on LSF + + """ + # Compile a list of all output seed-###/rtl_sim/test.vdb directories + dir_list = [] + for entry in os.scandir(base_dir): + vdb_path = "%s/%s/rtl_sim/test.vdb" % (base_dir, entry.name) + if 'seed' in entry.name: + logging.info("Searching %s/%s for coverage database" % + (base_dir, entry.name)) + if os.path.exists(vdb_path): + dir_list.append(vdb_path) + if dir_list == []: + logging.info("No coverage data available, exiting...") + sys.exit(RET_SUCCESS) + + if simulator == 'vcs': + cov_cmd = "urg -full64 -format both -dbname test.vdb " \ + "-report %s/rtl_sim/urgReport -dir" % base_dir + for cov_dir in dir_list: + cov_cmd += " %s" % cov_dir + logging.info("Generating merged coverage directory") + if lsf_cmd is not None: + cov_cmd = lsf_cmd + ' ' + cov_cmd + run_cmd(cov_cmd) + else: + logging.error("%s is an unsuported simulator! Exiting..." % simulator) + sys.exit(RET_FAIL) + + def main(): '''Entry point when run as a script''' @@ -452,7 +491,7 @@ def main(): parser.add_argument("--en_wave", action='store_true', help="Enable waveform dump") parser.add_argument("--steps", type=str, default="all", - help="Run steps: compile,sim,compare") + help="Run steps: compile,sim,compare,cov") parser.add_argument("--lsf_cmd", type=str, help=("LSF command. Run locally if lsf " "command is not specified")) @@ -469,7 +508,8 @@ def main(): steps = { 'compile': args.steps == "all" or 'compile' in args.steps, 'sim': args.steps == "all" or 'sim' in args.steps, - 'compare': args.steps == "all" or 'compare' in args.steps + 'compare': args.steps == "all" or 'compare' in args.steps, + 'cov': args.steps == "all" or 'cov' in args.steps } compile_cmds = [] @@ -521,6 +561,10 @@ def main(): if not compare(matched_list, args.iss, args.o): return RET_FAIL + # Generate merged coverage directory and load it into appropriate GUI + if steps['cov']: + gen_cov(args.o, args.simulator, args.lsf_cmd) + return RET_SUCCESS diff --git a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml index 698c51b5..87e7c870 100644 --- a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml +++ b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml @@ -46,7 +46,7 @@ -cm_dir /test.vdb -cm_log /dev/null -assert nopostproc - -cm_name test_ + -cm_name test__ wave_opts: > -ucli -do /vcs.tcl