diff --git a/compressed_decoder.sv b/compressed_decoder.sv
index 5e2431c9..3d48f20a 100644
--- a/compressed_decoder.sv
+++ b/compressed_decoder.sv
@@ -95,7 +95,8 @@ module compressed_decoder
               5'b01111: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], `OPCODE_OP};
 
               // c.sra
-              // c.slt
+              // c.slt -> slt rd', rd', rs2'
+              5'b00110: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[9:7], `OPCODE_OP};
               // c.sltr
               default:  illegal_instr_o = 1'b1;
             endcase
diff --git a/id_stage.sv b/id_stage.sv
index 3872f9f8..3714fa78 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -160,7 +160,6 @@ module id_stage
 
   // Compressed instruction decoding
   logic [31:0] instr;
-  logic        illegal_compressed_instr;
 
   // Immediate decoding and sign extension
   logic [31:0] imm_i_type;