diff --git a/dv/uvm/env/core_ibex_env_cfg.sv b/dv/uvm/env/core_ibex_env_cfg.sv
index d91474df..8c352d86 100644
--- a/dv/uvm/env/core_ibex_env_cfg.sv
+++ b/dv/uvm/env/core_ibex_env_cfg.sv
@@ -15,7 +15,7 @@ class core_ibex_env_cfg extends uvm_object;
   function new(string name = "");
     super.new(name);
     void'($value$plusargs("enable_irq_seq=%0d", enable_irq_seq));
-    void'($value$plusargs("enable_deug_seq=%0d", enable_debug_seq));
+    void'($value$plusargs("enable_debug_seq=%0d", enable_debug_seq));
   endfunction
 
 endclass
diff --git a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
index 547a822d..5377deaa 100644
--- a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
+++ b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
@@ -30,7 +30,7 @@ def process_ibex_sim_log(ibex_log, csv):
             # Extract instruction infromation
             m = re.search(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+) " \
                           "(?P<pc>[0-9a-f]+) (?P<bin>[0-9a-f]+) (?P<instr>.*)" \
-                          "x(?P<rd>\d+)=(?P<val>[0-9a-f]+)", line)
+                          "x(?P<rd>\d+)=0x(?P<val>[0-9a-f]+)", line)
             if m:
                 # Write the extracted instruction to a csvcol buffer file
                 rv_instr_trace = RiscvInstructiontTraceEntry()
@@ -40,7 +40,6 @@ def process_ibex_sim_log(ibex_log, csv):
                 rv_instr_trace.binary = m.group("bin")
                 rv_instr_trace.instr_str = m.group("instr")
                 trace_csv.write_trace_entry(rv_instr_trace)
-                #print("Processed instruction[%d] : %0s" % (instr_cnt, m.group("instr")))
                 instr_cnt += 1
 
     print("Processed instruction count : %d" % instr_cnt)