From 501cc2bb62906eb7ebc9d638d6a42695b08871ab Mon Sep 17 00:00:00 2001
From: Pirmin Vogel <vogelpi@lowrisc.org>
Date: Tue, 20 Aug 2019 14:50:21 +0100
Subject: [PATCH] ram_1p.sv: Fix rvalid_o generation

This signal must also be set in case of write transactions as it is
a request valid and not a read valid.
---
 examples/fpga/artya7-100/rtl/ram_1p.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/fpga/artya7-100/rtl/ram_1p.sv b/examples/fpga/artya7-100/rtl/ram_1p.sv
index 98b56c1e..eaf131cc 100644
--- a/examples/fpga/artya7-100/rtl/ram_1p.sv
+++ b/examples/fpga/artya7-100/rtl/ram_1p.sv
@@ -42,7 +42,7 @@ module ram_1p #(
     if (!rst_ni) begin
       rvalid_o <= '0;
     end else begin
-      rvalid_o <= req_i && ~write_i;
+      rvalid_o <= req_i;
     end
   end