From 52b03f363787806e977b2f19cd8722a4e724d740 Mon Sep 17 00:00:00 2001 From: Pirmin Vogel Date: Tue, 12 Nov 2019 17:42:55 +0100 Subject: [PATCH] [rtl/controller] Remove redundant check in EBREAK handling This commit removes a redundant for `ebrk_insn` in the `DBG_TAKEN_ID` state. If this signal is not set, the controller does not enter this state in the first place. This is not changing functional behavior, but removes a `MISSING_ELSE` coverage hole reported by @udinator. Signed-off-by: Pirmin Vogel --- rtl/ibex_controller.sv | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv index 732bc84c..4b02a26f 100644 --- a/rtl/ibex_controller.sv +++ b/rtl/ibex_controller.sv @@ -450,28 +450,26 @@ module ibex_controller ( // // for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39] // jump to debug exception handler in debug memory - if (ebrk_insn) begin - flush_id = 1'b1; - pc_mux_o = PC_EXC; - pc_set_o = 1'b1; - exc_pc_mux_o = EXC_PC_DBD; + flush_id = 1'b1; + pc_mux_o = PC_EXC; + pc_set_o = 1'b1; + exc_pc_mux_o = EXC_PC_DBD; - // update dcsr and dpc - if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry + // update dcsr and dpc + if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry - // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage) - csr_save_cause_o = 1'b1; - csr_save_id_o = 1'b1; + // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage) + csr_save_cause_o = 1'b1; + csr_save_id_o = 1'b1; - // dcsr - debug_csr_save_o = 1'b1; - debug_cause_o = DBG_CAUSE_EBREAK; - end - - // enter debug mode - debug_mode_d = 1'b1; + // dcsr + debug_csr_save_o = 1'b1; + debug_cause_o = DBG_CAUSE_EBREAK; end + // enter debug mode + debug_mode_d = 1'b1; + ctrl_fsm_ns = DECODE; end