diff --git a/dv/uvm/riscv_dv_extension/ibex_core_setting.sv b/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
index 4f4c5987..fc8d572f 100644
--- a/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
+++ b/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
@@ -46,25 +46,7 @@ bit support_umode_trap = 0;
 // Support sfence.vma instruction
 bit support_sfence = 0;
 
-// Cache line size (in bytes)
-// If processor does not support caches, set to XLEN/8
-int dcache_line_size_in_bytes = 128;
-
-// Number of data section
-// For processor that doesn't have data TLB, this can be set to 1
-// For processor that supports data TLB, this should be set to be larger than the number
-// of entries of dTLB to cover dTLB hit/miss scenario
-int num_of_data_pages = 4;
-
-// Data section byte size
-// For processor with no dTLB and data cache, keep the value below 10K
-// For processor with dTLB support, set it to the physical memory size that covers one entry
-// of the dTLB
-int data_page_size = 4096;
-int data_page_alignment = $clog2(data_page_size);
-
-// Stack section word length
-int stack_len = 5000;
+int max_interrupt_vector_num = 32;
 
 //-----------------------------------------------------------------------------
 // Kernel section setting, used by supervisor mode programs
diff --git a/dv/uvm/riscv_dv_extension/testlist.yaml b/dv/uvm/riscv_dv_extension/testlist.yaml
index d21b79e2..cdb4c5aa 100644
--- a/dv/uvm/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/riscv_dv_extension/testlist.yaml
@@ -39,8 +39,7 @@
     +directed_instr_1=riscv_loop_instr,4
     +directed_instr_2=riscv_hazard_instr_stream,4
     +directed_instr_3=riscv_load_store_hazard_instr_stream,4
-    +directed_instr_4=riscv_cache_line_stress_instr_stream,4
-    +directed_instr_5=riscv_multi_page_load_store_instr_stream,4
+    +directed_instr_4=riscv_multi_page_load_store_instr_stream,4
   rtl_test: core_ibex_base_test
 
 - test: riscv_rand_jump_test
@@ -65,8 +64,7 @@
     +num_of_sub_program=5
     +directed_instr_0=riscv_load_store_rand_instr_stream,40
     +directed_instr_1=riscv_load_store_hazard_instr_stream,40
-    +directed_instr_2=riscv_cache_line_stress_instr_stream,40
-    +directed_instr_3=riscv_multi_page_load_store_instr_stream,40
+    +directed_instr_2=riscv_multi_page_load_store_instr_stream,40
   rtl_test: core_ibex_base_test
 
 - test: riscv_illegal_instr_test
@@ -78,7 +76,7 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +enable_illegal_instruction=1
+    +illegal_instr_ratio=5
   rtl_test: core_ibex_base_test
 
 - test: riscv_hint_instr_test
@@ -88,7 +86,7 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +enable_hint_instruction=1
+    +hint_instr_ratio=5
   rtl_test: core_ibex_base_test
 
 - test: riscv_ebreak_test
@@ -290,7 +288,6 @@
     +num_of_sub_program=5
     +directed_instr_0=riscv_load_store_rand_instr_stream,20
     +directed_instr_1=riscv_load_store_hazard_instr_stream,20
-    +directed_instr_2=riscv_cache_line_stress_instr_stream,20
-    +directed_instr_3=riscv_multi_page_load_store_instr_stream,20
+    +directed_instr_2=riscv_multi_page_load_store_instr_stream,20
     +enable_unaligned_load_store=1
   rtl_test: core_ibex_base_test
diff --git a/dv/uvm/sim.py b/dv/uvm/sim.py
index 02c501b5..33d75943 100644
--- a/dv/uvm/sim.py
+++ b/dv/uvm/sim.py
@@ -137,7 +137,7 @@ def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts, verbos
       os.chdir(sim_dir)
       if verbose:
         print("Run dir: %s" % sim_dir)
-      binary = ("%s/%s.%d.bin" % (bin_dir, test['test'], i))
+      binary = ("%s/%s_%d.bin" % (bin_dir, test['test'], i))
       cmd = lsf_cmd + " " + test_sim_cmd.rstrip() + \
             (" +UVM_TESTNAME=%s " % test['rtl_test']) + \
             (" +bin=%s " % binary) + \