diff --git a/id_stage.sv b/id_stage.sv index 2ece85b3..09dcf2af 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -269,7 +269,6 @@ module id_stage logic [31:0] operand_c; - assign force_nop_o = force_nop_exc; assign pc_mux_sel_o = (exc_pc_sel == 1'b1) ? `PC_EXCEPTION : pc_mux_sel_int; @@ -283,15 +282,12 @@ module id_stage ); - // immediate extraction and sign extension assign imm_i_type = { {20 {instr[31]}}, instr[31:20] }; assign imm_s_type = { {20 {instr[31]}}, instr[31:25], instr[11:7] }; - assign imm_sb_type = { {19 {instr[31]}}, instr[31], instr[7], - instr[30:25], instr[11:8], 1'b0 }; - assign imm_u_type = { instr[31:12], {12 {1'b0}} }; - assign imm_uj_type = { {12 {instr[31]}}, instr[19:12], - instr[20], instr[30:21], 1'b0 }; + assign imm_sb_type = { {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }; + assign imm_u_type = { instr[31:12], 12'b0 }; + assign imm_uj_type = { {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; // immediate for CSR manipulatin (zero extended) assign imm_z_type = { 27'b0, instr[`REG_S1] }; @@ -304,7 +300,7 @@ module id_stage // destination registers assign regfile_waddr_id = instr[`REG_D]; - //assign alu_vec_ext = instr[9:8]; TODO + //assign alu_vec_ext = instr[9:8]; TODO assign alu_vec_ext = '0; @@ -331,20 +327,30 @@ module id_stage assign current_pc = current_pc_id_i; + + /////////////////////////////////////////////// + // _ ___ ___ ___ ___ ____ // + // | | | \ \ / / | / _ \ / _ \| _ \ // + // | |_| |\ \ /\ / /| | | | | | | | | |_) | // + // | _ | \ V V / | |__| |_| | |_| | __/ // + // |_| |_| \_/\_/ |_____\___/ \___/|_| // + // // + /////////////////////////////////////////////// + // hwloop_cnt_mux always_comb begin : hwloop_cnt_mux - case (hwloop_cnt_mux_sel) - 2'b00: hwloop_cnt = 32'b0; - //2'b01: hwloop_cnt = immediate21z_id; // TODO: FIXME use correct immediate when adding hwloops - //2'b10: hwloop_cnt = immediate13z_id; - 2'b11: hwloop_cnt = operand_a_fw_id; - default: hwloop_cnt = 32'b0; + unique case (hwloop_cnt_mux_sel) + 2'b00: hwloop_cnt = 32'b0; + 2'b01: hwloop_cnt = imm_i_type; + 2'b10: hwloop_cnt = 32'b0; + 2'b11: hwloop_cnt = operand_a_fw_id; endcase; // case (hwloop_cnt_mux_sel) end // hwloop register id - assign hwloop_regid = instr[22:21]; // set hwloop register id + assign hwloop_regid = instr[8:7]; // rd contains hwloop register id + ////////////////////////////////////////////////////////////////// // _ _____ _ // @@ -359,10 +365,10 @@ module id_stage begin unique case (jump_in_id_o) `BRANCH_JAL: jump_target = current_pc_id_i + imm_uj_type; - `BRANCH_JALR: jump_target = regfile_data_ra_id + imm_i_type; // cannot forward rA as path too long + `BRANCH_JALR: jump_target = regfile_data_ra_id + imm_i_type; // cannot forward rs1 as path is too long `BRANCH_COND: jump_target = current_pc_id_i + imm_sb_type; default: jump_target = '0; - endcase // unique case (instr[6:0]) + endcase end assign jump_target_o = jump_target; diff --git a/riscv_core.sv b/riscv_core.sv index 14be7fb7..2ab9b99f 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -82,7 +82,7 @@ module riscv_core // IF/ID signals - logic [31:0] instr_rdata_id; // Instruction sampled nsude the PC stage + logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage logic [31:0] current_pc_if; // Current Program counter logic [31:0] current_pc_id; // Current Program counter logic force_nop_id; @@ -105,18 +105,18 @@ module riscv_core // Stalling - logic stall_if; // Stall instruction fetch(deassert request) - logic stall_id; // Stall PC stage and instr memory and data memo - logic stall_ex; // Stall EX Stage - logic stall_wb; // Stall write back stage + logic stall_if; // Stall instruction fetch(deassert request) + logic stall_id; // Stall PC stage and instr memory and data memo + logic stall_ex; // Stall EX Stage + logic stall_wb; // Stall write back stage logic core_busy; logic if_busy; // Register Data - logic [31:0] regfile_rb_data_ex; // from id stage to load/store unit and ex stage - logic [31:0] regfile_rb_data_wb; // from ex stage to sp register + logic [31:0] regfile_rb_data_ex; // from id stage to load/store unit and ex stage + logic [31:0] regfile_rb_data_wb; // from ex stage to sp register // ALU Control @@ -130,78 +130,71 @@ module riscv_core logic [1:0] alu_vec_ext_ex; // Multiplier Control - logic mult_en_ex; - logic [1:0] mult_sel_subword_ex; - logic [1:0] mult_signed_mode_ex; - logic mult_mac_en_ex; + logic mult_en_ex; + logic [1:0] mult_sel_subword_ex; + logic [1:0] mult_signed_mode_ex; + logic mult_mac_en_ex; // Register Write Control - logic [4:0] regfile_waddr_ex; - logic regfile_we_ex; - logic [4:0] regfile_waddr_fw_wb_o; // From WB to ID - logic regfile_we_wb; - logic [31:0] regfile_wdata; + logic [4:0] regfile_waddr_ex; + logic regfile_we_ex; + logic [4:0] regfile_waddr_fw_wb_o; // From WB to ID + logic regfile_we_wb; + logic [31:0] regfile_wdata; - logic [4:0] regfile_alu_waddr_ex; - logic regfile_alu_we_ex; + logic [4:0] regfile_alu_waddr_ex; + logic regfile_alu_we_ex; - logic [4:0] regfile_alu_waddr_fw; - logic regfile_alu_we_fw; - logic [31:0] regfile_alu_wdata_fw; + logic [4:0] regfile_alu_waddr_fw; + logic regfile_alu_we_fw; + logic [31:0] regfile_alu_wdata_fw; // CSR control - logic csr_access_ex; - logic [1:0] csr_op_ex; + logic csr_access_ex; + logic [1:0] csr_op_ex; - logic [1:0] csr_op; - logic [11:0] csr_addr; - logic [31:0] csr_rdata; - logic [31:0] csr_wdata; + logic [1:0] csr_op; + logic [11:0] csr_addr; + logic [31:0] csr_rdata; + logic [31:0] csr_wdata; // Data Memory Control: From ID stage (id-ex pipe) <--> load store unit - logic data_we_ex; - logic [1:0] data_type_ex; - logic data_sign_ext_ex; - logic [1:0] data_reg_offset_ex; - logic data_req_ex; - logic [31:0] data_addr_ex; - logic data_misaligned_ex; - logic data_ack_int; + logic data_we_ex; + logic [1:0] data_type_ex; + logic data_sign_ext_ex; + logic [1:0] data_reg_offset_ex; + logic data_req_ex; + logic [31:0] data_addr_ex; + logic data_misaligned_ex; + logic data_ack_int; // Signals between instruction core interface and pipe (if and id stages) - logic instr_req_int; // Id stage asserts a req to instruction core interface - logic instr_ack_int; // instr core interface acks the request now (read data is available) + logic instr_req_int; // Id stage asserts a req to instruction core interface + logic instr_ack_int; // instr core interface acks the request now (read data is available) // Interrupts - logic irq_enable; - logic [31:0] epcr; - logic save_pc_if; - logic save_pc_id; + logic irq_enable; + logic [31:0] epcr; + logic save_pc_if; + logic save_pc_id; // hwloop data from ALU - logic [31:0] hwlp_cnt_ex; // from id to ex stage (hwloop_regs) - logic [2:0] hwlp_we_ex; // from id to ex stage (hwloop_regs) - logic [1:0] hwlp_regid_ex; // from id to ex stage (hwloop_regs) - logic hwlp_wb_mux_sel_ex; // from id to ex stage (hwloop_regs) - logic [31:0] hwlp_start_data_ex; // hwloop data to write to hwloop_regs - logic [31:0] hwlp_end_data_ex; // hwloop data to write to hwloop_regs - logic [31:0] hwlp_cnt_data_ex; // hwloop data to write to hwloop_regs + logic [31:0] hwlp_cnt_ex; // from id to ex stage (hwloop_regs) + logic [2:0] hwlp_we_ex; // from id to ex stage (hwloop_regs) + logic [1:0] hwlp_regid_ex; // from id to ex stage (hwloop_regs) + logic hwlp_wb_mux_sel_ex; // from id to ex stage (hwloop_regs) + logic [31:0] hwlp_start_data_ex; // hwloop data to write to hwloop_regs + logic [31:0] hwlp_end_data_ex; // hwloop data to write to hwloop_regs + logic [31:0] hwlp_cnt_data_ex; // hwloop data to write to hwloop_regs - // spr access to hwloops - logic [31:0] sp_hwlp_start; - logic [31:0] sp_hwlp_end; - logic [31:0] sp_hwlp_cnt; - logic [2:0] sp_hwlp_we; - logic [1:0] sp_hwlp_regid; // Access to hwloop registers - logic [31:0] hwlp_start_data; - logic [31:0] hwlp_end_data; - logic [31:0] hwlp_cnt_data; - logic [2:0] hwlp_we; - logic [1:0] hwlp_regid; - + logic [31:0] hwlp_start_data; + logic [31:0] hwlp_end_data; + logic [31:0] hwlp_cnt_data; + logic [2:0] hwlp_we; + logic [1:0] hwlp_regid; // hwloop controller signals logic [`HWLOOP_REGS-1:0] [31:0] hwlp_start_addr; // to hwloop controller @@ -212,32 +205,32 @@ module riscv_core // Debug Unit - logic dbg_stall; - logic dbg_flush_pipe; - logic dbg_trap; - logic dbg_st_en; // single-step trace mode enabled - logic [1:0] dbg_dsr; // Debug Stop Register + logic dbg_stall; + logic dbg_flush_pipe; + logic dbg_trap; + logic dbg_st_en; // single-step trace mode enabled + logic [1:0] dbg_dsr; // Debug Stop Register - logic dbg_reg_mux; - logic dbg_sp_mux; - logic dbg_reg_we; - logic [11:0] dbg_reg_addr; - logic [31:0] dbg_reg_wdata; - logic [31:0] dbg_reg_rdata; - logic [31:0] dbg_rdata; + logic dbg_reg_mux; + logic dbg_sp_mux; + logic dbg_reg_we; + logic [11:0] dbg_reg_addr; + logic [31:0] dbg_reg_wdata; + logic [31:0] dbg_reg_rdata; + logic [31:0] dbg_rdata; - logic [31:0] dbg_npc; - logic dbg_set_npc; + logic [31:0] dbg_npc; + logic dbg_set_npc; `ifdef TCDM_ADDR_PRECAL - logic [31:0] alu_adder_ex; + logic [31:0] alu_adder_ex; `endif // Performance Counters - logic perf_jump; - logic perf_branch; - logic perf_jr_stall; - logic perf_ld_stall; + logic perf_jump; + logic perf_branch; + logic perf_jr_stall; + logic perf_ld_stall;