diff --git a/dv/uvm/core_ibex/sim_makefrag_gen.py b/dv/uvm/core_ibex/sim_makefrag_gen.py
index ea9003d1..8187580d 100755
--- a/dv/uvm/core_ibex/sim_makefrag_gen.py
+++ b/dv/uvm/core_ibex/sim_makefrag_gen.py
@@ -65,6 +65,21 @@ def gen_riviera_makefrag():
             'SIM_OPTS += {1}').format(riviera_compile_opts, riviera_sim_opts)
 
 
+def gen_questa_makefrag():
+    questa_compile_opts = run_ibex_config('questa_compile_opts', [
+        '--ins_hier_path', 'core_ibex_tb_top',
+        '--string_define_prefix', 'IBEX_CFG_'
+    ])
+
+    questa_sim_opts = run_ibex_config('questa_sim_opts', [
+        '--ins_hier_path', 'core_ibex_tb_top',
+        '--string_define_prefix', 'IBEX_CFG_'
+    ])
+
+    return ('COMPILE_OPTS += {0}'
+            'SIM_OPTS += {1}').format(questa_compile_opts, questa_sim_opts)
+
+
 def gen_xlm_makefrag():
     xlm_compile_opts = run_ibex_config('xlm_opts', [
         '--ins_hier_path', 'core_ibex_tb_top',
@@ -79,7 +94,12 @@ def main():
         'Generates a makefile fragment for use with the Ibex DV makefile that '
         'sets up sim specific variables'))
 
-    sim_fns = {'vcs': gen_vcs_makefrag, 'riviera': gen_riviera_makefrag, 'xlm': gen_xlm_makefrag}
+    sim_fns = {
+        'vcs': gen_vcs_makefrag,
+        'riviera': gen_riviera_makefrag,
+        'xlm': gen_xlm_makefrag,
+        'questa': gen_questa_makefrag
+        }
 
     argparser.add_argument('sim',
                            help='Name of the simulator',
diff --git a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index 81d2adf9..cfceb730 100644
--- a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -52,6 +52,25 @@
     wave_opts: >
       -ucli -do <cwd>/vcs.tcl
 
+- tool: questa
+  compile:
+    cmd:
+      - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
+      - "vlog -64
+              -access=rwc
+              -f ibex_dv.f
+              -sv
+              -mfcu -cuname design_cuname
+              +define+UVM_REGEX_NO_DPI
+              +define+UVM
+              -writetoplevels <out>/top.list
+              -l <out>/compile.log <cmp_opts>"
+  sim:
+    cmd: >
+      vsim -64 -c <cov_opts> -do "run -a; quit -f" +designfile -f <out>/top.list <sim_opts>  -sv_seed <seed> +access +r+w +UVM_TESTNAME=<rtl_test> +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log
+    cov_opts: >
+      -do "coverage save -onexit <out>/cov.ucdb;"
+
 - tool: dsim
   env_var: DSIM,DSIM_LIB_PATH
   compile:
diff --git a/util/ibex_config.py b/util/ibex_config.py
index 1aa6fcf7..1329e717 100755
--- a/util/ibex_config.py
+++ b/util/ibex_config.py
@@ -226,6 +226,12 @@ def main():
         SimOpts('riviera_compile_opts', 'Riviera compile',
                 lambda p, v: None,
                 lambda d, v: '+define+' + d + '=' + v, '/'),
+        SimOpts('questa_sim_opts', 'Questa simulate',
+                lambda p, v: '-g/' + p + '=' + v,
+                lambda d, v: None, '/'),
+        SimOpts('questa_compile_opts', 'Questa compile',
+                lambda p, v: None,
+                lambda d, v: '+define+' + d + '=' + v, '/'),
         SimOpts('xlm_opts', 'Xcelium compile',
                 lambda p, v: '-defparam ' + p + '=' + v,
                 lambda d, v: '-define ' + d + '=' + v, '.'),