diff --git a/dv/uvm/common/irq_agent/irq_master_driver.sv b/dv/uvm/common/irq_agent/irq_master_driver.sv
index 6911e55b..89709c68 100644
--- a/dv/uvm/common/irq_agent/irq_master_driver.sv
+++ b/dv/uvm/common/irq_agent/irq_master_driver.sv
@@ -40,10 +40,8 @@ class irq_master_driver extends uvm_driver #(irq_seq_item);
   endtask : get_and_drive
 
   virtual protected task reset_signals();
-    forever begin
-      @(posedge vif.reset);
-      drive_reset_value();
-    end
+    @(negedge vif.reset);
+    drive_reset_value();
   endtask : reset_signals
 
   virtual protected task drive_seq_item (irq_seq_item trans);
diff --git a/dv/uvm/env/core_ibex_env.sv b/dv/uvm/env/core_ibex_env.sv
index f2b04f10..3e20b3d9 100644
--- a/dv/uvm/env/core_ibex_env.sv
+++ b/dv/uvm/env/core_ibex_env.sv
@@ -25,9 +25,7 @@ class core_ibex_env extends uvm_env;
                           create("data_if_slave_agent", this);
     instr_if_slave_agent = ibex_mem_intf_slave_agent::type_id::
                            create("instr_if_slave_agent", this);
-    if (cfg.enable_irq_seq) begin
-      irq_agent = irq_master_agent::type_id::create("irq_agent", this);
-    end
+    irq_agent = irq_master_agent::type_id::create("irq_agent", this);
     // Create virtual sequencer
     vseqr = core_ibex_vseqr::type_id::create("vseqr", this);
   endfunction : build_phase
@@ -36,9 +34,7 @@ class core_ibex_env extends uvm_env;
     super.connect_phase(phase);
     vseqr.data_if_seqr = data_if_slave_agent.sequencer;
     vseqr.instr_if_seqr = instr_if_slave_agent.sequencer;
-    if (cfg.enable_irq_seq) begin
-      vseqr.irq_seqr = irq_agent.sequencer;
-    end
+    vseqr.irq_seqr = irq_agent.sequencer;
   endfunction : connect_phase
 
 endclass
diff --git a/dv/uvm/tb/core_ibex_tb_top.sv b/dv/uvm/tb/core_ibex_tb_top.sv
index 25959b00..0e42b906 100644
--- a/dv/uvm/tb/core_ibex_tb_top.sv
+++ b/dv/uvm/tb/core_ibex_tb_top.sv
@@ -98,6 +98,7 @@ module core_ibex_tb_top;
     rst_n = 1'b0;
     repeat(100) @(posedge clk);
     rst_n = 1'b1;
+    dut_if.debug_req = 1'b0;
   end
 
 endmodule