diff --git a/rtl/cve2_decoder.sv b/rtl/cve2_decoder.sv
index 37cdd569..372a2f9b 100644
--- a/rtl/cve2_decoder.sv
+++ b/rtl/cve2_decoder.sv
@@ -210,7 +210,7 @@ module cve2_decoder #(
     multdiv_operator_o    = MD_OP_MULL;
     multdiv_signed_mode_o = 2'b00;
 
-    rf_wdata_sel_o        = RF_WD_EX;
+    rf_wdata_sel_o        = $bits(rf_wdata_sel_o)'({RF_WD_EX});
     rf_we                 = 1'b0;
     rf_ren_a_o            = 1'b0;
     rf_ren_b_o            = 1'b0;
@@ -617,7 +617,7 @@ module cve2_decoder #(
         end else begin
           // instruction to read/modify CSR
           csr_access_o     = 1'b1;
-          rf_wdata_sel_o   = RF_WD_CSR;
+          rf_wdata_sel_o   = $bits(rf_wdata_sel_o)'({RF_WD_CSR});
           rf_we            = 1'b1;
 
           if (~instr[14]) begin
@@ -643,7 +643,7 @@ module cve2_decoder #(
           rf_ren_a_o            = x_issue_resp_register_read_i[0];
           rf_ren_b_o            = x_issue_resp_register_read_i[1];
           rf_we                 = x_issue_resp_writeback_i;
-          rf_wdata_sel_o        = RF_WD_COPROC;
+          rf_wdata_sel_o        = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
         end
 
       end
diff --git a/rtl/cve2_id_stage.sv b/rtl/cve2_id_stage.sv
index 666cfc73..6f4d727f 100644
--- a/rtl/cve2_id_stage.sv
+++ b/rtl/cve2_id_stage.sv
@@ -418,7 +418,7 @@ module cve2_id_stage #(
 
   // Register file write data mux
   always_comb begin : rf_wdata_id_mux
-    unique case (rf_wdata_sel)
+    unique case ($bits(rf_wd_sel_e)'({rf_wdata_sel}))
       RF_WD_EX:     rf_wdata_id_o   = result_ex_i;
       RF_WD_CSR:    rf_wdata_id_o   = csr_rdata_i;
       RF_WD_COPROC: rf_wdata_id_o   = XInterface? x_result_i.data : result_ex_i;