From 71cb9878f468974c3171f610b9c47c70d5137fad Mon Sep 17 00:00:00 2001 From: Pasquale Davide Schiavone Date: Mon, 15 Jan 2018 15:25:54 +0100 Subject: [PATCH] update headers --- zeroriscy_alu.sv | 14 +++++++------- zeroriscy_compressed_decoder.sv | 2 +- zeroriscy_controller.sv | 2 +- zeroriscy_core.sv | 2 +- zeroriscy_cs_registers.sv | 8 ++++---- zeroriscy_debug_unit.sv | 2 +- zeroriscy_decoder.sv | 4 ++-- zeroriscy_ex_block.sv | 2 +- zeroriscy_fetch_fifo.sv | 2 +- zeroriscy_id_stage.sv | 4 ++-- zeroriscy_if_stage.sv | 2 +- zeroriscy_int_controller.sv | 2 +- zeroriscy_load_store_unit.sv | 4 ++-- zeroriscy_multdiv_fast.sv | 2 +- zeroriscy_multdiv_slow.sv | 2 +- zeroriscy_prefetch_buffer.sv | 6 +++--- zeroriscy_register_file.sv | 2 +- zeroriscy_register_file_ff.sv | 2 +- zeroriscy_tracer.sv | 2 +- 19 files changed, 33 insertions(+), 33 deletions(-) diff --git a/zeroriscy_alu.sv b/zeroriscy_alu.sv index 7bbc40b4..47a82f15 100644 --- a/zeroriscy_alu.sv +++ b/zeroriscy_alu.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -56,7 +56,7 @@ module zeroriscy_alu begin : g_revloop assign operand_a_rev[k] = operand_a_i[31-k]; end - endgenerate + endgenerate ///////////////////////////////////// @@ -68,7 +68,7 @@ module zeroriscy_alu // // ///////////////////////////////////// - logic adder_op_b_negate; + logic adder_op_b_negate; logic [32:0] adder_in_a, adder_in_b; logic [31:0] adder_result; @@ -104,7 +104,7 @@ module zeroriscy_alu assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); assign adder_result = adder_result_ext_o[32:1]; - + assign adder_result_o = adder_result; //////////////////////////////////////// @@ -188,7 +188,7 @@ module zeroriscy_alu assign is_equal = (adder_result == 32'b0); assign is_equal_result_o = is_equal; - + // Is greater equal always_comb @@ -199,7 +199,7 @@ module zeroriscy_alu is_greater_equal = operand_a_i[31] ^ (cmp_signed); end - // GTE unsigned: + // GTE unsigned: // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0 // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0 // (a[31] == 1 && b[31] == 0) => 1 @@ -277,5 +277,5 @@ module zeroriscy_alu default: ; // default case to suppress unique warning endcase end - + endmodule diff --git a/zeroriscy_compressed_decoder.sv b/zeroriscy_compressed_decoder.sv index b76612b5..4a5db030 100644 --- a/zeroriscy_compressed_decoder.sv +++ b/zeroriscy_compressed_decoder.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_controller.sv b/zeroriscy_controller.sv index d56963f3..7456e9d2 100644 --- a/zeroriscy_controller.sv +++ b/zeroriscy_controller.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_core.sv b/zeroriscy_core.sv index 8e44dc18..10fdaee0 100644 --- a/zeroriscy_core.sv +++ b/zeroriscy_core.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_cs_registers.sv b/zeroriscy_cs_registers.sv index ec36d79f..8f284279 100644 --- a/zeroriscy_cs_registers.sv +++ b/zeroriscy_cs_registers.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -148,7 +148,7 @@ module zeroriscy_cs_registers //////////////////////////////////////////// // ____ ____ ____ ____ // // / ___/ ___|| _ \ | _ \ ___ __ _ // - // | | \___ \| |_) | | |_) / _ \/ _` | // + // | | \___ \| |_) | | |_) / _ \/ _` | // // | |___ ___) | _ < | _ < __/ (_| | // // \____|____/|_| \_\ |_| \_\___|\__, | // // |___/ // @@ -179,7 +179,7 @@ module zeroriscy_cs_registers // mhartid: unique hardware thread id 12'hF14: csr_rdata_int = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]}; - + default: ; endcase end @@ -323,7 +323,7 @@ module zeroriscy_cs_registers // assign external performance counters generate genvar i; - for (i = 0; i < N_EXT_CNT; i++) + for (i = 0; i < N_EXT_CNT; i++) begin : g_extcounters assign PCCR_in[N_PERF_COUNTERS - N_EXT_CNT + i] = ext_counters_i[i]; end diff --git a/zeroriscy_debug_unit.sv b/zeroriscy_debug_unit.sv index 29639704..715fb92a 100644 --- a/zeroriscy_debug_unit.sv +++ b/zeroriscy_debug_unit.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_decoder.sv b/zeroriscy_decoder.sv index 4415c69b..27199213 100644 --- a/zeroriscy_decoder.sv +++ b/zeroriscy_decoder.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -220,7 +220,7 @@ module zeroriscy_decoder alu_operator_o = ALU_ADD; regfile_we = 1'b0; end - + end diff --git a/zeroriscy_ex_block.sv b/zeroriscy_ex_block.sv index 5790e207..855b2375 100644 --- a/zeroriscy_ex_block.sv +++ b/zeroriscy_ex_block.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_fetch_fifo.sv b/zeroriscy_fetch_fifo.sv index 79107371..9bf82559 100644 --- a/zeroriscy_fetch_fifo.sv +++ b/zeroriscy_fetch_fifo.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_id_stage.sv b/zeroriscy_id_stage.sv index b7b73827..6db041c3 100644 --- a/zeroriscy_id_stage.sv +++ b/zeroriscy_id_stage.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -759,7 +759,7 @@ module zeroriscy_id_stage // stall control assign id_ready_o = (~load_stall) & (~branch_stall) & (~jump_stall) & (~multdiv_stall); - + assign id_valid_o = (~halt_id) & id_ready_o; diff --git a/zeroriscy_if_stage.sv b/zeroriscy_if_stage.sv index 26f09378..c9da5b77 100644 --- a/zeroriscy_if_stage.sv +++ b/zeroriscy_if_stage.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_int_controller.sv b/zeroriscy_int_controller.sv index f8806fa4..34df6a4a 100644 --- a/zeroriscy_int_controller.sv +++ b/zeroriscy_int_controller.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_load_store_unit.sv b/zeroriscy_load_store_unit.sv index 34935318..14d70850 100644 --- a/zeroriscy_load_store_unit.sv +++ b/zeroriscy_load_store_unit.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -410,7 +410,7 @@ module zeroriscy_load_store_unit end else begin //if first part rvalid is NOT received - //the second grand is not received either by protocol. + //the second grand is not received either by protocol. //stay here NS = WAIT_RVALID_MIS; end diff --git a/zeroriscy_multdiv_fast.sv b/zeroriscy_multdiv_fast.sv index cecd50bc..01e0e6d2 100644 --- a/zeroriscy_multdiv_fast.sv +++ b/zeroriscy_multdiv_fast.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_multdiv_slow.sv b/zeroriscy_multdiv_slow.sv index 81a93a08..74e604e7 100644 --- a/zeroriscy_multdiv_slow.sv +++ b/zeroriscy_multdiv_slow.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_prefetch_buffer.sv b/zeroriscy_prefetch_buffer.sv index 198bbdc9..d92939c5 100644 --- a/zeroriscy_prefetch_buffer.sv +++ b/zeroriscy_prefetch_buffer.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -149,7 +149,7 @@ module zeroriscy_prefetch_buffer if (branch_i) begin instr_addr_o = addr_i; addr_valid = 1'b1; - end + end if(instr_gnt_i) NS = WAIT_RVALID; @@ -185,7 +185,7 @@ module zeroriscy_prefetch_buffer if (branch_i) begin addr_valid = 1'b1; NS = WAIT_ABORTED; - end + end end end else begin // just wait for rvalid and go back to IDLE, no new request diff --git a/zeroriscy_register_file.sv b/zeroriscy_register_file.sv index 84d27e7c..6a888d1a 100644 --- a/zeroriscy_register_file.sv +++ b/zeroriscy_register_file.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_register_file_ff.sv b/zeroriscy_register_file_ff.sv index 60b38ef6..33bd268a 100644 --- a/zeroriscy_register_file_ff.sv +++ b/zeroriscy_register_file_ff.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/zeroriscy_tracer.sv b/zeroriscy_tracer.sv index 17e53bdf..9c4af464 100644 --- a/zeroriscy_tracer.sv +++ b/zeroriscy_tracer.sv @@ -1,4 +1,4 @@ -// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at